Test‐Generation‐Based Fault Detection in Analog VLSI Circuits Using Neural Networks

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece‐wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.     

Test of a switched-capacitor ADC by a built-in charge sensor

A test methodology for switched capacitor circuits is described. The test approach uses a built-in sensor to analyze the charge transfer inside the circuit under test (CUT). The test methodology is applied to a 10-bit algorithmic analog to digital converter to obtain the static linearity and to the simulated fault coverage figures taking into account a catastrophic fault model. The goodness of the charge sensor has been experimentally evaluated with an SC integrator for fault detection and built-in sensor influence on the CUT performance.     

A realistic defect oriented testability methodology for analog circuits

Owing to the non-binary nature of their operation, analog circuits are influenced by process defects in a different manner compared to digital circuits. This calls for a careful investigation into the occurrence of defects in analog circuits, their modeling related aspects and their detection strategies. In this article, we demonstrate with the help of a real CMOS circuit that simple test stimuli, like DC, transient and AC, can detect most of the modeled process defects. Silicon devices tested with the proposed test methodology demonstrate the effectiveness of the method. Subsequently, the proposed test method is implemented in production test environment along with the conventional test for a comparative study. This test methodology is structured and simpler, therefore results in substantial test cost reduction.     

A unified approach for fault simulation of linear mixed-signal circuits

The rapidly evolving role of analog signal processing has spawned off a variety of mixed-signal circuit applications. The integration of the analog and digital circuits has created a lot of concerns in testing these devices. This paper presents an efficient unified fault simulation platform for mixed-signal circuits while accounting for the imprecision in analog signals. While the classical stuck-at fault model is used for the digital part, faults in the analog circuit cover catastrophic as well as parametric defects in the passive and active components. A unified framework is achieved by combining a discretized representation of the analog circuit with the Z-domain representation of the digital part. Due to the imprecise nature of analog signals, an arithmetic distance based fault detection criterion and a statistical measure of digital fault coverage are proposed.This research was supported by the National Science Foundation under grant MIP-9222481.     

基于噪声测量的模拟电路故障分析研究

模拟电路故障检测是在当前电子计算机技术不断完善的背景下,基于集成电路故障检测困难发展而来的新型电路检测模式。对于模拟电路来说,故障检测是一个难题,在此基础上,噪声检测在近年来开始逐渐兴起。为了进一步探究利用噪声进行模拟电路故障检测的方法,文中从模拟电路故障检测的背景展开论述,阐述了传统和现代两种不同的模拟电路故障检测方式,分析了利用噪声原理进行模拟电路故障检测的优势和特点,并且详细论述了当前利用RS运算符进行噪声故障检测的计算方法,并对利用噪声进行模拟电路故障检测的步骤做出了详细的阐述。     

基于PSPICE进行模拟电路故障建模的方法

文章研究了基于PSPICE的模拟电路故障仿真中的故障建模问题。提出了用故障字典法诊断模拟电路硬故障时,基本元件的物理故障和集成电路的功能故障进行故障建模的方法。在直流诊断和交流诊断中，故障建模的方法有所不同。最后用例子说明了这种方法的可行性。     

Analog Automatic Test Pattern Generation for Quasi-Static Structural Test

A new approach for structural, fault-oriented analog test generation methodology to test for the presence of manufacturing-related defects is proposed. The output of the test generator consists of optimized test stimuli, fault coverage and sampling instants that are sufficient to detect the failure modes in the circuit under test. The tests are generated and evaluated on a multistep ADC taking into account the potential fault masking effects of process spread on the faulty circuit responses. Similarly, the test generator results offer indication for the circuit partitioning within the framework of circuit performance, area and testability.     

基于闭环集成运放的模拟电路模块级软故障诊断

基于斜率故障模型,提出了一种诊断模拟电路中基于闭环集成运算放大器的模块级软故障的字典法.在由闭环运放组成的模拟电路中,通过对电路以闭环运放及与其输入直接相连的元件看作一个整体划分模块,对各个模块中的任一元件或进行宏模型替代之后的运放等效电路,利用电路中的两节点电压增量计算出的斜率作为统一故障特征,建立故障字典,实现电路中相应模块包含的运放和所有元件的软故障诊断.给出了运放的等效宏模型和模块级软故障的诊断步骤,并用仿真实例证明了该诊断方法的有效性.     

A New Analog Circuit Fault Diagnosis Method Based on Improved Mahalanobis Distance

This paper presents a new analog circuit fault diagnosis method based on improved Mahalanobis Distance. The Mahalanobis Distance is improved according to the characteristics of analog circuit, and then introduced into analog circuit fault detection. First, the circuit testability was analyzed, and the relation of ambiguity groups was determined on the basis of the test matrix, and then the separable potential faulty components under the assumption of single fault were also determined. Finally, the suspicious components could be classified using the improved Mahalanobis Distance according to the feature values of the test points, so as to reduce the number of classes and enhance the speed when classifying faults. The experiment shows that the method can achieve fast analog circuit fault diagnosis and better results of analog circuit diagnosis detection.     

模拟电路故障诊断的PSpice与Matlab仿真分析研究

根据模拟电路故障诊断中的测前模拟诊断SBT法,本文采用PSpice对待测电路CUT故障进行模拟仿真,通过小波包分析和信息熵方法提取故障电路输出信号的特征向量,利用Matlab设计的神经网络算法构建故障分类器并对电路故障进行识别与诊断。仿真实验结果表明将PSpice与Matlab相结合的诊断方法能够有效地诊断模拟电路故障,为模拟电路故障诊断的教学和科研提供参考。     

模拟电路故障诊断的结点电压灵敏度比值法

在证明线性电路中结点电压变化量比值等于结点电压灵敏度比值的基础上,提出了结点电压灵敏度比值法,通过结点电压变化量比值和结点电压灵敏度比值的比对确定电路的故障元件。理论分析和实验结果表明,该方法算法简单、诊断速度快,在可测点受限条件下具有较高的诊断精度,特别适合大规模线性模拟电路的故障诊断和测试。     

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

基于仿真和编码理论的数模混联电路故障诊断方法研究

数模混联电路的设计被广泛运用于各种电路系统。而模拟电路和数字电路在故障模式、测试方法上的显著差别给数模混联电路的测试带来了很大困难。基于对输出电平的16进制编码,将传统的故障字典法推广到可以诊断数模混联电路的新故障字典法。利用EDA的辅助分析,在PSpice仿真环境下,从故障建模、故障注入,到电路仿真,数据分析,再到建立故障字典以及故障诊断,建立了一套有效的基于仿真的数模混联电路的测试诊断方法。并给出了仿真实例,对数、模混联电路的故障诊断具有推广意义。     

Fault Models and Test Generation for OpAmp Circuits—The FFM

The analog VLSI technology processes are reaching the matureness, nevertheless, there is a big constraint, regarding their use on complex electronic products: the test. The Design for Testability paradigm was developed to permit the test plan implementation early in the design cycle. However to succeed onto this strategy, the fault simulation should be carried out in order to evaluate appropriate test patterns, fault grade and so forth. Consequently adequate fault models must be established. Due to the lack of fault models, suitable to fault simulation on OpAmps, we propose in this work a methodology for Functional Fault Modeling-FFM, and some methods for test generation. A fault dictionary for OpAmps is built and a procedure for compact test vector construction is proposed. The results have shown that high level OpAmp requirements, as slew-rate, common mode rejection ration etc., can be checked by this approach with good compromise between the fault modeling problem, the analog nature of the circuit and the circuit complexity by itself.     

基于ELM网络的模拟电路故障诊断

由于模拟电路的非线性、易受外界干扰等因素,模拟电路的故障在设备总故障中占很大的比例。因此,对模拟电路的故障诊断技术进行深入研究具有很重要的意义。文中针对雷达电路的故障进行快速有效的特征提取,采用神经网络中ELM网络建立诊断系统结构,并通过对具体电路的仿真,输出ELM网络的诊断结果。实际应用表明,该系统具有操作简便、诊断精度高的特点,达到了设计要求。     

基于电子电路故障的诊断基本技术

电子电路是由具有特定功能的电子元器件组合成的,在电子电路中每个元器件都具备自己特定的作用。一旦某个元件发生损坏,电子电路的功能一定会受到影响,发生变化。这种电路系统丧失规定的功能的现象就被称之为电路故障。本文通过电子电路故障类型的分类着手,进而分析了电子电路故障诊断的基本技术,接着阐述了模拟电路诊断的方法,进而了解了数字电路故障测试的基本技术。希望这一项研究对今后这一课题的研究有借鉴价值和参考作用。     

基于SOFM网络和异质信息融合的模拟电路诊断

大规模集成电路的发展使得传统的接触法测试在某些场合受到了限制．针对其造成的电量测试信息不足的问题,文中融合电量信息和非电量信息作为故障特征信息,应用自组织特征映射（SOFM）神经网络对模拟电路进行故障诊断．提取电路工作时的电压和温度信息作为故障特征信息,经预处理后作为样本输入给SOFM神经网络进行电路故障诊断．通过输出层各神经元的竞争,得到获胜神经元,从而对样本数据进行故障识别分类．仿真结果表明,应用所提融合诊断方法提高了诊断准确率．     

A novel method for fault diagnosis of analog circuits based on WP and GPNN

A novel method for fault diagnosis of analog circuits with tolerance based on wavelet packet (WP) decomposition and probabilistic neural networks using genetic algorithm (GPNN) is proposed in this paper. The fault feature vectors are extracted after feasible domains on the basis of WP decomposition of responses of a circuit being solved. Then by fusing various uncertain factors into probabilistic operations, GPNN methods to diagnose faults are proposed whose parameters and structure obtained form genetic optimisations resulting in best detection of faults. Finally, simulations indicated that GPNN classifiers are correct 7% more than BPNN of the test data associated with our sample circuits.