Design tools for analog and digital ICs

The era of the system on a chip is well under way, bringing in its train new headaches for the IC design engineer. One reason for the difficulties is that such systems are increasingly being built up from an assembly of pre-designed components-so-called intellectual property (IP) or virtual components-which sometimes come from diverse sources. Further, a decision is often demanded very early in the design process as to which functions will be executed in hardware and which in software, after which concurrent design of both components is necessary to ensure they work together. Then, too, the shrinking dimensions of the structures that make up the chip are compelling consideration of their physical and electrical properties in much more detail than ever before. All the while, market pressures are forcing companies to design and verify application-specific ICs with millions of logic gates in less and less time     

数字PID控制在运动控制系统中的应用

在半导体设备运动过程中,有效的调节数字PID控制参数可以提高设备运动的稳定性和可靠性,利用积分分离的算法来实现具有最佳组合的PID控制。     

模拟与数字IC并驾齐驱

据Databeans公司最近对模拟IC市场调研报告显示．全球模拟市场从2003年-2009年复合增长率为12％。这个数字要高出其它产品的增长率。这也预示着高性能模拟市场在今后的一段时间里发展潜力巨大。在美国半导体工业协会(SIA)的市场统计中也有数据显示．在未来的2-3年发展中，模拟市场的发展将快速超越数字求场。     

Defect level for non-equiprobable faults in digital ICs

Common measures of test efficiency are the fault coverage and the defect level for a given product yield. An extension of the well known formula relating these three quantities to the case of general non-equiprobable faults has been derived by exploiting the concept of critical area. This also leads to a more meaningful definition of fault coverage.<>     

Analog phase measuring circuit for digital CMOS ICs

A circuit measuring the phase of incoming asynchronous signals relative to the system clock in digital signal processing is described. The system clock can be in the range from 10 to 20 MHz, as is typical for video signal processing applications. As a reference in the asynchronous signal the positive or negative slope is taken. Its phase is measured with a resolution of 1/32 of a system clock cycle (approximately 1.5 to 3 ns). Pure digital CMOS technology without precision components is used, to enable combined integration on processor chips. Timing precision (jitter) is better than 200 ps without any adjustments. One external capacitor is needed     

Special ICs in digital switching-an overview

Traces the influence of special-purpose integrated and LSI circuits in digital switching systems. The existence of custom digital chips, codecs and filters, and high- and low-voltage analog cross-point arrays is related to the choice between alternative architectures. Recent trends toward replacing mature components such as transformers by subscriber line interface circuits (SLICs) are outlined.     

Microprocessors in a digital system design curriculum

For some time now, the notion that "an algorithm is an algorithm" has been emphasized in digital system design. In approaching such design problems, the question of hardware versus software implementation of the algorithm should be left to the last. In fact, such approaches have not been viable until the advent of the microprocessor, and software design has seemingly gone its own way independently of hardware design. But has it really? It is becoming increasingly clear that structured approaches to the design of digital systems, hardware or software, have evolved in both areas and are virtually identical. It is possible to teach a course on digital system design so that a diverse group can understand and learn from each other's background. It is also possible to have a laboratory wherein realistic projects can be undertaken. In this paper, the digital system design sequence and laboratory facilities at Northwestern University will be discussed. Also, desirable design tools will be postulated.     

GaAs digital dynamic ICs for applications up to 10 Ghz

To evaluate the potentiality of GaAs MESFETs as transmitting gates, dynamic TT~ flip-flops have been fabricated using a self-aligned planar process. The maximum operating frequency is 10.2 GHz, which is the best speed performance ever reported for a digital circuit. The performance of the transmitting gates within the circuits are discussed in detail. Speed improvement and topological simplification of fully static LSI subsystems are investigated.     

基于全数字伺服控制单元的位置控制系统设计

阐述了基于全数字伺服控制单元的位置控制系统的特点,并且对运动控制算法进行分析,介绍了欧姆龙公司最新推出的新型全数字交流伺服控制单元MCW151的原理和性能,阐述基于交流伺服控制单元MCW151的位置控制系统的特点,并且设计了一种新的高精度伺服控制系统。     

Collector-top GaAs/AlGaAs heterojunction bipolar transistors for high-speed digital ICs

GaAs/AlGaAs collector-top heterojunction bipolar transistors with magnesium and phosphorus double-implanted external bases were fabricated. A cutoff frequency of 17 GHz and a gate delay time of 63 ps for DCTL were obtained. These results indicate the potential of collector-top HBTs for high-speed ICs.     

A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs

Process-induced and environmental fluctuations play an important role in the design process for modern high-performance integrated circuits. The conventional principle of considering the verification of worst-case requirements reduces the performance that can potentially be achieved by circuits and technology. This paper presents a new mechanism that permits the compensation of random independent delay fluctuations due to environmental factors. It shows that it is significantly possible to reduce the latency time of a circuit even for a moderate length of pipeline stages.     

48-GHz digital ICs and 85-GHz baseband amplifiers usingtransferred-substrate HBT's

Using substrate transfer processes, we have fabricated heterojunction bipolar transistors with submicrometer emitter-base and collector-base junctions, minimizing RC parasitics and increasing f_max to 500 GHz. The process also provides a microstrip wiring environment on a low-ϵ_r dielectric substrate. First design iterations of emitter-coupled-logic master-slave flip-flops exhibit 48 GHz maximum clock frequency when connected as static frequency dividers. Baseband amplifiers have been demonstrated with bandwidths up to 85 GHz     

Noise-induced error rate as limiting factory for energy per operation in digital ICs

Due to the steady progress in computer technologies over the past years, the physical limits of the energy required per logical operation are assuming increased practical significance. Whereas earlier studies have considered only the elementary energies (e.g., kT, hv) or the power consumption during gate switching, the present work takes account of the random errors induced in an idealized gate by noise. The dependence of the minimum energy W/SUB I/ on the permissible error rate A is calculated for thermal noise. The result obtained, W/SUB I//spl ap/3.9 kT in (5A)/SUP -1/ for 10/SUP -7/>A>10/SUP -23/, is discussed regarding other limits in semiconductor circuits.     

Crosstalk effects in mixed-signal ICs in deep submicron digital CMOS technology

This paper illustrates the crosstalk phenomenon and its impact on the design of mixed analog/digital circuits with high accuracy specifications. Generation of digital disturbs, propagation through the substrate, and effects on analog devices are considered, with particular emphasis on integrated circuits realized on heavily doped substrate, where traditional shielding is less effective. Techniques to reduce analog/digital crosstalk are reviewed and discussed. A simple modeling approach is presented, suitable for the analysis of crosstalk effects using a conventional electrical simulator (SPICE). Experimental results on a test chip are presented to validate the modeling approach.     

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.     

监控电池供电设备的电源管理芯片

为了保证带有微处理器(μP)系统能够正常的工作,当通电、断电,以及进入或退出关机和睡眠状态时,都需要对电源进行监控管理。电源管理芯片具不仅具有通电复位的功能,还可以提供附加的功能,例如备用电池的管理、存储器的写保护、电源低(Low-Line)早期报警或软件看门狗等。图1表示由电源管理芯片ICI(MA×807)管理μP系统的电源。     

Economical Failure Analysis for Microprocessors

A technique is presented for isolating the failing node within a microprocessor type chip. The computer-driven production-tester is used to identify the failing instructions prior to failure analysis. In the laboratory, simple two or three instruction test-patterns are programmed into a n × 16 (1 ? n ? 255) memory buffer and then clocked into the device under test in an endless repetitive loop. Internal microprobing is then used to check the internal control lines and registers to localize the failure. The technique has been used to isolate failure mechanisms on wafers and in packaged devices from a variety of sources, including environmental stress failures and field returns. The article demonstrates the feasibility of performing efficient, accurate, and low cost failure analysis on microprocessors. The essential features are an efficient laboratory administrative system, concise and accurate input documentation, knowledge of the internal workings of each chip, the memory buffer-testing technique, and an accurate microprobing capability. Results at Mostek indicate that a single, well trained technician with occasional engineering supervision can successfully analyze an average of two moderately difficult failing devices per day. Since a usual sample of devices will contain some simple failures, an average daily throughput of about four to five devices has been realized. The capital outlay (less than $1000) for the equipment (exclusive of pre-existing lab equipment such as an oscilloscope) has been confined to the construction and components cost of the memory buffer and its associated interconnect wiring.     

微处理器发展及应用误区分析

简要介绍了通用CPU、DSP和FPGA等3大类微处理器的发展历史.针对现在由于各种微处理器部分功能重叠,各生产厂商宣传误导造成了设计师在实际应用时选型困难.通过这3大类处理器的实际应用,分析了现在比较流行的对于各种处理器选型和发展的认识误区,并给出一定的见解.最后结合实际的使用范围,讨论在各种工程应用中适用的处理器组合.     

A sensitivity optimization approach to design of a disturbanceobserver in digital motion control systems

This paper is concerned with a digital design methodology for the disturbance observer. The controller (disturbance observer) is designed such that the system sensitivity function is made to match a chosen target sensitivity function by numerical optimization. One advantage of the proposed design method is that the tradeoff between command following, disturbance suppression, and measurement noise rejection is made transparent in the process of the control system design. This allows the system designer to bypass the effort of obtaining a highly accurate system model. Another aim of this research, relative to previous works, is to study how the design specifications can be best structured in the digital filter (a main component of the disturbance observer) for easy implementation. The robust feedback controller, designed in the velocity loop, is used in conjunction with a feedback controller located in the position loop and a feedforward controller acting on the desired output to construct a control structure for high-speed/high-accuracy motion control. Simulation and experiments applied to a high-speed XY table designed for micro positioning demonstrate the effectiveness of the proposed controller     

Motion detection and motion compensation for digital subtraction angiography image enhancement

For the enhancement of digital subtraction angiography (DSA) images, registration of mask and contrast image prior to subtraction is a pre-requisite. One of the main requirements of this task is that the region-of-interest used for the calculation of the registration parameters should contain the vascular structures of interest. This, however, is also one of the main problems in DSA because the contrasted vascular structures can be regarded as a distortion that makes the images to be compared dissimilar. In this paper we present a comparison between three frequently used similarity measures and histogram-based similarity measures. This reveals the advantages of the latter. The data-driven approach is especially suitable for registration of two images which are identical except for some structures visible in one but not in the other image. Based on an energy similarity measure, a motion vector field is obtained by template matching, which gives a set of homologous landmarks or control points in the mask and contrast image. A point-based registration is performed fitting the parameter of an appropriate transformation for patient motion correction. An affine and an elastic transformation are compared for an abdominal fluoroscopic scene.