A high-performance lateral PNP transistor structure

This paper proposes a novel lateral PNP-type structure that is fully compatible with existing single-polysilicon BiCMOS processes and offers a valid alternative to shallow polysilicon emitter transistors. We have used both an analytical approach and a more accurate computer-aided design, obtaining 0.9 GHz and 4.4 GHz cutoff frequency for 2 μm and 0.8 μm minimum feature transistors, respectively     

A column-base InP lateral bipolar transistor

An InP lateral bipolar transistor has been successfully fabricated on a semi-insulating substrate by implanting Si⁺ as the emitter and collector contacts and Mg⁺ as the column base. An array of 33 1-μm-diameter columns with 1-μm separation between each was formed between the emitter-collector spacing of 3 μm. A current gain of 290 was obtained at 77 K; it was over 12 at room temperature     

The lateral punch-through transistor

Operation of a diffused-gate, lateral punch through transistor has been demonstrated. Operation is similar to the static induction transistor, and the device can be used in planar integrated circuits. Current flow in this lateral device obeys the space charge limited conduction law over a wide range of currents, and the drain current exhibits a negative temperature coefficient.     

A silicon medium-power transistor for high-current high-speed switching applications

A diffused base, diffused emitter, n-p-n silicon switching transistor has been developed for high-current applications such as switching magnetic memories. The transistor is designed to operate as a switch at the 0.75- ampere level. For a collector current of 0.75 ampere, the large signal current gain is 20 and the saturation voltage drop 4 volts. The breakdown voltages are 75 volts collector-to-base, and 6 volts emitter-to-base. The unit shows fast switching characteristics. The rise, storage, and fall times are each of the order of 0.1 µsec. It has a common emitter unity gain frequency greater than 50 Mc. The transistor employs a localized emitter produced by photoresist techniques and oxide masked diffusion. Lead attachment is accomplished by compression bonding. The silicon wafer is bonded through a molybdenum intermediary to a massive copper stud. The design theory of the device, and the variation of device characteristics with temperature are given. The applicability of this devices to RF amplifier service is also discussed.     

A new epitaxial lateral overgrowth silicon bipolar transistor

A new device structure and method of fabricating a silicon bipolar transistor is proposed. The device has reduced collector parasitic capacitance and resistance as compared to other advanced bipolar technologies. By using selective and lateral epitaxial overgrowth techniques the buried (N+) layer is not necessary. Two-dimensional computer simulations show theC_{CS} times R_{C}product to be reduced by a factor of 5.45 along with reduced CCB.     

A high-performance lateral bipolar transistor fabricated on SIMOX

Double-diffused, lateral n-p-n bipolar transistors were fabricated in a simple CMOS-like process using SIMOX silicon-on-insulator (SOI) substrates. Excellent device characteristics were achieved, with peak h_FE=120, BV_CEO=10 V, and peak f_t=4.5 GHz. The f_t versus BV _CEO trade-off was studied as a function of n ^- collector width. f_t>25 GHz is predicted for this structure with an improved device layout and optimized basewidth. This process may be easily extended in order to fabricate complementary BJTs in a C-BiCMOS thin-film SOI technology     

A high-performance lateral geometry transistor for complementary integrated circuits

The lateral geometry transistor has shown itself to be highly useful in the realization of low-frequency integrated circuits. This simple structure has been limited essentially to dc applications, however, by bandwidth and switching time performance. The p-n-p device to be described in this paper substantially overcomes these deficiencies by the addition of an n+ diffusion directly beneath the emitter region. As a result of the steeper gradient at the bulk, or planar, portion of the emitter-base junction, injection occurs primarily near the surface. It is possible to control the dimensions of the buried layer such that injection of carriers greater than a few micrometers from the collector will be minimized. A further consequence of the n+ region is the introduction of a graded base such that minority carrier transport is enhanced. The improved transistor structure has demonstrated the feasibility of obtaining an f_{T} of 10 MHz to 20 MHz at collector currents of 100 µA and rise, fall, and storage times in the tens of nanoseconds.     

A simple technique for improving lateral p-n-p transistor performance

Outlines a simple and elegant method that would simultaneously increase the current gain, frequency response, and voltage capability of the lateral p-n-p transistor. This is accomplished by introducing aluminium in the collector regions of the device.     

Bipolar transistor with self-aligned lateral profile

This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-poly-refractory metal emitter stack to reduce the emitter resistance, a high-performance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications.     

A lateral silicon-on-insulator bipolar transistor with a self-aligned base contact

A novel lateral bipolar transistor structure in silicon-on-insulator (SOI) is presented. The structure allows for a minimum geometry base width yet still provides for a metal contact to the entire base region. Fabricated transistors exhibit a base resistance of less than 20 Ω.     

Formal design procedures for pass transistor switching circuits

Two formal design techniques are presented to realize pass logic networks in NMOS and CMOS technologies. The first technique uses a modified Karnaugh map minimization procedure, which can be effective tool for the design of networks up to five or six variables. For networks involving more than six variables, an algorithmic procedure is developed by modifying the conventional Quine-McCluskey approach. The savings in silicon area depends on the transistor count as well as the interconnect structure. Maximum topograph regularity for an array of pass transistors can be achieved in the intersection of the set of control variables with the set of pass variables in a null set. This allows the pass variables and the control variables to flow at right angles to each other. This requirement may increase the transistor count in the design, hence there is a tradeoff between topological regularity and transistor count. Cells drawn in CMOS and NMOS are compared.     

Design and characterization of a step-recovery switching transistor

Fast rise time pulses can be generated with a special high-frequency silicon transistor structure having a collector impurity profile designed to control charge storage in the collector. When switched out of saturation it operates in a manner analogous to a step-recovery diode. The theory of operation is discussed along with the design and fabrication of the diffused impurity profiles. Its unique geometry combines planar and mesa technologies. Experimental transistors have a storage time of approximately 2-30 ns followed by a fall time as fast as 0.5 ns. The storage time can be adjusted by varying the initial base current or the driving pulse. The storage time and fall time are accurately characterized by the charge-control model. A transformer input circuit gives the best switching performance. Control devices of conventional planar structure fail to produce fast switching times. They demonstrate the failure of the charge-control model in describing the fall time of planar transistors in general.     

Profiled current drive for pulsed bipolar transistor switching

Preliminary investigations have been made of the profiling of base current drive to obtain fast turn-on without lifetime pulse stretching and turn-off delays.<>     

Thin-film lateral bipolar transistor in silicon-on-sapphire structure

Heteroepitaxial films of silicon-on-sapphire were used to fabricate lateral bipolar n-p-n transistors. The devices have a common-base direct-current amplification factor of 0.9 and a maximum frequency of oscillation of 2.4 GHz. As a result of the vertical p-n-junction arrangement, small junction areas are possible, e.g. 1×10?6cm2, which yield depletion-layer capacitances of 0.02?0.05 pF.     

A lateral metal—insulator—p-Si tunnel transistor

We report the fabrication of a lateral MIS tunnel transistor whose emitter and collector are Al/SiO2/p-Si tunnel junctions. All processing is carried out at room temperature except for the growth of the passivating field oxide. The small signal common emitter current gain is 20. Two coupled gain mechanisms exist for such a lateral MIS tunnel transistor. The first mechanism relies on a high minority-carrier injection ratio of the emitter junction. Second, the minority carriers injected into the reverse-biased collector junction may produce additional gain through multiplication of majority-carrier current. Lateral MIS tunnel transistors on n-Si make use of the second mechanism. Our device takes advantage of the high minority-carrier injection ratio achievable with Al/SiO2/p-Si tunnel junctions.     

GaAs lateral bipolar transistor with field-separated carriers

A new type of GaAs lateral bipolar transistor has been developed by introducing an n-i-p-i-n structure where the electric field is applied perpendicular to the direction of carrier injection in order for the carriers to be separated. The diffusion length is increased owing to the increase of lifetime due to the spatial separation of injected carriers, resulting in the increase of current gain.     

Automatic switching synchronisation of serial and parallelavalanche transistor connections

150 A/10 ns current pulses across a low ohmic resistive load (1 Ω) were obtained using Marx-type serial connection of the stages with the parallel connection of a few avalanche transistors in each stage. The automatic feedback allows perfect time synchronisation of the switching process in all the transistors