About the origin of low wafer performance and crystal defect generation on seed‐cast growth of industrial mono‐like silicon ingots

The era of the seed‐cast grown monocrystalline‐based silicon ingots is coming. Mono‐like, pseudomono or quasimono wafers are product labels that can be nowadays found in the market, as a critical innovation for the photovoltaic industry. They integrate some of the most favorable features of the conventional silicon substrates for solar cells, so far, such as the high solar cell efficiency offered by the monocrystalline Czochralski‐Si (Cz‐Si) wafers and the lower cost, high productivity and full square‐shape that characterize the well‐known multicrystalline casting growth method. Nevertheless, this innovative crystal growth approach still faces a number of mass scale problems that need to be resolved, in order to gain a deep, 100% reliable and worldwide market: (i) extended defects formation during the growth process; (ii) optimization of the seed recycling; and (iii) parts of the ingots giving low solar cells performance, which directly affect the production costs and yield of this approach. Therefore, this paper presents a series of casting crystal growth experiments and characterization studies from ingots, wafers and cells manufactured in an industrial approach, showing the main sources of crystal defect formation, impurity enrichment and potential consequences at solar cell level. The previously mentioned technological drawbacks are directly addressed, proposing industrial actions to pave the way of this new wafer technology to high efficiency solar cells. Copyright © 2012 John Wiley & Sons, Ltd.     

直接键合四结GaAs太阳电池研究

晶圆直接键合技术由于能将表面洁净的两个晶圆集成到一起,从而可以用来制备晶格失配 III-V族多结太阳电池。为了制备GaInP/GaAs/InGaAsP/InGaAs四结太阳电池,需采用具有低电阻率的GaAs/InP键合界面,从而实现GaInP/GaAs和InGaAsP/InGaA上下两个子电池的电学导通。我们设计并研究了具有不同掺杂元素和掺杂浓度的三种键合界面,并采用IV曲线对其电学性质进行表征。此外,对影响键合界面质量的关键工艺过程进行了研究,主要包括表面清洗技术和键合参数优化,例如键合温度、键合压力和键合时间等。最终制备出的键合四结GaInP/GaAs/InGaAsP/InGaAs太阳电池在AM0条件下效率最高达33.2%。     

清洗工艺对锗外延片表面点状缺陷的影响

锗外延片表面的雾、水印及点状缺陷等会影响太阳电池的性能和成品率,其中点状缺陷出现的比例最高。研究了锗抛光片清洗工艺对外延片表面点状缺陷的影响,获得了无点状缺陷、低粗糙度及高表面质量的锗单晶片。采用厚度为175μm p型<100>锗单面抛光片进行清洗试验,研究了SC-1溶液的不同清洗时间、清洗温度和去离子水冲洗温度对锗抛光片外延后点状缺陷的影响,分析了表面SiO_2残留和锗片表面粗糙度对外延片表面点状缺陷的影响。结果表明点状缺陷主要是由于锗单晶抛光片表面沾污没有彻底清洗干净以及清洗过程中产生新的缺陷造成的。采用氢氟酸溶液浸泡、SC-1溶液低温短时间清洗结合低温去离子水冲洗后的锗抛光片进行外延,用其制备的太阳电池光电转换效率由原来的25%提高到31%。     

Mechanical strength of 300 mm diameter silicon wafers at high temperatures: modeling and simulation

Under gravitational and thermal constraints of IC process technology, 300 mm diameter silicon wafers can partly relax via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the criterion for yielding under a plane stress state. The material attributes, e.g. oxygen and its state of aggregation, are taken into account. While the plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design, the control of plastic deformation due to gravitational forces may be accomplished by equipment design. This system approach allows calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulations for use in ‘what if’ experiments or initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.     

Deformation Anisotropy of <Emphasis Type="Italic">Y</Emphasis> + 128°-Cut Single Crystalline Bidomain Wafers of Lithium Niobate

Bidomain single crystals of lithium niobate (LiNbO₃) and lithium tantalate (LiTaO₃) are promising materials for use as actuators, mechanoelectrical transducers, and sensors capable of working in a wide temperature range. One need to take into account the anisotropy of the properties of the crystalline material when such devices are designed. In this study we investigated deformations of bidomain round shaped Y + 128°-cut wafers of lithium niobate in an external electric field. The dependences of the piezoelectric coefficients on the rotation angles were calculated for lithium niobate and lithium tantalate and plotted for the crystal cuts which are used for the formation of a bidomain ferroelectric structure. In the experiment, we utilized an external heating method and long-time annealing with the lithium out-diffusion method in order to create round bidomain lithium niobate wafers. Optical microscopy was used to obtain the dependences of the bidomain crystals’ movements on the rotation angle with central fastening and the application of an external electric field. We also modelled the shape of the deformed bidomain wafer with the suggestion that the edge movement depends on the radial distance to the fastening point quadratically. In conclusion, we revealed that the bidomain Y + 128°-cut lithium niobate wafer exhibits a saddle-like deformation when a DC electric field is applied.     

Single‐Crystal Germanium Growth on Amorphous Silicon

Growing single‐crystal semiconductors directly on an amorphous substrate without epitaxy or wafer bonding has long been a significant fundamental challenge in materials science. Such technology is especially important for semiconductor devices that require cost‐effective, high‐throughput fabrication, including thin‐film solar cells and transistors on glass substrates as well as large‐scale active photonic circuits on Si using back‐end‐of‐line CMOS technology. This work demonstrates a CMOS‐compatible method of fabricating high‐quality germanium single crystals on amorphous silicon at low temperatures of <450 °C. Grain orientation selection by geometric confinement of polycrystalline germanium films selectively grown on amorphous silicon by chemical vapor deposition is presented, where the confinement selects the fast‐growing grains for extended growth and eventually leads to single crystalline material. Germanium crystals grown using this method exhibit (110) texture and twin‐mediated growth. A model of confined growth is developed to predict the optimal confining channel dimensions for consistent, single‐crystal growth. Germanium films grown from one‐dimensional confinement exhibit a 200% grain size increase at 1 μm film thickness compared to unconfined films, while 2D confinement growth achieved single crystal Ge. The area of single crystalline Ge on amorphous layers is only limited by the growth time. Significant enhancement in room temperature photoluminescence and reduction in residual carrier density have been achieved using confined growth, demonstrating excellent optoelectronic properties. This growth method is readily extensible to any materials system capable of selective non‐epitaxial deposition, thus allowing for the fabrication of devices from high‐quality single crystal material when only an amorphous substrate is available.     

Assessment of ultra-thin Si wafer thickness in 3D wafer stacking

3D integration with multi-stacked wafers is a promising option to enhance device performance and density beyond traditional device scaling limits. However, to bring wafer stacking into reality, there are many technological challenges to be resolved, and one of those is the problem of uniform Si wafer thinning. For multi-stacked devices, Si wafers must be drastically thinned down to less than 50 μm. Problems associated with such ultra-thin Si wafers range from basic wafer handling to difficulty in accurately assessing the thickness of the thinned wafer across the wafer. In this study, bonded wafer pairs have been prepared with different bonding materials, and the stacks were ground down to about 30 μm. The thickness of the ultra-thin wafers was measured by Fourier transform infrared spectrometry (FTIR) technique, and its stability based on bonding status as well as measuring issues will be discussed.     

Room temperature wafer bonding of silicon, oxidized silicon, and crystalline quartz

The use of plasma immersion as preparation for room temperature wafer bonding has been investigated. Silicon wafers have been successfully bonded at room temperature after exposure to oxygen or argon plasma. Oxidized silicon wafers and crystalline quartz have been bonded after exposure to oxygen plasma. The bonded interfaces exhibit very high surface energies, comparable to what can be achieved with annealing steps in the range of 600–800°C using normal wet chemical activation before bonding. The high mechanical stability obtained after bonding at room temperature is explained by an increased dynamic in water removal from the bonded interface allowing covalent bonds to be formed. Electrical measurements were used to investigate the usefulness of plasma bonded interfaces for electronic devices.     

Annealing effects of NTD silicon for semiconductor power devices

The use of neutron transmutation doped (NTD) Si has become very important for processing high-voltage power devices. A simple annealing process is usually required to anneal the lattice defects caused by neutron irradiation. This is usually performed by the silicon supplier by annealing the silicon crystal at a low temperature (approximately 700°C). High-voltage power devices, however, require much higher processing diffusion temperature. In situ annealing of silicon, therefore, can occur during device processing. Furthermore, we demonstrate here that higher yield can be obtained using the in situ annealing. This improvement is due to the effectiveness and uniformity of annealing of thin wafers. The uniformity and blocking voltage distribution of high-voltage rectifiers and thyristors using crystal annealed and in situ wafer annealed NTD silicon are presented.     

纳秒脉冲激光处理后硅电池光电转换效率研究

为了研究纳秒激光于硅晶片改性的可能性,对飞秒及皮秒激光在SF6气体中与硅表面作用形成锥形微观结构及其作用过程进行了分析。通过在SF6气体氛围中采用6ns激光脉冲辐照硅片表面的方法,以获得硅片表面峰状结构,并对此种作用下微观结构形成过程及结果进行了分析。将激光处理后的硅片与未经激光处理的硅片同时放入到硅电池片生产线的适当工序中制成硅电池片,通过对比测试两种硅电池的光电转换效率,从硅表面状况等因素对实验结果进行了初步分析。结果表明,激光处理后的硅片制成硅电池片的光电转换效率与未经激光处理的相比有一定程度的提高,可达15%～25%。     

Optimization of Si NC/P3HT Hybrid Solar Cells

Silicon nanocrystals (Si NCs) are shown to be an electron acceptor in hybrid solar cells combining Si NCs with poly(3‐hexylthiophene) (P3HT). The effects of annealing and different metal electrodes on Si NC/P3HT hybrid solar cells are studied in this paper. After annealing at 150 °C, Si NC/P3HT solar cells exhibit power conversion efficiencies as high as 1.47%. The hole mobility in the P3HT phase extracted from space‐charge‐limited current measurements of hole‐only devices increases from 2.48 × 10^?10 to 1.11 × 10^?9 m² V^?1 s^?1 after annealing, resulting in better transport in the solar cells. A quenching of the open‐circuit voltage and short‐circuit current is observed when high work function metals are deposited as the cathode on Si NC/P3HT hybrid devices.     

The effect of patterns on thermal stress during rapid thermalprocessing of silicon wafers

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform     

Fast Growth of Thin MAPbI3 Crystal Wafers on Aqueous Solution Surface for Efficient Lateral‐Structure Perovskite Solar Cells

Solar‐grade single or multiple crystalline wafers are needed in large quantities in the solar cell industry, and are generally formed by a top‐down process from crystal ingots, which causes a significant waste of materials and energy during slicing, polishing, and other processing. Here, a bottom‐up technique that allows the growth of wafer‐size hybrid perovskite multiple crystals directly from aqueous solution is reported. Single‐crystalline hybrid perovskite wafers with centimeter size are grown at the top surface of a perovskite precursor solution. As well as saving raw materials, this method provides unprecedented advantages such as easily tunable thickness and rapid growth of the crystals. These crystalline wafers show high crystallinity, broader light absorption, and a long carrier recombination lifetime, comparable with those of bulk single crystals. Lateral‐structure perovskite solar cells made of these crystals demonstrate a record power conversion efficiency of 5.9%.     

Modeling emissivity of rough and textured silicon wafers

A method for calculating the emissivity of Si wafers with planar and nonplanar (such as rough or textured) surface morphologies is described. The technique is similar to that used in modeling of light trapping in solar cells and is also applicable to those cases when the wafer may have thin dielectric or metal layers. A software package is developed that uses this method. This package includes an approach for calculating the refractive index and absorption coefficient as a function of wavelength, for various temperatures and dopant concentrations. We present results for a number of cases to demonstrate the applications of this model.     

Mechanical properties of nitrogen-doped CZ silicon crystals

We investigated the effect of the nitrogen doping level on plastic properties of 300 mm silicon material in the temperature range between 650°C and 1000°C. Undoped, low N-doped, and high N-doped materials were examined. The dependence of the upper and lower yield point and the size dependence of indentation related dislocation rosettes on temperature were obtained.An increase in the nitrogen concentration leads to enhanced upper and lower yield points. Possible mechanisms of interaction of dislocations with impurities resulting in hardening of silicon single crystals are discussed. Finite element method (FEM) calculated data of bearing stress observed in 300 mm Si wafers annealed in a vertical furnace are compared with measured upper yield point values. At high nitrogen concentration the tolerable process temperatures, where plastic flow of Si wafers under load can be avoided, are significantly increased.     

Wafer reuse for repeated growth of III–V solar cells

The epitaxial lift‐off (ELO) technique can be used to separate a III–V solar cell structure from its underlying GaAs or Ge substrate. ELO from 4‐inch Ge wafers is shown and 2‐inch GaAs wafer reuse after lift‐off is demonstrated without degradation in performance of the subsequent thin‐film GaAs solar cells that were retrieved from it. Since a basic wet chemical smoothing etch procedure appeared insufficient to remove all the surface contamination, wafer re‐preparation is done by a chemo‐mechanical polishing procedure. Copyright © 2010 John Wiley & Sons, Ltd.     

The one-step vacuum growth of high-quality CuInS2 thin film suitable for photovoltaic applications

Due to its direct energy band gap of 1.53 eV, which is well matched to the solar spectrum, the ternary compound CuInS₂ becomes a promising absorber material for high conversion efficiency solar cells. We report in this paper the preparation and characterization of improved quality CuInS₂ films for use as a high-efficiency solar cell absorber. The films were deposited by RF reactive sputter technique, in which the Cu–In alloy target, H₂S reactant gas, and soda lime glass and Si wafer substrates were used. The as-deposited films were the CuInS₂ chalcopyrite single phase with the preferred orientation of (1 1 2). Void-free films with a grain size of about 400 nm and the constituent ratio [Cu+In]/[S] and [Cu]/[Cu+In] approaching 1 and 0.5, respectively, could be attained by optimizing the process parameters, and films with outstanding electrical characteristics could thus be obtained.     

Application of Two Hopfield Neural Networks for Automatic Four-Element LED Inspection

A system for the automatic inspection of LED wafer defects is proposed to detect defective dies in a four-element (aluminum gallium indium phosphide, AlGaInP) wafer. There are over 80000 dies on an LED wafer. Defective dies are typically visually identified with the aid of a scanning electron microscope. This process involves dozens of operators or engineers visually checking the wafers and hand marking the defective dies. However, wafers may not be fully and thoughtfully checked, and different observers usually find different results. These shortcomings lead to significant labor and production costs. Therefore, a solution that consists of two Hopfield neural networks, of which one is used to identify the LED die regions and the other is used to cluster the die into three groups, is proposed to facilitate the detection of defective dies in wafer images. The experimental results show that the proposed method successfully detects defective dies in a four-element wafer.     

High‐rate deposition of a‐Si:H thin layers for high‐performance silicon heterojunction solar cells

In this paper, we describe a technique for high‐quality interface passivation of n‐type crystalline silicon wafers through the growth of hydrogenated amorphous Si (a‐Si:H) thin layers using conventional plasma‐enhanced chemical vapor deposition. We investigated the onset of crystallization of the a‐Si:H layers at various deposition rates and its effect on the surface passivation properties. Epitaxial growth occurred, even at a low substrate temperature of 90 °C, when the deposition rate was as low as 0·5 Å/s; amorphous growth occurred at temperatures up to 150 °C at a higher deposition rate of 4·2 Å/s. After optimizing the intrinsic a‐Si:H layer deposition conditions and then subjecting the sample to post‐annealing treatment, we achieved a very low surface recombination velocity (7·6 cm/s) for a double‐sided intrinsic a‐Si:H coating on an n‐type crystalline silicon wafer. Under the optimized conditions, we achieved an untextured heterojunction cell efficiency of 16·7%, with a high open‐circuit voltage (694 mV) on an n‐type float‐zone Si substrate. On a textured wafer, the cell efficiency was further enhanced to 19·6%. Copyright © 2011 John Wiley & Sons, Ltd.     

Study of thinned Si wafer warpage in 3D stacked wafers

3D (three-dimensional) wafer stacking technology has been developed extensively recently. One of the many technical challenges in 3D stacked wafers, and one of the most important, is wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within wafer (WIW) uniformity and even electrical failure. In this study, the wafer warpage of thinned Si wafers in stacked wafers has been evaluated. Si wafer or glass was used as a thick substrate, and Cu or polyimide was used as the bonding material. The top Si wafer in the bonded stack was ground down to 20–100 μm, and wafer curvature was measured. Wafer curvature and how it relates to bonding material, substrate material of the stacked layers, and thickness of thinned Si wafer will be discussed.