Modeling and Technique to Improve PSRR and PS-IMD in Analog PWM Class-D Amplifiers

Although power-supply noise, qualified by power- supply rejection ratio (PSRR), has been recognized as a potential drawback of Class-D amplifiers (CDAs) compared to linear amplifiers, the mechanisms of PSRR for CDAs are not well established. It is also not well recognized that the power-supply noise can intermodulate with the input signal, manifesting into power-supply induced intermodulation distortion (PS-IMD), and that the PS-IMD can be significantly larger than the output distortion component at supply noise frequency. Furthermore, techniques to improve PSRR and PS-IMD are largely unreported in literature. In this brief, by means of a linear model, the PSRR and PS-IMD of single-feedback and double-feedback CDAs are analyzed and analytical expressions derived. A simple method is proposed to improve PSRR and PS-IMD with very low hardware overheads, and the improvement is ~ 26 dB. Analytical expressions for PSRR and PS-IMD of the improved design are derived and the pertinent parameters thereof are investigated. The model and analyses provide practical insight to the mechanisms of PSRR and PS-IMD, and how various parameters may be varied to meet a given specification.     

A 2.65 W high-fidelity filterless class D audio amplifier using multiple loop filters

The design of a 2.65 W, high-fidelity, filterless Class D audio amplifier in a standard 0.5 μm CMOS technology is proposed in this paper, where an architecture with multiple loop filters is utilized. This structure attenuates residual clock signals around the loop allowing very low total harmonic distortion (THD) and intermodulation distortion to be achieved in conjunction with high power supply rejection ratio (PSRR). The active area of this circuit is about 1.5 × 1.5 mm². The THD + N is <0.03 % at 1 kHz input frequency and 100 mW output power. The PSRR is ?80 dB at 217 Hz and maximum output power at 10 % THD is 2.658 W. A Figure of merit is defined to estimate the excellent performance which can meet the demands of portable communication devices greatly.     

3-state BTL closed-loop PWM Class D amplifiers

One of the shortcomings of a number of Class D amplifiers (CDAs) designs is their susceptibility to supply noise, quantified by Power Supply Rejection Ratio (PSRR). Reported investigations thereto to-date remain incomplete/over-simplified, particularly the assumption that the AC ground is noise-less and a simplified fully-differential integrator model. In this paper, the effect of supply noise in the AC ground to PSRR is analytically investigated, and the associated analytical expressions derived. Of specific interest, the analysis is applied to the ubiquitous 3-state Bridge-tied-load (BTL) closed-loop PWM CDA, taking into consideration not only the effect of the non-ideal AC ground, but also the effect of the resistor and capacitor mismatch based on a realistic fully-differential integrator model. Further, the PSRR analysis of 3-state BTL closed-loop CDAs has to date been limited to the single-feedback topology and in this paper, extended to the double-feedback topology. These analyses and derived equations herein are useful as they provide valuable insights to CDA designers into the PSRR mechanisms—for example, the counter-intuitive observation that the CDA with 1st-order integrators provides similar or better PSRR than the CDA with 2nd-order integrators if both CDAs are designed to the same carrier attenuation—including the effect of various circuit parameters, and ensuing trade-offs. The derived analytical expressions are verified by means of HSPICE simulations and on the basis of practical measurements on discretely-realized CDAs.     

Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range

Internally compensated CMOS op amps have been widely used in sampled-analog signal processing applications over the past several years. However, the popular two-stage op amp suffers from poor AC power supply rejection to one of the power rails. Two circuits are presented that overcome the power-supply rejection ratio (PSRR) problems of the earlier amplifier: one for virtual ground applications such as switched-capacitor integrators, the other for buffer applications requiring wide common-mode input range. Small signal analysis is developed for the open-loop and PSRR responses of the two amplifiers. In addition, design guidelines are suggested and test results are presented.     

A new PWM controller with one-cycle response

This paper proposes a new nonlinear control technique that has one-cycle response, does not need a resetable integrator in the control path, and has nearly constant switching frequency. It obtains one-cycle response by forcing the error between the switched variable and the control reference to zero each cycle, while the on and off pulses of the controller are adjusted each cycle to ensure near constant switching frequency. The small switching frequency variation due to changes in the reference signal and supply voltage and delays in the circuit are quantified. Using double-edge modulation, the switching frequency variation is further reduced, thus, the associated signal distortion is minimized. An experimental 0-20 kHz bandwidth 95 W RMS power audio amplifier using the control method demonstrates the applicability of this control technique for high-fidelity audio applications. The amplifier has a power supply ripple rejection (PSRR) of 63 dB at 120 Hz. Additionally, the total harmonic distortion plus noise (THD+N) is less than 0.07% measured with a power supply ripple of 15%     

Novel low-voltage folder for analogue-to-digital converter

A novel architecture of low-voltage folder is presented for folding analogue-to-digital (A/D) converter applications. With MOS transistors completely replacing the resistor load used in the conventional folder, this circuit has a good power-supply–rejection-ratio (PSRR) 21.2?dB for the output common voltage and can work well even under a very low power supply 1.0?V. A moderately high gain 14.5?dB and a wide input bandwidth 506?MHz are obtained. The circuit dissipates only 1.2?mW from 1.2?V power supply. The performance is verified by Hspice-Avanti-99.4 simulations on 0.18?µm digital CMOS technology.     

Carrier Distortion in Hysteretic Self-Oscillating Class-D Audio Power Amplifiers: Analysis and Optimization

An important distortion mechanism in hysteretic self-oscillating (SO) class-D (switch mode) power amplifiers-carrier distortion-is analyzed and an optimization method is proposed. This mechanism is an issue in any power amplifier application where a high degree of proportionality between input and output is required, such as in audio power amplifiers or xDSL drivers. From an average-mode point of view, carrier distortion is shown to be caused by nonlinear variation of the hysteretic comparator input average voltage with the output average voltage. This easily causes total harmonic distortion figures in excess of 0.1-0.2%, inadequate for high-quality audio applications. Carrier distortion is shown to be minimized when the feedback system is designed to provide a triangular carrier (sliding) signal at the input of a hysteretic comparator. The proposed optimization method is experimentally proven in an audio power amplifier leading to THD figures that are comparable to the state of the art. Experimental hardware is a hysteretic SO bandpass current-mode-controlled single-ended audio power amplifier capable of 45 W into 8 Omega or 80 W into 4Omega from a plusmn34 V supply with less than 0.03% THD from 100 Hz to 6.7 kHz. Carrier distortion is shown to account for this limitation in THD performance.     

Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters

This paper discusses the design, analysis and performance of a low-voltage, highly linear switched-R-MOSFET-C filter. High linearity, even at a low supply voltage, is achieved through the use of duty-cycle-controlled tuning. Tuning MOSFETs are switched completely on while conducting, such that their nonlinear resistance is much smaller than the linear filter resistors, resulting in low distortion. The MOSFETs are also placed inside the filter feedback loop which further reduces distortion. Because tuning is done in the time domain, rather than in the voltage domain, the tuning range is independent of the supply voltage. The filter achieves -77 dB total harmonic distortion (THD) using a 0.6-V supply, and -90 dB THD using a 0.8-V supply, with a 0.6-Vpp differential 2 kHz sine input. The prototype IC, implemented in a 0.18-mum CMOS process, occupies an area of 0.7 mm² and consumes 1 mW of power from a 0.6-V supply.     

A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator

A digital Class-D amplifier comprises a pulsewidth modulator (PWM) and an output stage. In this paper, we simplify the time-domain expression for the algorithmic PWM linear interpolation (LI) sampling process and analytically derive its double Fourier series expression. By means of our derivation, we show that the nonlinearities of the LI process are very low, especially given its modest computation complexity and low sampling frequency. In particular, the total-harmonic distortion (THD) /spl ap/0.02% and foldback distortion is -98.4 dB (averaged from modulation indexes M=0.1 to 0.9) for the 4-kHz voiceband bandwidth @1-kHz input, 48-kHz sampling. We also describe a simple hardware for realizing the LI process. We propose a frequency doubler (with small overheads) for the pulse generator for the PWM, thereby reducing the counter clock rate by 2, leading to a substantial /spl sim/47% power dissipation reduction for the Class-D amplifier. By means of computer simulations and on the basis of experimental measurements, we verify our double Fourier series derivation and show the attractive attributes of a Class-D amplifier embodying our simplified LI sampling expression and reduced clock rate pulse generator. We show that our Class-D amplifier design is micropower (/spl sim/60 /spl mu/W @1.1 V and 48-kHz sampling rate, and THD /spl ap/0.03%) and is suitable for practical power-critical portable audio devices, including digital hearing aids.     

2.5W低噪声CMOSD类音频功放设计

提出了一种基于0.5μm5VCMOS工艺的低噪声PWM调制D类音频功率放大器。该放大器在5V电源电压下以全桥方式可以驱动4Ω负载输出2.5W功率;转换效率等于87%,信噪比达94dB(负载8Ω,输出功率1W);THD+N仅0.05%(负载4Ω,输出功率1W);PSRR为68dB(频率1kHz)。分析了整体电路结构及其线性化模型,并着重介绍了高性能前置斩波稳定运算放大器(开环增益117dB,等效输入噪声16μV.Hz-1/2),线性三角波振荡电路(斜率偏差仅±0.2%)和功率器件、驱动电路的设计。最后给出了D类放大器的测试结果。     

THD改善的D类音频功放

提出了一种双环反馈拓扑结构的D类音频功放.通过对基于脉冲宽度调制的D类功放反馈系统的分析,指出环路参数对总谐波失真THD和电源抑制比PSRR等性能有着重要的影响,讨论了如何通过参数优化来改善一阶单环反馈D类功放的THD指标.在此基础上提出了一种双环反馈拓扑结构,通过数学分析显示该二阶闭环系统的THD指标能得到更进一步地改善.测试结果显示,双环结构D类功放的THD较单环得到了7倍的改善.     

High-efficiency dynamic supply CMOS audio power amplifier for low-power applications

This paper describes the analysis and design of a dynamic supply CMOS audio power amplifier for low-power applications. The dynamic supply technique is used to increase the efficiency of a class AB power amplifier. The polarization of its output stage is adaptive so that the maximum efficiency enhancement can be achieved without jeopardizing the linearity of the system. Two types of adaptive polarization are proposed and compared. A concept of power supplies switching is also proposed. Simulation results are presented showing that an efficiency of 53.6% at a total harmonic distortion (THD) of less than 0.1% can be achieved, whereas the maximal theoretical value for a class AB amplifier is approximately 33.3%.     

一种高线性Gm-C复数滤波器的设计

针对低电源电压Gm-C复数滤波器线性度不足的问题,提出了一种使用大信号线性化技术的一阶复数带通滤波器。所提出的复数滤波器使用了不平衡差分对和自适应偏置电路两种线性化技术,通过扩展跨导相对恒定的输入电压范围提高滤波器的线性度。滤波器采用UMC 110 nm CMOS工艺设计,中心频率和带宽分别为2 MHz和1 MHz。Cadence仿真结果显示,在1.2 V电源电压下,滤波器功耗为229μW,镜像抑制比(IIR)为18 dB,线性度(输入三阶交调点IIP3)为9.53 dBm,总谐波失真(THD)为-55.7 dB。该复数滤波器电路结构简单、功耗较低,以期能广泛应用于低电源电压的接收机设计。     

Low-power CMOS continuous-time filters

A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance. Integrator excess phase shift is reduced using balanced signal paths, and open-loop gain is increased using low-voltage cascode amplifiers. Two-pole bandpass and five-pole lowpass ladder filters have been implemented in a 1.2 μm n-well CMOS process. The lowpass prototypes provided 300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB dynamic range with 1% total harmonic distortion (THD), and 30 μW/pole (300 kHz bandwidth) power dissipation with a 1.5 V supply; the bandpass prototypes had a tunable center frequency of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75 μW/pole (525 kHz center frequency) from a 1.5 V supply. The active filter area was 0.1 mm²/pole for both designs     

一种10-ppm/~oC低压CMOS带隙电压基准源设计

在对传统CMOS带隙电压基准源电路分析和总结的基础上,综合一级温度补偿、电流反馈和电阻二次分压技术,提出了一种10-ppm/oC低压CMOS带隙电压基准源。采用差分放大器作为基准源的负反馈运放,简化了电路的设计,放大器的输出用于产生自身的电流源偏置,提高了电源抑制比(PSRR)。整个电路采用TSMC 0.35mm CMOS工艺实现,采用Hspice进行仿真,仿真结果证明了基准源具有低温度系数和高电源抑制比。     

Low-distortion switched-capacitor filter design techniques

The distortion mechanism in switched-capacitor (SC) filters are considered, and closed-form expression relating switched-capacitors filter distortion to circuit parameters are derived. Design techniques for low-distortion applications are discussed and are applied to a sixth-order experimental filter. The filter design uses a fully differential class A/B op amp with a continuous-time common-mode feedback circuit. Distortion measurements show that for 82-dB dynamic range (relative to noise floor) the total harmonic distortion of 0.02% within the whole 4-kHz bandwidth and 0.07% within 20-kHz bandwidth.     

低压CMOS带隙电压基准源设计

在对传统典型CMOS带隙电压基准源电路分析和总结的基础上,综合一级温度补偿、电流反馈技术,提出了一种1-ppm/°C低压CMOS带隙电压基准源。采用差分放大器作为基准源的负反馈运放,简化了电路设计。放大器输出用作电路中PMOS电流源偏置,提高了电源抑制比(PSRR)。整个电路采用TSMC0.35μmCMOS工艺实现,采用HSPICE进行仿真,仿真结果证明了基准源具有低温度系数和高电源抑制比。     

A 0.02% THD and 80 dB PSRR filterless class D amplifier with direct lithium battery hookup in mobile application

This paper presents a fully integrated CMOS filterless class D amplifier that can directly hook up lithium battery in mobile application The proposed amplifier embodies a 2-order feedback path architecture instead of direct feedback of output to input of the integrator to decrease the high frequency intermodulation distortion associated with direct feedback and eliminate the integrator input common mode disturbance from the output in ternary modulation. The prototype class D amplifier realized in 0.35μm digital technology achieves a THD+N of 0.02% when delivering 400 mW to an 8Ω load from V_DD=3.6 V. The PSRR of the prototype class D amplifier is 80 dB at 217 Hz. Furthermore a filterless method that can eliminate the external LC filter is employed which offers great advantages of saving PCB space and lowering system cost. In addition the prototype class D amplifier can operate in large voltage range with V_DD range from 2.5 to 4.2 V in mobile application. The total area of the amplifier is 1.7 mm².     

一种具有高电源抑制比的低功耗CMOS带隙基准电压源

文章设计了一种适用于CMOS工艺的带隙基准电压源电路，该电路采用工作在亚阈值区的电路结构，并采用高增益反馈回路，使其具有低功耗、低电压、高电源电压抑制比和较低温度系数等特点。     

A 900-mV low-power ΔΣ A/D converter with 77-dB dynamicrange

The design of a low-voltage and low-power ΔΣ analog-to-digital (A/D) converter is presented. A third-order single-loop ΔΣ modulator topology is implemented with the differential modified switched op-amp technique. The modulator topology has been transformed as to accommodate half-delay integrators. Dedicated low-voltage circuit building blocks, such as a class AB operational transconductance amplifier, a common-mode feedback amplifier, and a comparator are treated, as well as low-voltage design techniques. The influence of very low supply voltage on power consumption is discussed. Measurement results of the 900-mV ΔΣ A/D converter show a 77-dB dynamic range in a 16-kHz bandwidth and a 62-dB peak signal-to-noise ratio for a 40-μW power consumption