A novel high-/spl kappa/ SONOS memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si structure for fast speed and long retention operation

A novel high-/spl kappa/ silicon-oxide-nitride-oxide-silicon (SONOS)-type memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si (MATHS) structure is reported for the first time. Such MATHS devices can keep the advantages of our previously reported TaN/HfO/sub 2//Ta/sub 2/O/sub 5//HfO/sub 2//Si device structure to obtain a better tradeoff between long retention and fast programming as compared to traditional SONOS devices. While at the same time by replacing hafnium oxide (HfO/sub 2/) with aluminum oxide (Al/sub 2/O/sub 3/) for the top blocking layer, better blocking efficiency can be achieved due to Al/sub 2/O/sub 3/'s much larger barrier height, resulting in greatly improved memory window and faster programming. The fabricated devices exhibit a fast program and erase speed, excellent ten-year retention and superior endurance up to 10/sup 5/ stress cycles at a tunnel oxide of only 9.5 /spl Aring/ equivalent oxide thickness.     

A new metal-ferroelectric (PbZr/sub 0.53/Ti/sub 0.47/O/sub 3/)-insulator (Dy/sub 2/O/sub 3/)-semiconductor (MFIS) FET for nonvolatile memory applications

Metal-ferroelectric-insulator-semiconductor (MFIS) field-effect transistors with Pb(Zr/sub 0.53/,Ti/sub 0.47/)O/sub 3/ ferroelectric layer and dysprosium oxide Dy/sub 2/O/sub 3/ insulator layer were fabricated. The out-diffusion of atoms between Dy/sub 2/O/sub 3/ and silicon was examined by secondary ion mass spectrometry profiles. The size of the memory windows was investigated. The memory windows measured from capacitance-voltage curves of MFIS capacitors and I/sub DS/-V/sub GS/ curves of MFIS transistors are consistent. The nonvolatile operation of MFIS transistors was demonstrated by applying positive/negative writing pulses. A high driving current of 9 /spl mu/A//spl mu/m was obtained even for long-channel devices with a channel length of 20 /spl mu/m. The electron mobility is 181 cm/sup 2//V/spl middot/s. The retention properties of MFIS transistors were also measured.     

Fabrication and Properties of $hbox{Pt}/hbox{Bi}_{3.15}hbox{Nd}_{0.85} hbox{Ti}_{3}hbox{O}_{12}/breakhbox{HfO}_{2}/hbox{Si}$ Structure for Ferroelectric DRAM (FEDRAM) FET

Metal–ferroelectric–insulator–semiconductor (MFIS) capacitors with 400-nm-thick $hbox{Bi}_{3.15}hbox{Nd}_{0.85}hbox{Ti}_{3}hbox{O}_{12}$ (BNdT) ferroelectric film and 4-nm-thick hafnium oxide $(hbox{HfO}_{2})$ layer on silicon substrate have been fabricated and characterized. It is demonstrated that the $hbox{Pt}/hbox{Bi}_{3.15}hbox{Nd}_{0.85}hbox{Ti}_{3}hbox{O}_{12}/ hbox{HfO}_{2}/hbox{Si}$ structure exhibits a large memory window of around 1.12 V at an operation voltage of 3.5 V. Moreover, the MFIS memory structure suffers only 10% degradation in the memory window after $hbox{10}^{10}$ switching cycles. The retention time is 100 s, which is enough for ferroelectric DRAM field-effect-transistor application. The excellent performance is attributed to the formation of well-crystallized BNdT perovskite thin film on top of the $ hbox{HfO}_{2}$ buffer layer, which serves as a good seed layer for BNdT crystallization, making the proposed $hbox{Pt}/hbox{Bi}_{3.15}hbox{Nd}_{0.85}hbox{Ti}_{3}hbox{O}_{12}/ hbox{HfO}_{2}/hbox{Si}$ suitable for high-performance ferroelectric memories.      

Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.     

Structural advantage for the EOT scaling and improved electron channel mobility by incorporating dysprosium oxide (Dy/sub 2/O/sub 3/) into HfO/sub 2/ n-MOSFETs

A structural approach of fabricating laminated Dy/sub 2/O/sub 3/-incorporated HfO/sub 2/ multimetal oxide dielectric has been developed for high-performance CMOS applications. Top Dy/sub 2/O/sub 3/ laminated HfO/sub 2/ bilayer structure shows the thinnest equivalent oxide thickness (EOT) with a reduced leakage current compared to HfO/sub 2/. This structure shows a great advantage for the EOT scaling CMOS technology. Excellent electrical performances of the Dy/sub 2/O/sub 3//HfO/sub 2/ multimetal stack oxide n-MOSFET such as lower V/sub T/, higher drive current, and an improved channel electron mobility are reported. Dy/sub 2/O/sub 3//HfO/sub 2/ sample also shows a better immunity for V/sub t/ instability and less severe charge trapping characteristics. Two different rationed Dy/sub 2/O/sub 3//HfO/sub 2/ and HfO/sub 2/ n-MOSFET were measured by charge-pumping technique to obtain the interface state density (D/sub it/), which indicates a reasonable and similar interface quality. Electron channel mobility is analyzed by decomposing into three regimes according to the effective field. Reduced phonon scattering is found to be the plausible mechanism for higher channel mobility.     

SBT铁电薄膜及其脉冲准分子激光制备

采用脉冲准分子激光沉积法在Ｐｔ／Ｔｉ／ＳｉＯ２／Ｓｉ衬底上成功地制备了ＳＢＴ铁电薄膜，发现存在一个最佳沉积衬底温度约为４５０℃。在该温度下沉积的ＳＢＴ薄膜具有较饱和的方形电滞回线，其剩余极化Ｐｒ和矫顽电场Ｅｃ分别为８．４μＣ／ｃｍ２和５７ｋＶ／ｃｍ。     

层状钙钛矿铁电薄膜中铁电极化子研究

用PLD方法在铂金硅衬底制作了高质量的SrBi2Ta2O9(SBT)铁电薄膜样品．在10到300K的低温范围，研究了SBT薄膜的电子输运特性，分析了其传导机制．结果显示在SBT铁电薄膜中存在两种导电机制．根据SBT层状结构，两种导电机制分为：被限制在Bi—O层内的内输运，和能够穿过Bi—O层的外输运．首次观察到作为内传导载流子的铁电极化子的电输运行为．在SBT薄膜中铁电极化子的热激活能Eα～0．0556eV．研究结果为SBT薄膜具有极低漏电流提供了一种解释．     

Mobility enhancement in TaN metal-gate MOSFETs using tantalum incorporated HfO/sub 2/ gate dielectric

TaN metal-gate nMOSFETs using HfTaO gate dielectrics have been investigated for the first time. Compared to pure HfO/sub 2/, a reduction of one order of magnitude in interface state density (D/sub it/) was observed in HfTaO film. This may be attributed to a high atomic percentage of Si-O bonds in the interfacial layer between HfTaO and Si. It also suggests a chemical similarity of the HfTaO-Si interface to the high-quality SiO/sub 2/-Si interface. In addition, a charge trapping-induced threshold voltage (V/sub th/) shift in HfTaO film with constant voltage stress was 20 times lower than that of HfO/sub 2/. This indicates that the HfTaO film has fewer charged traps compared to HfO/sub 2/ film. The electron mobility in nMOSFETs with HfO/sub 2/ gate dielectric was significantly enhanced by incorporating Ta.     

Characteristics of metal-ferroelectric-insulator-semiconductor structure using Sr0.8Bi2.2Ta2O9 and Sr0.8Bi2.2Ta2O9-BaZrO3 for ferroelectric gates

Characteristics of BaZrO₃ (BZO) modified Sr_0.8Bi_2.2Ta₂O₉ (SBT) thin films fabricated by sol-gel method on HfO₂ coated Si substrates have been investigated in a metal-ferroelectric-insulator-semiconductor (MFIS) structure for potential use in a ferroelectric field effect transistor (FeFET) type memory. MFIS structures consisting of pure SBT and doped with 5 and 7 mol% BZO exhibited memory windows of 0.81, 0.82 and 0.95 V with gate voltage sweeps between −5 and +5 V, respectively. Leakage current density levels of 10⁻⁸ A/cm² for BZO doped SBT gate materials were observed and attributed to the metallic Bi on the surface as well as intrinsic defects and a porous film microstructure. The higher than expected leakage current is attributed to electron trapping/de-trapping, which reduces the data retention time and memory window. Further process improvements are expected to enhance the electronic properties of doped SBT for FeFET.     

Evidence and understanding of ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors outperforming sandwich counterparts

Metal-insulator-metal capacitors with atomic-layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminated and sandwiched dielectrics have been compared, for the first time, for analog circuit applications. The experimental results indicate that significant improvements can be obtained using the laminated dielectrics, including an extremely low leakage current of 1/spl times/10/sup -9/ A/cm/sup 2/ at 3.3V and 125/spl deg/C, a high breakdown electric field of /spl sim/3.3MV/cm at 125/spl deg/C, good polarity-independent electrical characteristics, while retaining relatively high capacitance density of 3.13 fF//spl mu/m/sup 2/ as well as voltage coefficients of capacitance as low as -80 ppm/V and 100 ppm/V/sup 2/ at 100 kHz. The underlying mechanism is likely due to alternate insertions of Al/sub 2/O/sub 3/ layers that reduce the thickness of each HfO/sub 2/ layer, hereby efficiently inhibiting HfO/sub 2/ crystallization, and blocking extensions of grain boundary channels from top to bottom as well as to achieve good interfacial quality.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

Improving channel carrier mobility and immunity to charge trapping of high-K NMOSFET by using stacked Y/sub 2/O/sub 3//HfO/sub 2/ gate dielectric

A stacked Y/sub 2/O/sub 3//HfO/sub 2/ multimetal gate dielectric with improved electron mobility and charge trapping characteristics is reported. Laminated hafnium and yttrium were sputtered on silicon followed by post-deposition anneal (PDA) in N/sub 2/ ambient. The new dielectric shows a similar scalability to HfO/sub 2/ reference. Analysis on flatband voltage shift indicates positive fixed charge induced by Y/sub 2/O/sub 3/. Excellent transistor characteristics have been demonstrated. Stacked Y/sub 2/O/sub 3//HfO/sub 2/, compared to HfO/sub 2/ reference with similar equivalent oxide thickness (EOT), shows 49% enhancement in transconductance and 65% increase in the peak electron mobility. These improvements may be attributed to better charge trapping characteristics of the multimetal dielectric.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

SONOS-type flash memory using an HfO/sub 2/ as a charge trapping layer deposited by the sol-gel spin-coating method

In this letter, the authors fabricate the silicon-oxide-nitride-oxide-silicon (SONOS)-like memory using an HfO/sub 2/ as charge trapping layer deposited by a very simple sol-gel spin-coating method and 900 /spl deg/C 1-min rapid thermal annealing. They examine the quality of sol-gel HfO/sub 2/ charge trapping layer by X-ray photoemission spectroscopy, Id-Vg, charge retention, and endurance. The threshold voltage shift is 1.2 V for the sol-gel HfO/sub 2/ trapping layer. The sol-gel HfO/sub 2/ film can form a deep trap layer to trap electrons for the SONOS-like memory. Therefore, the sol-gel device exhibits the long charge retention time and good endurance performance. The charge retention time is 10/sup 4/ s with only 6% charge loss and long endurance program/erase cycles up to 10/sup 5/.     

MIM capacitors using atomic-layer-deposited high-/spl kappa/ (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ dielectrics

Metal-insulator-metal (MIM) capacitors with (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ high-/spl kappa/ dielectric films were investigated for the first time. The results show that both the capacitance density and voltage/temperature coefficients of capacitance (VCC/TCC) values decrease with increasing Al/sub 2/O/sub 3/ mole fraction. It was demonstrated that the (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitor with an Al/sub 2/O/sub 3/ mole fraction of 0.14 is optimized. It provides a high capacitance density (3.5 fF//spl mu/m/sup 2/) and low VCC values (/spl sim/140 ppm/V/sup 2/) at the same time. In addition, small frequency dependence, low loss tangent, and low leakage current are obtained. Also, no electrical degradation was observed for (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitors after N/sub 2/ annealing at 400/spl deg/C. These results show that the (HfO/sub 2/)/sub 0.86/(Al/sub 2/O/sub 3/)/sub 0.14/ MIM capacitor is very suitable for capacitor applications within the thermal budget of the back end of line process.     

Fabrication and characterization of M-I-FIS ferroelectric-gate structures using HfAlOx buffer layer

Metal-insulator-ferroelectric-insulator-semiconductor (M-I-FIS) ferroelectric-gate structures have been fabricated and characterized using HfAlO_x as an upper insulating layer and SrBi₂Ta₂O₉ (SBT) as a ferroelectric layer. Clear hysteresis loop due to the ferroelectric SBT is obtained in the capacitance-voltage characteristics with a memory window of more than 1 V. It is demonstrated that the leakage current density is significantly reduced by inserting the HfAlO_x buffer layer and that the data retention time for the M-I-FIS structure is longer than the MFIS structure without HfAlO_x buffer layer.     

Metal-insulator-metal RF bypass capacitor using niobium oxide (Nb/sub 2/O/sub 5/) with HfO/sub 2//Al/sub 2/O/sub 3/ barriers

A high capacitance density (C/sub density/) metal-insulator-metal (MIM) capacitor with niobium pentoxide (Nb/sub 2/O/sub 5/) whose k value is higher than 40, is developed for integrated RF bypass or decoupling capacitor application. Nb/sub 2/O/sub 5/ MIM with HfO/sub 2//Al/sub 2/O/sub 3/ barriers delivers a high C/sub density/ of >17 fF//spl mu/m/sup 2/ with excellent RF properties, while maintaining comparable leakage current and reliability properties with other high-k dielectrics. The capacitance from the dielectric is shown to be stable up to 20 GHz, and resonant frequency of 4.2 GHz and Q of 50 (at 1 GHz) is demonstrated when the capacitor is integrated using Cu-BEOL process.     

La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs with high hole mobility and good device characteristics

We have studied high-k La/sub 2/O/sub 3/ p-MOSFETs on Si/sub 0.3/Ge/sub 0.7/ substrate. Nearly identical gate oxide current, capacitance density, and time-dependent dielectric breakdown (TDDB) are obtained for La/sub 2/O/sub 3//Si and La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ devices, indicating excellent Si/sub 0.3/Ge/sub 0.7/ quality without any side effects. The measured hole mobility in nitrided La/sub 2/O/sub 3//Si p-MOSFETs is 31 cm/sup 2//V-s and comparable with published data in nitrided HfO/sub 2//Si p-MOSFETs. In sharp contrast, a higher mobility of 55 cm/sup 2//V-s is measured in La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFET, an improvement by 1.8 times compared with La/sub 2/O/sub 3//Si control devices. The high mobility in Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs gives another step for integrating high-k gate dielectrics into the VLSI process.     

Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO/sub 2//metal stacks

The performance of aggressively scaled (1.4nm相似文献