Use of self‐erase discharges for high‐speed and low‐voltage addressing of PDPs

Abstract— A technique called “self‐erase‐discharge addressing” has been incorporated with a address‐while‐display driving scheme, contiguous subfield, and erase addressing to obtain high‐speed and low‐voltage addressing of PDPs. The technique uses a relatively high X‐sustain pulse voltage VXsus, which produces a weak self‐erase discharge at its trailing edge. An application of a data pulse Vdata synchronous to a weak self‐erase discharge results in full erase discharge and eliminates all the wall charges. The technique assures a wider operating‐voltage margin since it provides identical amounts of priming charges as well as wall charges to all the horizontal scan lines just prior to addressing. The priming charges are generated by the weak self‐erase discharges, resulting in low Vdata of 30 V and a high addressing speed of 0.66 μsec for a Ne + 10% Xe PDP. V_Xsus = 245 V, and the voltage margins of Vdata and VXsus were 35 and 16 V, respectively. For a 30% Xe PDP, Vdata and VXsus were 30 and 335 V, respectively, with an addressing speed of 1.0 μsec. In order to obtain high dark‐room contrast, it is essential to use ramp reset pulses, with which erase addressing cannot be achieved. By adopting the write addressing only to the first subfield and the self‐erase‐discharge addressing to the subsequent subfields, a peak and background luminance in green of 3100 and 0.22 cd/m², respectively, were obtained with a dark‐room contrast of 14,000:1. The number of subfields was 28, and the light emission duty was 83%. The number of ramp reset pulse drivers could be reduced to 12 by adopting the common reset pulse technique.     

Investigation of the firing voltage in a shadow‐mask PDP

Abstract— A numerical method was used to investigate the firing characteristics of the discharge cell in an AC shadow‐mask PDP (SM‐PDP). The firing voltages for the various discharge paths in the addressing and sustaining periods were calculated, and the effects of the metal barrier rib and the dielectric layer in the discharge cell on the firing characteristics were studied. Furthermore, the advantages of the SM‐PDP in terms of the firing characteristics will be discussed.     

Feasibility of driving PDPs with 1‐V data and 30‐V scan pulses by controlling the self‐erase‐discharge threshold

Abstract— In order to realize low‐voltage addressing of PDPs, an erase‐addressing scheme was adopted together with an accumulation of an appropriate amount of wall charge by using priming and bias pulses prior to addressing. The switching operation is performed by using sharp threshold characteristics of the self‐erase discharge. Cessation of the scan pulse ignites a weak self‐erase discharge, which, together with the data pulse, triggers an intense self‐erase discharge. By using the drive scheme, the data‐ and scan‐pulse voltages can be reduced to 1.1 and 29.6 V, respectively, provided that the panel has perfectly uniform voltage characteristics.     

High‐speed low‐voltage driving of high‐Xe‐content PDPs with priming particles

Abstract— Power savings, image‐quality improvement, and cost reduction are the major issues facing PDP development. High‐Xe‐content PDPs have attained improved luminous efficiency, but with sacrifices in higher switching and sustain voltages and slower discharge build‐up. By examining PDPs having 3.5%–30% Xe content, it was found that utilization of the space‐charge priming effect as well as wall‐charge accumulation are effective in obtaining a low operating voltage and a high switching speed. The improvements are enhanced for higher Xe pressures. By using space‐charge priming, the statistical time lag of the discharge triggering for the 30% Xe content is reduced significantly and becomes approximately equal to that of 3.5% Xe content. Once triggered, the formative time lag of the discharge becomes shorter and the space charge experiences diffusion/drift; hence, accumulation of the wall charge is faster for discharges with higher Xe contents. These indicate that the use of an erase addressing scheme, rather than a write addressing scheme, is preferable when driving high Xe‐content PDPs, because the erase addressing scheme provides the addressing operation with an abundant amount of priming particles. Also, the drive voltages are lower for the erase addressing scheme. In order to reduce the address voltage, it is effective to accumulate wall charges prior to addressing. It was found that there are limiting values for the charge accumulation, above which self‐erase discharges ignite and the wall charge is dissipated. The self‐erase discharge occurs at relatively low wall voltages when the Xe percentages becomes higher. The sustain pulse voltage can be reduced while keeping the luminous efficiency high by increasing the sustain pulse frequency. As the frequency is increased, a residual amount of space charge created by the preceding sustain pulse increases. Due to the priming effect of these space charge, the build‐up of the discharge current becomes faster, resulting in a lower voltage.     

Investigation of the discharge process in a shadow‐mask PDP cell using fluid models

Abstract— Two fluid models, LFA (local field approximation) and EME (electron mean energy), were applied to simulate the discharge process of a novel PDP with a shadow mask. In order to consider the variation of the secondary electron emission coefficient under different electric‐field and gas content, the secondary electron emission coefficient was calculated as a function of the energy of incident ions. The variation of the mean density of different particles as a function of time, electron temperature, and their space distributions in the discharge cell will be presented. And the simulation results of these two models are also compared in this paper. Then the EME model was used to investigate the relation between the discharge efficiency and the structure of the shadow mask, the xenon concentration, and the pressure.     

High‐speed and low‐voltage write addressing of plasma display panels by use of extremely weak discharge

Although the priming effect shortens address period and reduces address voltage, it is difficult to use the priming effect for the conventional write addressing method because the ramp reset pulses provide little priming effect. An extremely weak discharge for priming has been incorporated with write addressing method. The extremely weak discharge is generated by priming pulse applied just prior to the scan pulse. In the 4‐in‐diagonal test panel containing Ne + 10%Xe mixture gas, infrared emission intensity of the discharge is 900 times smaller than that of sustain discharge. Therefore, there is no degradation of dark room contrast ratio. Because the priming discharge generates a very small amount of charges, there is little reduction in the amount of wall charge accumulated during reset period. Namely, increase in address voltage can be avoided. Although the discharge intensity is extremely low, it provides sufficient priming particles for high‐speed and low‐voltage addressing. When priming pulse voltage is 70 V and width is 10 µs, the address discharge delay is reduced to less than half. When the scan voltage margin is 10 V, the data voltage is reduced to 17 V, which is 20 V lower than that of conventional method.     

The 121‐contiguous‐subfield addressing of high Xe‐content PDPs

Abstract— As the Xe content of PDPs is increased, the space‐charge priming becomes more effective. Also, the diffusion/drift of the space charges and accumulation of the wall charges becomes faster. These facts indicate that the use of an erase addressing is preferable for high‐Xe‐content PDPs. A 30%‐Xe green test panel was driven with contiguous subfields using erase addressing and a grouped Address‐While‐Display scheme. Crosstalk was suppressed by driving the odd and even sustain electrodes separately. The fast addressing speed of 0.283 μsec allowed for 121 subfields and 122 gray levels, with a resultant luminance of 4200 cd/m² and a dark‐room contrast of 310:1. The scan and data pulse voltages were as low as 90 and 75 V, respectively. All the subfields had an identical length of 136 μsec, but the number of sustain pulses in these subfields could be varied between 2 and 20. By selecting an adequate number of sustain pulses in the subfields, arbitrary gamma characteristics could be realized. A gray‐scale expression having a constant difference between the consecutive “perceived” luminance levels was verified throughout all the luminance levels.     

Driving passive‐matrix LCDs with low hardware complexity and reduced supply voltage

In passive‐matrix liquid‐crystal displays (LCDs), multiplexing is achieved by using the intrinsic non‐linear characteristics of the liquid‐crystal material. If the electro‐optic characteristic is steeper than necessary for the matrix display, the selection ratio need not be maximized. Instead, the selection ratio can be reduced to match the electro‐optic characteristics of the display. This leads to a reduction in the supply voltage of the drive electronics. We have considered the possibility of using addressing techniques with low hardware complexity along with displays having steep electro‐optic characteristics. Supply voltages for these techniques are compared with that of multi‐line addressing (MLA). The supply voltages of the Hybrid Addressing Technique (HAT), Improved Hybrid Addressing Technique‐S3 (IHAT‐S3), and Improved Hybrid Addressing Technique‐S4 (IHAT‐S4) are lower than that of MLA for the lower range of N. These hybrid addressing techniques with lower hardware complexity are a better choice for driving passive‐matrix LCDs, especially in portable equipment.     

Data‐pulse‐voltage reduction of AC‐PDPs by using metastable‐particle priming

Abstract— It is shown that space charges dominate the build‐up of an address discharge when it is preceded by a priming discharge in less than 32 μsec. When the separation of these discharges (cease period) exceeds 32 μsec, the space charges diffuse away and the metastable particles start playing the role of priming. The priming effect of the metastable particles is not too strong, which is desirable for adopting a data‐pulse‐voltage reduction technique for PDPs. By choosing the length of the cease period to be between 32 and 80 μsec in the Address‐While‐Display drive scheme, the data pulse voltage was reduced to 20 V. This leads to a considerable cost reduction of data driver ICs.     

Characterization of micro‐cell discharge in AC‐PDPs by spatio‐temporal optical emission spectroscopy

Abstract— We have developed highly resolved spatio‐temporal optical emission spectroscopy to investigate the discharge characteristics of coplanar type ac plasma‐display panels (AC‐PDPs). Spatio‐temporal emission profiles were measured for relevant lines of atomic He, Ne, Xe, and ionic Xe in He‐Xe and Ne‐Xe systems with various Xe concentrations and total gas pressures. The surface‐discharge behavior in coplanar PDPs has been clarified.     

Discharge characteristics and low‐voltage driving of high‐Xe‐content PDPs

Abstract— High‐Xe‐content PDPs attain improved luminous efficiency, but with sacrifices of higher sustain and address voltages and slower discharge build‐up. By examining PDPs with 3.5–100% Xe contents, it was revealed that space‐charge priming as well as wall‐charge accumulation are effective in obtaining low‐voltage and high‐speed operation. In addition, it was found that the effectiveness is emphasized for higher‐Xe‐pressure PDPs. In this respect, erase addressing is more favorable than write addressing, especially for high‐Xe‐pressure PDPs. The formative time lag of the discharge and diffusion/drift of the space charges are shorter for high Xe contents. In this respect, high‐Xe‐content PDPs have a potential for high‐speed addressing, if driven adequately. The use of space‐charge priming, however, is limited by the duration between the priming and scan pulses. Accumulation of wall charges is limited by ignition of a self‐erase discharge with which all the wall charges are dissipated. Although the highest efficiency and luminance are attained with a 100%‐Xe panel, the optimum Xe gas content, considering the sustain pulse voltage and drive voltage margin, would be 70% Xe + Ne.     

Minimum‐voltage driving of small STN‐LCDs by optimized multiple‐row addressing

Abstract— In small STN‐LCDs for portable applications, rows and columns are driven by one IC. The LC supply voltages are generated on‐chip from the battery voltage by voltage multiplying. The total LC supply voltage should be as low as possible to minimize the accompanied power losses. By using multiple‐row addressing, the row and maximum column voltages can be made equal, leading to a minimum LC supply voltage. This occurs when the number of simultaneously addressed rows is equal to the square root of the number of rows in the panel. The LC supply voltage may be minimized further by using a liquid crystal which allows multiplexing of more rows than are actually present in the display panel, while at the same time fewer simultaneously addressed rows are required.     

Novel pixel design for high‐resolution AMOLED displays with a shadow mask

Abstract— The bottlenecks in achieving high resolution for active‐matrix OLED (AMOLED) displays based on currently available manufacturing processes were evaluated and compared. The use of a shadow mask has proven to be viable for mass production, but the fabrication of high‐precision shadow masks becomes very difficult when the resolution exceeds 180 ppi. The latest breakthrough in increasing display resolution is presented. Without an increase in cost, the limitations of the conventional shadow‐mask process using novel subpixel designs have been successfully overcome. A high resolution reaching of 270 ppi has been successfully demonstrated on a 3‐in. VGA‐format AMOLED display, fabricated by using a shadow mask with a much lower resolution of 135 ppi. This innovative pixel design opens up the possibilities of manufacturing high‐resolution displays using a relatively low‐resolution shadow mask.     

Improvement of PDP discharge efficiency based on macro‐cell studies

Abstract— In this paper we explain how macro‐cells (real PDP cells scaled‐up a hundred times) with external and removable electrodes have been validated by comparison with real panels and modeling and used to optimize the luminous efficacy of real PDPs. We illustrate the application of the macroscopic PDP tool to optimize the electrode configuration of short‐gap discharges towards higher luminous efficacy, as well as its use in conjunction with 2D and 3D modeling to lower the operating voltages of high‐efficacy long‐gap discharges triggered by auxiliary electrodes.     

Pore‐free mold‐pattern‐transfer method for barrier ribs of HD PDPs

Abstract— Among various barrier‐rib manufacturing processes, the mold‐pattern‐transfer method has potential to reduce processing cost as well as the manufacture of high‐resolution pixels. In this study, the effects of major processing variables of the mold‐pattern‐transfer process on the formation of air‐trapped pores within barrier ribs were examined. The results indicated that with an optimum combination of the processing variables, barrier ribs without trapped defects can be produced, demonstrating the possibility of reducing the number of processing steps and costs of barrier ribs.     

Effects of diamond and AlN layers inserted beneath the phosphor layer on the discharge characteristics of PDPs

Abstract— In this study, the effects of diamond and AlN layers inserted beneath the phosphor layer of the rear plate of a PDP were investigated. The layers were formed via an osmotic‐pressure coating process. Macrocells and test panels were prepared to examine their effects on luminance and luminous efficacy. The results indicate that the layers primarily affect the glow‐discharge behavior and eventually enhance the luminous efficacy of the PDP, suggesting the possibile improvement in the performance of PDPs.     

Address‐While‐Display technique combined with gas‐discharge AND logic for driving AC‐PDPs

A hybrid AWD/AND drive technique has been developed in which an Address‐While‐Display (AWD) scheme is combined with an AND logic characteristic that gas discharges demonstrate. The AWD technique enables AC‐PDPs to be driven at high luminance, while the AND logic reduces the number of scan drivers by an order of magnitude. A detailed analysis of the addressing operation has been made. The hybrid drive utilizes the AND logic in two ways: (1) a combination of two voltage pulses and (2) a combination of a voltage pulse and discharge‐priming particles. It was found that the addressing operation requires the establishment of a discharge between the scan and data electrodes, and also between the scan and display electrodes.     

Protective layer for high‐efficiency PDPs driven at low voltage

Abstract— The sustain pulse voltage of a panel for 66‐kPa Ne + Xe (5–30%) with an (SrCa)O protective layer is 20–40% lower than that with an MgO protective layer. The luminous efficiency of the panel with a Ne + Xe (30%) (SrCa)O protective layer is 1.5 times that of the conventional panel with a Ne + Xe (10%) MgO protective layer; the sustain pulse voltages of these panels are almost the same. The power loss caused by panel capacitance is proportional to the second power of the sustain pulse voltage. Using the (SrCa)O protective layer for Xe (5–30%), the power loss is reduced by 35–60% compared with the MgO protective layer. It follows that, using the (SrCa)O protective layer, we can increase the Xe content with little power loss and thus achieve high‐efficiency PDPs. As for MgO and CaO with Xe ions, electrons are probably ejected from only the defect states. On the other hand, as for the SrO with Xe ions, it is likely that electrons can be ejected from not only defect states but also the valance band. This seems to be the reason why the driving voltage is lower with the (SrCa)O protective layer than with the MgO protective layer.     

High‐frequency drive of high‐Xe‐content PDPs for high efficiency and low‐voltage performance

Abstract— It has been well known that the luminous efficiency of PDPs can be improved by increasing the Xe content in the panel. For instance, the efficiency is improved by a factor 1.7 when the Xe content is increased from 3.5% to 30%. The sustain pulse voltage, however, increases from 180 to 230 V by a factor 1.3. It was found that the increase in the sustain pulse voltage can be suppressed by increasing the sustain pulse frequency. The high‐frequency operation further increases the luminous efficiency. If the Xe content is increased from 3.5% to 30% and the drive pulse frequency is increased from 147 to 313 kHz, the luminous efficiency becomes 2.7 times higher and the luminance 4.5 times higher. Furthermore, the increase in the sustain pulse voltage is suppressed 1.1 times, from 180 to 200 V. A mechanism of attaining high efficiency and low‐voltage performance can be considered as follows. A train of pulses is applied during a sustain period. As the sustain pulse frequency is increased, the pulse repetition rate becomes faster and a percentage of the space charge created by the previous pulse remains until the following pulse is applied. Due to the priming effect of these space charge, the discharge current build‐up becomes faster, the width of the discharge current becomes narrower, ion‐heating loss is reduced, and the effective electron temperature is optimized so that Xe atoms are excited more efficiently. The intensity of Xe 147‐nm radiation, dominant in low‐pressure Xe dis‐charges, saturates with respect to electron density due to plasma saturation. This determines the high end of the sustain pulse frequency.     

Effects of Xe content on wall‐voltage variation during address period in AC plasma‐display panel

Abstract— To investigate the influence of the gas condition, especially xenon (Xe) gas, on the wall‐voltage variation in relation to the electric‐field intensity during the address period, the wall voltages were measured under various Xe‐gas content ranging from 11 to 20% by using the V^t closed curve analysis method. It was observed that under a weak electric‐field intensity between the scan and address electrodes, the change in Xe content did not affect the wall‐voltage variation, even at a higher panel temperature of 65δC. However, under a strong electric‐field intensity, the wall‐voltage variations were reduced with an increase in the Xe content, confirming that a higher electric‐field intensity would be required to induce the wall‐voltage variation at a higher Xe content during the address period.