A small‐area and low‐power data driver IC using two‐stage DAC with a capacitor array for active matrix flat‐panel displays

A small‐area and low‐power data driver integrated circuit (IC) using a two‐stage digital‐to‐analog converter (DAC) with a capacitor array is proposed for active matrix flat‐panel displays. The proposed data driver IC employs a capacitor array in the two‐stage DAC so as to reduce the DAC area and eliminate the need for a resistor string, which has high‐power consumption. To verify the proposed two‐stage DAC, a 20‐channel data driver IC with the proposed 10‐bit two‐stage DAC was fabricated using a 0.18‐μm complementary metal–oxide–semiconductor process with 1.8 and 6 V complementary metal–oxide–semiconductor devices. The proposed 10‐bit two‐stage DAC occupies only 43.8% of the area of a conventional 10‐bit two‐stage DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.58/?0.52 least significant bit and +0.62/?0.59 least significant bit, respectively. The measured interchannel deviation of the voltage outputs is 8.8 mV, and the measured power consumption of the 20‐channel data driver IC is reduced to 7.1 mW, which is less than half of the power consumed by the conventional one.     

10‐bit source driver with resistor‐resistor‐string digital‐to‐analog converter

Abstract— A 10‐bit gray‐scale source driver using a resistor‐resistor‐string digital‐to‐analog converter (RR‐DAC) is proposed for a TFT‐LCD source driver. The 10‐bit RR‐DAC consists of an 8‐bit resistor‐string DAC and a two‐bit resistor‐string DAC without an intermediate unity‐gain buffer to isolate the parallel‐connected resistor string. The output deviation of the proposed source driver is less than ±3 mV. The chip area of the proposed 10‐bit source driver with an RR‐DAC is increased to 29% of that of an 8‐bit source driver.     

Peripheral circuit designs using low‐temperature p‐type poly‐Si thin‐film transistors

Abstract— P‐type low‐temperature (450°C) polycrystalline‐silicon thin‐film‐transistor circuits for peripheral driver integration in active‐matrix displays are proposed and verified. A low‐voltage (5 V) driven poly‐Si scan driver is designed by employing a level shifter and shift register. A source driver for six‐bit digital interface is proposed, and the building blocks such as latch, DAC, and analog buffer are described. The latch samples and holds the digital bits (D and D') without an output voltage loss. A new source‐follower type analog buffer is developed and exhibits a small offset deviation regardless of the V_TH variation of the buffer TFT. The simulation and measurement results ensure that the proposed circuits were successfully designed for p‐type panel integration.     

A 13‐bit universal column driver for various displays of OLED and LCD

A universal column driver is implemented in a 0.13‐µm high‐voltage CMOS process for not only TFT‐LCD but also OLED applications. The proposed column driver employs 13‐bit linear DAC to cover all gamma curves of display applications and address‐based configuration for intra‐ panel interface protocol to support both TV and IT applications. Measured results demonstrate the average voltage of output channels (AVO) is under 1mv, which satisfies 1‐LSB resolution at 18.5V of AVDD.     

Pixel structures using the negative feedback method for high‐resolution active matrix organic light‐emitting diode displays

Novel two pixel structures are proposed for high‐resolution active matrix organic light‐emitting diode displays. The proposed two pixels (pixel structures A and B) use the negative feedback method for high‐resolution displays that requires to have small‐sized storage capacitance. The proposed pixel structures A and B improve the luminance uniformity by reducing the voltage distortion in the storage capacitor. However, the proposed pixel structure A is vulnerable to the organic light‐emitting diode (OLED) degradation because the anode voltage of the OLED affects the emission current. In order to compensate the OLED degradation, the proposed pixel structure B stores the turn‐on voltage of OLEDs in the storage capacitor. The simulation results show that the emission current error of the proposed pixel structure B is improved by four times in comparison with the proposed pixel structure A when the OLED turn‐on voltage increases by 0.1 V. Also, the emission current error of the proposed pixel structure B when the threshold voltage of driving thin‐film transistors varies from ?2.2 to ?1.8 V is from ?0.69 least significant bit (LSB) to 0.13 LSB, which shows the excellent luminance uniformity. The proposed pixels are designed for 5.5‐in. full high‐definition displays.     

Compact and power‐saving polysilicon data driver with common‐decoder DA converter (CD‐DAC)

Abstract— A common‐decoder architecture for a data‐driver circuit fabricated by using a polysilicon process has been developed. The architecture achieves a compact circuit and low‐power consumption. In application to an integrated polysilicon data driver for small‐sized displays, this architecture reduces the area of the data driver by removing the vertical bus lines that occupy a large area. It also suppresses the power consumption of the data bus by reducing the number of driven lines in the data bus during word‐to‐word transitions from six to two. By using a conventional 4‐μm design rule, we fabricated an active‐matrix OLED (AMOLED) panel with an integrated six‐bit data‐driver circuit with 384 outputs. The driver circuit had a height of 2.6 mm and a pitch between output lines of 84 μm. The maximum power consumption of the driver was only 5 mW, i.e., 3.8 mW for logic‐data transfer and 1.2 mW for reference‐voltage source. Furthermore, we also fabricated an active‐matrix LCD (AMLCD) panel including driver circuits of the same type as the integrated elements. Six‐bit full‐color images were successfully displayed on both panels.     

A timing controller embedded driver IC with 3.24‐Gbps eDP interface for chip‐on‐glass TFT‐LCD applications

This paper presents a timing controller embedded driver (TED) IC with 3.24‐Gbps embedded display port (eDP), which is implemented using a 45‐nm high‐voltage CMOS process for the chip‐on‐glass (COG) TFT‐LCD applications. The proposed TED‐IC employs the input offset calibration scheme, the zero‐adjustable equalizer, and the phase locked loop‐based bang‐bang clock and data recovery to enhance the maximum data rate. Also, the proposed TED‐IC provides efficient power management by supporting advanced link power management feature of eDP standard v1.4. Additionally, the smart charge sharing is proposed to reduce the dynamic power consumption of output buffers. Measured result demonstrates the maximum data rate of 3.24 Gbps from a 1.1 V supply voltage with a 7.9‐inch QXGA 60‐Hz COG‐LCD prototype panel and 44% power saving from the display system.     

A reduced‐voltage differential signaling (RVDS) interface for chip‐on‐glass TFT‐LCD applications

Abstract— Reduced‐voltage differential signaling (RVDS) is a novel interface for TFT‐LCD panels with a chip‐on‐glass (COG) structure, which has a point‐to‐point topology and a voltage mode differential signaling scheme. The voltage‐driving interface scheme has advantages in high‐speed operation owing to its relatively small time constant for the resistive channel condition. And reduced‐voltage signaling can reduce the power consumption of a transmitter. The display source driver IC with an RVDS interface, which is fabricated by using a 0.25‐μm CMOS process with a 2.5‐V logic supply voltage, offers a high data rate up to 500 Mbps, low‐current consumption of 2.2 mA, and good EMI characteristics. Also, an RVDS interface has programmable options that control the bandwidth, system power, and EMI performance. Therefore, the RVDS interface is a competitive solution for low‐power, low‐cost, and slim notebook applications.     

A 1.4‐Gbps intra‐panel interface with low‐power and low‐EMI schemes for Tablet PC applications

An intra‐panel interface addressing all of the high‐speed, low‐power, and low‐electromagnetic interference (EMI) requirements for tablet personal computer applications is presented. This work proposes an adaptive clock window scheme to achieve 1.4‐Gbps data‐rate. For EMI suppression, data scrambling, horizontal blank period pattern scrambling, and novel clock and data recovery circuit are introduced. Lastly, for power‐saving, the proposed interface dynamically biases source driver's output buffers and employs early charge sharing by controlling the configuration data. For verification, a WQXGA thin‐film transistor liquid crystal display system is implemented with the timing controller and source driver ICs that are fabricated using 65‐nm and 180‐nm complementary metal‐oxide semiconductor (CMOS) processes, respectively. The liquid crystal display system demonstrates maximum operation speed of 1.4 Gbps and suppression of EMI noise in LTE Band‐20 and GSM 850 bands. The proposed power‐saving schemes achieve 4.3% reduction in total power consumption by source driver IC, which reaches about 85% of power consumption by enhanced reduced‐voltage differential signaling interface circuit.     

Design of a low‐power‐consumption a‐IGZO TFT‐based Vcom driver circuit with long‐term reliability

Abstract— An amorphous‐InGaZnO (a‐IGZO) thin‐film transistor (TFT)‐based Vcom driver circuit that has long‐term reliability and can be integrated with the pixel array on a panel has been designed. Owing to the Vcom inversion, the power consumed by the proposed driving scheme is 40% less than that consumed by the conventional line‐inversion method. The high mobility (>10 cm²/V‐sec) of the a‐IGZO TFTs allows the integration of devices with small channel widths (<750 μm) and thus keeps the overall device size small, which is important for displays with narrow bezels. The lifetime of the Vcom driver is improved by AC driving (by clocking the n‐th and (n + 1)‐th frame with 20 and 0 V, respectively) of the buffer TFTs.     

Low‐temperature poly‐Si TFT‐LCD with an integrated analog circuit

We have developed a 6‐bit D/A converter and amplifier integrated low‐temperature poly‐Si TFT‐LCD in which an integrated signal‐line driver is driven by a 5‐V power supply. We have employed a D/A converter including a new capacitor array and an original amplifier comprised of serially connected comparators to achieve high accuracy. The D/A converter performs gamma correction using upper significant bits of input data. Control signals for these circuits were generated by the integrated timing circuit. These advances in integration have been achieved for the first time using 3‐μm design rule and improved LTPS TFT technologies and provide an advanced display system with lower power consumption, smaller module size, and higher durability.     

A 4‐bit ultra‐wideband complementary metal‐oxide‐semiconductor attenuator with low root‐mean‐square amplitude error

This article presents the 4‐bit ultra‐wideband complementary metal‐oxide‐semiconductor (CMOS) attenuator in a standard 0.18‐μm CMOS process. This design adopts switched bridge‐T type topologies for each attenuation bit. Based on insertion losses and input P_1‐dB considerations, the circuit performances can be optimized by the proper bit ordering arrangement. Therefore, the bit ordering 0.5‐4‐2‐1 dB is employed in the 4‐bit attenuator. Moreover, series inductors are added between each bit to further improve the input and output return losses. Measured results demonstrate that the attenuation range of the circuit is 7.5 dB with 0.5 dB step and the root‐mean‐square (RMS) amplitude error is between 0.11 and 0.13 dB from 3.1 to 10.8 GHz. The differences between simulated and measured RMS amplitude errors are less than 0.2 dB, which demonstrates the good agreement and feasibility of the design concept. The measured input P_1‐dB is 15 dBm at 5 GHz and the chip area is 1.12 mm² including all testing pads.     

Bit‐depth extension: Overcoming LCD‐driver limitations by using models of the equivalent input noise of the visual system

Abstract— Continuous tone, or “contone,” imagery usually has 24 bits/pixel as a minimum, with 8 bits each for the three primaries in typical displays. However, lower‐cost displays constrain this number because of various system limitations. Conversely, higher‐quality displays seek to achieve 9–10 bits/pixel/color, though there may be system bottlenecks limited to 8. The two main artifacts from reduced bit‐depth are contouring and loss of amplitude detail; these can be prevented by dithering the image prior to these bit‐depth losses. Our technique builds on Roberts's noise‐modulation idea and the subsequently influenced work in halftoning for hardcopy and dithering for displays. However, most halftoning/dithering work was primarily directed to displays at the lower end of bits/pixel (e.g., 1 bit as in halftoning) and higher ppi. We approach the problem from the higher end of bits/pixel/color, for example, 6–8, and lower spatial resolution (<100 ppi), which changes the game substantially from halftoning experience. Instead of spatial dither, it is better to use an amplitude dither. In addition, dynamic displays allow for the use of a temporal dithering component. This paper will report on techniques and observations made in achieving contone quality on ～100‐or‐less‐ppi LCDs starting from 4‐ to 8‐bit driver limits, and resulting with no visible dither patterns, noise, contours, or loss of amplitude detail at viewing distances as close as the near focus limit (～120 mm).     

An integrated poly‐Si TFT current data driver with a data‐line pre‐charge function

Abstract— We have developed an integrated poly‐Si TFT current data driver with a data‐line pre‐charge function for active‐matrix organic light‐emitting diode (AMOLED) displays. The current data driver is capable of outputting highly accurate (±0.8%) current determined by 6‐bit digital input data. A novel current‐programming approach employing a data‐line pre‐charge function helps achieve accurate current programming at low brightness. A 1.9‐in. 120 × 136‐pixel AMOLED display using these circuits was demonstrated.     

Ultra‐low‐power LTPS TFT‐LCD technology using a multi‐bit pixel memory circuit

Abstract— Two types of low‐temperature poly‐Si TFT LCDs, which integrate a multi‐bit memory circuit and a liquid‐crystal driver within a pixel, have been developed using two different TFT process technologies. Both a 1.3‐in. 116‐ppi LCD having a 2‐bit pixel memory and a 1.5‐in. 130‐ppi LCD having a 5‐bit pixel memory consume very little power, less than 100 μW, which indicates that this technology is promising for mobile displays.     

A low‐profile quad‐port UWB MIMO antenna using defected ground structure with dual notch‐band behavior

A compact (45 × 45 × 1.6 mm³) ultrawide‐band (UWB), multiple‐input multiple‐output (MIMO) design using microstrip line feeding is presented. The proposed design comprises four elliptical monopoles placed orthogonally on a cost‐effective FR‐4 substrate. In order to improve the impedance bandwidth and lessen the return loss of the MIMO antenna, defects in ground plane are created by etching symmetrical square slots and half‐rings. Moreover, a different method (of unsymmetrical H‐shaped slot with C‐shaped slot) was proposed into the patch to introduce dual‐band rejection performance from UWB at center frequency 5.5 GHz (covering lower WLAN as well as upper WLAN) and 7.5 GHz (X band). In addition, a stub is introduced at the edge of each defected ground structure to obtain isolation >–22 dB covering entire performing band from 2 to 16.8 GHz (where, S₁₁ < –10 dB). The proposed design has miniaturized size, very low envelop correlation coefficient less than 0.1, stable gain (2‐4 dBi except for notch bands). Furthermore, various MIMO performance parameters are within their specifications, such as diversity gain (= 10 dB), total active reflection coefficient (<–5 dB, and channel capacity loss (<0.35 bits/s/Hz). The presented design is optimized using the HFSS software, and fabricated design is tested using vector network analyzer. The experimental results are in good agreement with the simulation results.     

Clamped‐inverter circuit architecture for luminescent‐period‐control driving of active‐matrix OLED displays

Abstract— An innovative pixel‐driving technology for high‐performance active‐matrix OLED flat‐panel displays is described. Called “clamped‐inverter circuit architecture,” it uses luminescent‐period‐control driving to reduce the inter‐pixel non‐uniformity caused by the device‐to‐device variability of low‐temperature poly‐Si TFTs. A prototype full‐color display shows a luminous deviation of less than 1.6%, which corresponds to only the LSB‐error in 6‐bit gray‐scale.     

Novel back‐channel‐etch process flow based a‐IGZO TFTs for circuit and display applications on PEN foil

In this study, we report high‐quality amorphous indium–gallium–zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) fabricated on a polyethylene naphthalate foil using a new back‐channel‐etch (BCE) process flow. The BCE flow allows a better scalability of TFTs for high‐resolution backplanes and related circuits. The maximum processing temperature was limited to less than 165 °C in order to ensure good overlay accuracy (<1 µm) on foil. The presented process flow differs from the previously reported flow as we define the Mo source and drain contacts by dry etch prior to a‐IGZO patterning. The TFTs show good electrical performance, including field‐effect mobilities in the range of 15.0 cm²/(V·s), subthreshold slopes of 0.3 V/decade, and off‐currents <1.0 pA on foil. The threshold voltage shifts of the TFTs measured were less than 1.0 V after a stressing time of 10⁴ s in both positive (+1.0 MV/cm) and negative (?1.0 MV/cm) bias directions. The applicability of this new BCE process flow is demonstrated in a 19‐stage ring oscillator, demonstrated to operate at a supply voltage of 10 V with a stage delay time of 1.35 µs, and in a TFT backplane driving a 32 × 32 active‐matrix organic light‐emitting diode display.     

One‐bit in‐phase observation for direct learning‐based digital predistortion with modified frequency‐domain delay estimation and alignment

This article proposes a novel digital predistortion (DPD) implementation method for RF power amplifiers. The new approach adopts only one 1‐bit comparator in the feedback path to observe the in‐phase (I) or the quadrature (Q) component of the error signal between the input and the output signals. To this end, the theoretical derivation of the in‐phase observation based on direct learning architecture (DLA) DPD is first given in this article, by combining the existing 1‐bit method and the low‐cost in‐phase observation. To facilitate the delay estimation and alignment, a modified iterative frequency‐domain delay estimation is presented, which only acquires either I or Q components of the output signal to achieve satisfied delay estimation. Experimental results show that the proposed DPD method decreased the normalized mean square error (NMSE) and the adjacent channel power ratio (ACPR) to less than ?42 and ?51 dB, respectively, which indicates that the proposed DPD system can achieve comparable performance as the existing DPD identification techniques with lower implementation complexity.     

An efficient high payload ±1 data embedding scheme

Embedding of confidential data in the least significant bit of an image is still an attractive method of steganography. Utilizing the full capacity of cover images by embedding one bit of data per pixel, using methods such as LSB flipping or LSB matching, usually decreases the security, making the algorithm vulnerable to steganalytic attacks. In this paper, we propose a novel efficient high payload ±1 steganographic method based on a special two variable binary function. This function uses the information of the least two significant bit planes of the cover image for the embedding and extraction purposes. Embedding efficiency, defined as the number of embeddable bits per one change in the cover medium, is a good criterion for concurrent evaluation of the capacity and security. Rather than randomly selecting +1 or −1, we achieve higher embedding efficiencies by choosing the correct modification component. In the generalized form of the proposed method, n bits of data are embedded in n pixels of the cover medium, by causing one unit change in only one third of these pixels. Analytical and experimental results demonstrated that the proposed method provides higher embedding efficiency than the other LSB embedding schemes. The proposed method is also applicable to other digital cover media.