Performance Benefits of Diamond-like Carbon Liner Stressor in Strained P-Channel Field-Effect Transistors With Silicon–Germanium Source and Drain

We report the first investigation of the impact of diamond-like carbon (DLC) high-stress liner on strained p-channel metal–oxide–semiconductor field-effect transistors (p-FETs) having silicon–germanium (SiGe) source-and-drain (S/D) stressor. The DLC exhibited a very high compressive stress of $sim$5 GPa. At a fixed $I_{ rm off}$ of $hbox{1}times hbox{10}^{-7} hbox{A}/mu hbox{m}$, the DLC liner stressor contributed to a further 11% $I_{rm on}$ enhancement for p-FETs with $hbox{Si}_{0.75} hbox{Ge}_{0.25}$ S/D. This is the first demonstration that further boost in device performance in a p-FET that is already strained using $hbox{Si}_{0.75}hbox{Ge}_{0.25}$ S/D can be achieved with DLC liner stressor. Due to the extremely high intrinsic compressive stress of the DLC, a very small DLC thickness of $sim$27 nm is sufficient for achieving significant strain effect and performance enhancement.      

Strained-SOI n-Channel Transistor With Silicon–Carbon Source/Drain Regions for Carrier Transport Enhancement

A novel 80 nm gate length strained-Si n-channel transistor structure with lattice-mismatched source and drain (S/D) formed on thin-body silicon-on-insulator substrate is reported. The strained transistor features silicon–carbon$(hboxSi_1 - yhboxC_y)$S/D regions, which are pseudomorphically grown by selective epitaxy. The incorporated carbon mole fraction$y$is 0.01. The lattice mismatch between$hboxSi_0.99hboxC_0.01$and Si results in lateral tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron mobility enhancement. The implementation of the$hboxSi_0.99hboxC_0.01$stressors provides a substantial drive current$I_ Dsat$enhancement of 11% over a control transistor at a gate length of 80 nm and a width of$simhbox1.1 muhboxm$, while the enhancement for the linear drive current$I_ Dlin$is approximately two times larger. Pulse measurements were also performed to correct for self-heating effects.     

Strained ${rm n}$-MOSFET With Embedded Source/Drain Stressors and Strain-Transfer Structure (STS) for Enhanced Transistor Performance

A novel-channel MOS transistor with a silicon-germanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated. The additional SiGe structure couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. We termed the SiGe region a strain-transfer structure due to its role in enhancing the transfer of strain from lattice-mismatched S/D stressors to the channel region. Numerical simulations were performed using the finite-element method to explain the strain-transfer mechanism. A significant drive current I_DSAT improvement of 40% was achieved over the unstrained control devices, which is predominantly due to the strain-induced mobility enhancement. In addition, the impact of scaling the device design parameters on transistor drive current performance was investigated. Guidelines on further performance optimization in such a new device structure are provided.     

Strained p-Channel FinFETs With Extended Π -Shaped Silicon–Germanium Source and Drain Stressors

Further enhancement of performance in a strained p-channel multiple-gate or fin field-effect transistor (FinFET) device is demonstrated by utilizing an extended-Pi-shaped SiGe source/drain (S/D) stressor compared to that utilizing only Pi-shaped SiGe S/D. With the usage of a longer hydrofluoric acid cleaning time prior to the selective-epitaxy-raised S/D growth, a recess in the buried oxide is formed. This recess allows the subsequent SiGe growth on the fin sidewalls of the S/D regions to extend into the recessed buried oxide to provide a larger compressive stress in the channel for enhanced electrical performance compared to a device with SiGe S/D stressor. Process simulation shows that longitudinal compressive stress in the channel region is higher in a FinFET with extended-Pi-SiGe S/D than that with Pi-SiGe S/D. An enhancement of 26% in the drive current was experimentally observed, demonstrating further boost in enhancement of strained p-channel FinFET with little additional cost using this novel process.     

Strained Thin-Body p-MOSFET With Condensed Silicon-Germanium Source/Drain for Enhanced Drive Current Performance

Strained p-MOSFETs with silicon-germanium (SiGe) source and drain (S/D) stressors were fabricated on thin-body silicon-on-insulator (SOI) substrate using a novel local oxidation or Ge condensation technique. By directly growing SiGe on the S/D regions and followed by a local Ge condensation process, the challenges imposed on Si recess etch on thin-body SOI substrates can be alleviated. In the Ge condensation step, the Ge content in the S/D regions may also be increased. At a gate overdrive of -1 V, strained p-MOSFETs show an enhancement in the saturation drive current I_on of up to 38% over the control p-MOSFETs. This significant I_on enhancement is attributed to strain-induced band structure modification, which reduces the hole effective mass along the transport direction. The improved series resistance of the strained devices with SiGe S/D accounted for approximately one-third of the I_on enhancement.     

Performance Enhancement in Uniaxial Strained Silicon-on-Insulator N-MOSFETs Featuring Silicon–Carbon Source/Drain Regions

We report the demonstration of a novel strained silicon-on-insulator N-MOSFET featuring silicon-carbon (Si_1-yC_y) source and drain (S/D) regions, tantalum nitride metal gate, and hafnium-aluminum oxide high-k gate dielectric. Due to the lattice mismatch between Si_0.99C_0.01 S/D stressors and Si, a lateral tensile strain is induced in the transistor channel, leading to substantial electron mobility enhancement. At a fixed OFF-state leakage of 100 nA/mum, the Sii-j/C_1-yC_y S/D N-MOSFET having a width of 4.7 mum achieves a drive current Josat enhancement of 16% over a control N-MOSFET. This iDsat enhancement, which is primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate length LG due to an increased strain level in the transistor channel as the Si_1-yC_y S/D stressors are placed in closer proximity. Slightly improved series resistance with Si_1-yC_y S/D regions in a strained N-MOSFET accounted for approximately 2% I_Dsat gain. In addition, a reduction of device width is found to reduce the drive current enhancement of the N-MOSFETs due to the presence of a transverse compressive strain in the transistor channel induced by the isolation regions.     

Hot-Carrier Effects in Strained n-Channel Transistor With Silicon–Carbon (Si1 − yCy) Source/Drain Stressors and Its Orientation Dependence

We report the hot-carrier effects in a novel strained n-channel transistor (n-FET) featuring silicon-carbon source and drain (Si_1-yC_y S/D) stressors, and its dependence on channel orientations for the first time. Due to strain-induced bandgap reduction, Si_1-yC_y S/D n-FETs show enhanced impact ionization and therefore more pronounced drive current degradation over a control n-FET. As a consequence of the increased interface state generation, a strained n-FET with [010] channel shows worse hot-carrier reliability over a transistor with the conventional [110] channel, which leads to a larger shift in threshold voltage and subthreshold swing. In addition, a hot-carrier lifetime projection shows a dependence of operating drain voltage on the channel orientation of the strained n-FET.     

Silicon–Carbon Stressors With High Substitutional Carbon Concentration and In Situ Doping Formed in Source/Drain Extensions of n-Channel Transistors

We report the first demonstration of n-channel field-effect transistors (N-FETs) with in situ phosphorus-doped silicon-carbon (SiCP) stressors incorporated in the source/drain extension (SDE) regions. A novel process which formed recessed SDE regions followed by selective epitaxy of SiCP was adopted. High in situ doping contributes to low series resistance to channel resistance ratio and is important for reaping the benefits of strain. Substitutional carbon concentration was varied, showing enhanced drive current with increased for comparable off-state leakage, series resistance, and control of short-channel effects. A record high carbon substitutional concentration of 2.1% was achieved. Use of heavily doped silicon-carbon stressor with large lattice mismatch with respect to Si and placed in close proximity to the channel region in the SDE regions is expected to be important for strain engineering in nanoscale N-FETs.     

Drive-Current Enhancement in Ge n-Channel MOSFET Using Laser Annealing for Source/Drain Activation

A gate-first self-aligned Ge nMOSFET with a metal gate and CVD$hboxHfO_2$has been successfully fabricated using KrF laser annealing (LA) as dopant-activation annealing. By applying an aluminum laser reflector on TaN metal gate, source/drain (S/D) regions are selectively annealed without heating the gate stack. Small S/D resistance and good gate-stack integrity are achieved simultaneously. As a result, a larger drive current and a lower threshold voltage are achieved in Ge nMOSFET using LA activation than that using conventional rapid thermal annealing activation.     

New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate

Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations.      

Source/Drain Engineering for Parasitic Resistance Reduction for Germanium p-MOSFETs

A reduction of parasitic resistance is presented with incorporation of preamorphization implantation (PAI) and self-aligned Cu₃Ge in the source/drain region for germanium p-MOSFETs. Full activation of boron in the amorphous layer can be obtained during solid-phase epitaxial growth, and a concentration as high as 4 x 10²⁰/cm³ is achieved. This nonthermal equilibrium concentration is maintained during the subsequent Cu₃Ge formation. Cu₃Ge is adopted as a contact metal in germanium p-MOSFETs for the first time, due to its superior electrical properties (6.8 muOmegaldrcm for resistivity and ~1 x 10^-7 Omega cm² on p-type germanium for specific contact resistance). The fabricated p+/n diode yields a five order of magnitude between forward and reverse currents, which can be attributed to the reduction in parasitic resistance. The low reverse current mitigates concerns of possible deep-level traps introduced by copper. It also confirms the nonexistence of extended defects created by PAI as a result of the unique role of vacancies in germanium. With high dopant concentrations achieved by PAI and low resistance of Cu³Ge, excellent MOSFET characteristics are demonstrated in self-aligned Cu³Ge p-MOSFETs. A 15% mobility enhancement over Si universal mobility and a 60% parasitic resistance reduction are achieved.     

Platinum Germanosilicide as Source/Drain Contacts in P-Channel Fin Field-Effect Transistors (FinFETs)

In this paper, platinum germanosilicide (PtSiGe) was investigated extensively as an alternative to nickel germanosilicide (NiSiGe) for contact formation on silicon-germanium (SiGe) source/drain (S/D) stressors. We show that PtSiGe has superior thermal and morphological stability as compared to NiSiGe. Our results further show that the formation of PtSiGe yields a low hole barrier height (Phi_B ^P) of 215 meV in a self-aligned process. We also demonstrated the integration of PtSiGe contacts in FinFET devices. FinFETs with PtSiGe contacts achieve a 27% reduction in external resistance (R_EXT) compared to FinFETs with NiSiGe contacts. Statistical comparison reveals that the drive current performance is enhanced by 21% while maintaining comparable control of short-channel effects. These results illustrate the potential of forming contacts with low Schottky barrier heights using PtSiGe in strained transistors with SiGe S/D stressors, thereby reducing R_EXT and extending transistor performance.     

Vertical n-Channel Poly-Si Thin-Film Transistors With Symmetric S/D Fabricated by Ni-Silicide-Induced Lateral-Crystallization Technology

We have successfully developed and fabricated the vertical n-channel polycrystalline silicon thin-film transistors with symmetric S/D fabricated by Ni-silicide-induced lateral-crystallization technology (NSILC-VTFTs). The NSILC-VTFTs are S/D symmetric devices and equivalent to dual-gate devices. The dual-gate structure of NSILC-VTFTs can moderate the lateral electrical field in the drain depletion region, significantly reducing the leakage current. In NSILC-VTFTs, the Ni accumulation and grain boundaries induced from S/D sides can be centralized in the $hbox{n}^{+}$ floating region. The effects of Ni accumulation in symmetric VTFTs crystallized by NSILC and metal-induced lateral crystallization are studied. In addition, a two-step lateral crystallization has been introduced to improve the crystal integrity through secondary crystallization. The NSILC-VTFTs crystallized by two-step lateral crystallization show a steep subthreshold swing of 180 mV/dec and field effect mobility $mu = hbox{553} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ without $hbox{NH}_{3}$ plasma treatment.      

On the Low-Frequency Noise of pMOSFETs With Embedded SiGe Source/Drain and Fully Silicided Metal Gate

The low-frequency noise of silicon pMOSFETs with embedded SiGe source/drain (S/D) regions is studied. The gate stack consists of HfSiON/SiO₂ covered by a fully silicided gate electrode. S/D regions with different Ge content and thickness have been processed. It is shown that, while mobility and drive current are significantly enhanced by this strain-engineering approach, the 1/f noise is little affected, irrespective of the germanium content or thickness of the epitaxial SiGe S/D layers, i.e., the amount of compressive strain in the channel. From this, it is derived that, first of all, the embedded (S/D) processing does not degrade the gate-stack quality and that, second, no evidence of an intrinsic strain effect on the 1/f noise is observed here.     

A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process

In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 10⁷ to 1.39 times 10⁷. Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.     

Laser Annealing of Amorphous Germanium on Silicon–Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

We report the first demonstration of a novel germanium-enrichment process for forming a silicon-germanium (SiGe) source/drain (S/D) stressor with a high Ge content. The process involves laser-induced local melting and intermixing of a Ge layer with an underlying Si_0.8Ge_0.2 S/D region, leading to a graded SiGe S/D stressor with a significant increase in the peak Ge content. Various laser fluences were investigated for the laser annealing process. The process is then successfully integrated in a device fabrication flow, forming strained silicon-on-insulator p-channel field-effect transistors (p-FETs) with a high Ge content in SiGe S/D. A drive current enhancement of ~ 12% was achieved with this process, as compared to a strained p-FET with Si_0.8Ge_0.2 S/D p-FETs. The I _Dsat enhancement, primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate lengths.     

Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies

The asymmetric source/drain extension (ASDE) transistor can be a suitable option because of improved short channel effects in technology nodes beyond 32 nm. In this paper, we have analyzed the impact of asymmetric drain extension reduction on the device metrics, namely, gate-to-drain capacitance, drain current, subthreshold leakage, and gate tunneling leakage current. Also, analytical models have been developed to model the effect of the ASDE devices. Based on our proposed analytical model, SPICE-compatible transistor models have been developed to include the ASDE device structure as possible design options. With our SPICE-compatible transistor models, large-scale circuit simulation can be performed to evaluate the benefits and the overheads associated with the ASDE devices. It is observed from circuit simulations that there is an optimal drain extension length which is different from the source extension length. With the ASDE devices, the circuit power delay product can effectively be reduced by almost 35% with respect to the conventional symmetric devices.     

WSe2场效应晶体管的源漏接触特性研究

二硒化钨(WSe2)具有双极导电特性,可以通过外界掺杂或改变源漏金属来调节载流子传输类型,是一类特殊的二维纳米材料,有望在未来集成电路中成为硅(Si)的替代材料.文章采用理论与实验相结合的方式系统分析了 WSe2场效应晶体管中的源漏接触特性对器件导电类型及载流子传输特性的影响,通过制备不同金属作为源漏接触电极的WSe2场效应晶体管,发现金属/WSe2接触的实际肖特基接触势垒高低极大地影响了晶体管的开态电流.源漏金属/WSe2接触特性不仅取决于接触前理想的费米能级差,还受到界面特性,特别是费米能级钉扎效应的影响.     

Source/Drain Series-Resistance Effects in Amorphous Gallium–Indium Zinc-Oxide Thin Film Transistors

In this letter, we investigated the effects of source/drain series resistance on amorphous gallium-indium-doped zinc-oxide (a-GIZO) thin film transistors (TFTs). A linear least square fit of a plot of the reciprocal of channel resistance versus gate voltage yields a threshold voltage of 3.5 V and a field-effect mobility of about 13.5 cm²/Vldrs. Furthermore, in a-GIZO TFTs, most of the current flows in the distance range of 0-0.5 mum from the channel edge and shorter than that in a-Si:H TFTs. Moreover, unlike a-Si:H TFTs, a-GIZO TFTs did not show an intersection point, because they did not contain a highly doped ohmic (n+) layer below the source/drain electrodes.     

Novel Offset-Gated Bottom Gate Poly-Si TFTs With a Combination Structure of Ultrathin Channel and Raised Source/Drain

We propose an offset-gated bottom gate polycrystalline silicon thin-film transistor (TFT), with a combination structure of ultrathin channel and raised source/drain, employing a simple process of the back surface exposure. It is experimentally and simulatively demonstrated that the new device has lower leakage current and better saturation characteristics, as compared with the conventional non offset TFT, due to the lateral electric field near the drain, which is reduced by the proposed structure. Moreover, the proposed TFT exhibits much better ON/OFF current ratio because the high current drive due to the raised source/drain structure is enough to compensate for the ON-state current reduction due to the offset-gate structure.