Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion

Capacitive crosstalk between adjacent signal wires has significant effect on performance and delay uncertainty of point-to-point on-chip buses in deep submicrometer (DSM) VLSI technologies. We propose a hybrid polarity repeater insertion technique that combines inverting and non-inverting repeater insertion to achieve constant average effective coupling capacitance per wire transition for all possible switching patterns. Theoretical analysis shows the superiority of the proposed method in terms of performance and delay uncertainty compared to conventional and staggered repeater insertion methods. Simulations at the 90-nm node on semi-global METAL5 layer show around 25% reduction in worst case delay and around 86% delay uncertainty minimization compared to standard bus with optimal repeater configuration. The reduction in worst case capacitive coupling reduces peak energy which is a critical factor for thermal regulation and packaging. Isodelay comparisons with standard bus show that the proposed technique achieves considerable reduction in total buffers area, which in turn reduces average energy and peak current. Comparisons with staggered repeater which is one of the simplest and most effective crosstalk reduction techniques in the literature show that hybrid polarity repeater offers higher performance, less delay uncertainty, and reduced sensitivity to repeater placement variation.      

An adjustable output driver with a self-recovering Vpp generatorfor a 4M×16 DRAM

This paper describes an adjustable output driver with a self-recovering Vpp generator for a 4M×16 DRAM. Its driver characteristics can easily be switched between fast and slow modes in the assembly process. With a small inductance load, the driver operates 2.5 ns faster in fast mode than in slow mode. In slow mode, this driver reduces the initial drive current and prevents ringing waveforms even with a large inductance load. For example, with a 5-pF capacitance load and a 20-cm wire, the ringing amplitude in slow mode is reduced to 1/3 of fast mode. Users can select the output driver operating mode that best suits their application. The self-recovering Vpp generators feed 16 output drivers and control the generator capacity according to the data pattern to supply the exact amount of Vpp charge consumed by the output drivers. The Vpp generator saves 3.9 mA on average in 25-ns read cycle     

A robust, load-insensitive pad driver

A new approach to implement load-insensitive integrated pad drivers in monolithic integrated circuits is presented. The design utilizes a source follower topology along with a simple negative feedback approach to fix and control both rise and fall times independent of loading capacitance. This novel technique was used to implement a differential output pad driver for Universal Serial Bus design in a standard 0.35-μm/3-V CMOS technology. The two drivers occupy less than 0.15 mm² of die area and can handle a capacitive load of 0-100 pF and 0-800 pF for 1.2- and 1.5-Mbps data rates, respectively. Measured transition times for 1.2 Mbps (with 50 pF) and 1.5 Mbps (with 350 pF) data rates were 17 and 250 ns, respectively     

Low-Voltage Bootstrapped CMOS Drivers With Efficient Conditional Bootstrapping

In this paper, a set of low-voltage bootstrapped CMOS drivers are presented to reduce power consumption and improve switching speed for driving a large capacitive load. The proposed drivers can reduce the power consumption by making bootstrap operations conditional to input statistics. They also improve switching speed by providing larger bootstrap voltages for the same amount of integrated bootstrap capacitance as compared with conventional bootstrapped drivers. The proposed drivers were designed using 0.18- CMOS technology. The comparison results indicate that the proposed drivers achieve power savings up to 97% with 13%-22% improvements on switching speed as compared with the conventional design.     

Voltage-pulse driven harmonic resonant rail drivers for low-power applications

We describe a new design technique for efficient harmonic resonant rail drivers. The proposed circuit implementation is coupled to a standard pulse source and uses only discrete passive components and no external dc power supply. It can thus be externally tuned to minimize the consumed power in the target IC. A new design technique based on current-fed voltage pulse-forming network theory is proposed to find the value of each discrete component for a target frequency and a given load capacitance. The proposed circuit topology can be used to generate any desired periodic 50% duty-cycle waveform by superimposing multiple harmonics of the desired waveform, however, this paper focuses on the generation of trapezoidal-wave clock signals. We have tested the driver with a capacitive load between 38.3 and 97.8 pF with clock frequency ranging between 0.8 and 15 MHz. The overall power dissipation for our second-order harmonic rail driver is 19% of fC/sub L/V/sup 2/ at 15 MHz and 97.8 pF load.     

Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses

This paper demonstrates that driver preemphasis technique can be used for on-chip global buses to increase signal channel bandwidth. Compared to conventional repeater insertion techniques, driver preemphasis saves repeater layout complexity and reduces power consumption by 12%-39% for data activity factors above 0.1. A driver circuit architecture using voltage-mode preemphasis technique was tested in 0.18-mum CMOS technology for 10-mm long interconnects at 2 Gb/s     

Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect

In this paper, we propose a new circuit technique called self-timed regenerator (STR) to improve both speed and power for on-chip global interconnects. The proposed circuits are placed along global wires to compensate the loss in resistive wires and to amplify the effect of wire inductance in the wires to enable transmission line like behavior. For different wire widths, the number of STR and sizing of the transistors are optimized to accelerate the signal propagation while consuming minimum power. In 90-nm CMOS technology, STR design achieved a delay improvement of 14% over the conventional repeater design. Furthermore, 20% power reduction is achieved for iso-delay, and 8% delay improvement for iso-power compared with the repeater design. The proposed technique has also been applied to a clock distribution network, reducing clock power by 26%.     

On the design and optimization of symmetric low swing to high swing level converter for on-chip interconnects

This paper reports a series of symmetric high performance, low to full swing level converters (udld1-converter to udld5-converter) for recovering signal levels at the receiver end of the global interconnects with large capacitive loads. The proposed udld5-converter provides a matching receiver for the up-down low swing voltage driver (UDLD) signaling style for driving the global interconnect lines. When implemented on 0.13 μm CMOS 1.2 V technology, the udld5-converter performs 16% faster, reduces the energy per switching event by 4%, the energy-delay product by 19%, and the active area by 10%, when compared with a counterpart up low swing voltage driver (ULD) level converter (uld-converter). The proposed level converter receivers, each provide a different performance energy saving trade off. The paper also provides comparative performance evaluation of the various proposed level converters and uld-converter.     

纳米MnO_2的水热合成及其在LiPF_6中的电容行为

以硫酸锰和次氯酸钾为主要原料,在酸性条件下水热合成了MnO2纳米丝球。通过XRD和SEM分析了MnO2的晶体结构和表面形态。应用循环伏安、恒电流充放电、交流阻抗等方法研究了该MnO2电极在1mol/LLiPF6(DMC+EC)有机电解液中,0～2.5V的电位的电容行为。结果表明:样品为α-MnO2,丝球平均直径约20μm,单丝直径约80nm,长度在3～5μm。该MnO2电极具有良好的电容性能,180mA/g电流密度下初始比容量达129.3F/g,相应能量密度为45.7Wh/kg。     

Optimal global interconnects for GSI

Performance of a high-speed chip is largely affected by both latency and bandwidth of global interconnects, which connect different macrocells. Therefore, one of the important goals is to design high-bandwidth and fast buses that connect a processor and its on-chip cache memory or link different processors within a multiprocessor chip. In this paper, the width of global interconnects is optimized to achieve a large "data-flux density" and a small latency simultaneously. Data-flux density is the product of interconnect bandwidth and reciprocal wire pitch, which represents the number of bits per second that can be transferred across a unit-length bisectional line. The optimal wire width, which maximizes the product of data-flux density and reciprocal latency, is independent of interconnect length and can be used for all global interconnects. It is rigorously proved that the optimal wire width is the width that results in a delay that is 33% larger than the time-of-flight (ToF). Using the optimal wire width decreases latency, energy dissipation, and repeater area considerably, compared to a sub-optimal wire width (e.g., 42% smaller latency, 30% smaller energy-per-bit, and 84% smaller repeater area compared with the W/sub opt//2 case) at the cost of a small decrease in data-flux density (e.g., 14% smaller compared with W/sub opt//2 case). A super-optimal wire width, however, causes a slight decrease in latency (e.g., 14% for 2W/sub opt/) at the cost of a large decrease in data-flux density (e.g., 35% for 2W/sub opt/).     

High-speed and low-power repeater for VLSI interconnects

This paper proposes a repeater for boosting the speed of interconnects with low power dissipation. We have designed and implemented at 45 and 32 nm technology nodes. Delay and power dissipation performances are analyzed for various voltage levels at these technology nodes using Spice simulations. A significant reduction in delay and power dissipation are observed compared to a conventional repeater. The results show that the proposed high-speed low-power repeater has a reduced delay for higher load capacitance. The proposed repeater is also compared with LPTG CMOS repeater, and the results shows that the proposed repeater has reduced delay. The proposed repeater can be suitable for high-speed global interconnects and has the capacity to drive large loads.     

Low-power CMOS/BiCMOS drivers and receivers for on-chipinterconnects

Novel low-voltage swing CMOS and BiCMOS driver/receiver circuits for low-power VLSI applications are proposed. Interconnect wire drivers with low output signal swing are employed. Special receivers provide single and double level conversion while minimizing the total driver/receiver transmission delay. These level converters have no DC power dissipation. At 3.3 V power supply voltage, the proposed circuits consume less power without delay penalty. The power saving is observed to be as high as 30%. At lower supplies further power and delay improvements are observed     

Optimal interconnection circuits for VLSI

The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi2, and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.     

Current-mode signaling in deep submicrometer global interconnects

This paper addresses propagation delay and power dissipation for current mode signaling in deep submicrometer global interconnects. Based on the effective lumped element resistance and capacitance approximation of distributed RC lines, simple yet accurate closed-form expressions of delay and power dissipation are presented. A new closed-form solution of delay under step input excitation is first developed, exhibiting an accuracy that is within 5% of SPICE simulations for a wide range of parameters. The usefulness of this solution is that resistive load termination for current mode signaling is accurately modeled. This model is then extended to a generalized delay formulation for ramp inputs with arbitrary rise time. Using these expressions, the optimum-line width that minimizes the total delay for current mode circuits is found. Additionally, a new power-dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on the results and derived formulations, a comparison between voltage and current mode repeater insertion for long global deep submicrometer interconnects is presented.     

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance. In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane. We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes. We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects.     

Overshoot-controlled RLC interconnections

How overshoot in the step response of a circuit involving an RLC line can be controlled using a combination of driver and line resistance that depends on the load capacitance is shown. The no-peak condition or its equivalent is used to relate line parameters to the driver and load impedances. This no-peak condition generalizes the impedance matching customarily used for lossless lines, i.e. it provides an alternative to the traditional choice R_D=√ L/C. The results allow improved circuit response without risk of overshoot, for example, by reduction of driver resistance below √L/C for cases where line resistance is unavoidable and/or where load capacitance is not negligible compared to line capacitance. The algebraic formulas derived are more effective than case-by-case numerical simulations for analyzing scaling and technology issues, whether on-chip, or at the packaging, board, or system levels     

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.     

Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis

Interconnect resistance and inductance shield part of the load capacitance, resulting in a faster voltage transition at the output of the driver. Ignoring this shielding effect may induce significant error when estimating short-circuit power. In order to capture this shielding effect, an effective capacitance of a distributed RLC load is presented for accurately estimating the short-circuit power. The proposed method has been verified with Cadence Spectre simulations. The average error of the short-circuit power obtained with the effective capacitance is less than 7% for the example circuits as compared with an RLC model. This effective capacitance can be used in look-up tables or in empirical -factor expressions to estimate short-circuit power.     

A novel energy-recovery sustaining driver for plasma display panel

A novel energy-recovery driver is proposed to drive a plasma display panel (PDP) in the sustaining operation. The proposed circuit uses the parallel resonance between the inductor and the intrinsic capacitance of PDP to mainly recover the energy lost by the capacitive displacement current of the PDP. The parasitic resonance caused by the parasitic inductance and the stray capacitance is prevented greatly. A 34-in AC PDP equipped with the proposed driving circuit, operated at 100 kHz, is investigated. In addition, some prior work is shown in this paper for comparison, in which the power consumption of driving the same 34-in panel is measured. The experimental results show that the proposed driver has a low-cost structure and better performance than the prior ones.     

High-voltage CdSe-Ge TFT driver circuits for passive AC-TFELdisplays

Since an electroluminescent display (ELD) is a capacitive display driven at high voltage, it is necessary to fabricate high-voltage, large-current drivers. It is shown that a 20-μm complementary CdSe-Ge thin-film transistor technology can be used to integrate the high-voltage section of the drive circuits on the substrate of an ELD. The realized column driver levels a 15 V CMOS signal up to a modulation voltage of 50 V. A novel tristate row driver circuit, which is based on the symmetric character of the thin-film transistor, handles row selecting voltages of about 200 V together with current pulses of approximately 100 mA. In this paper, the design, simulation, and measurement of these circuits are described. Technology problems due to high voltages were solved