一个有效的不完全Scan结构MOS电路的测试生成算法

本文介绍一个不完全Scan结构MOS电路的测试生成算法DALG—EX18。该算法充分考虑不完全Scan结构的特点,同时也考虑MOS电路中由三态器件引出的一些特性,在传统5值D-算法基础上,引入18值及其计算规则,加入新的处理步骤,并辅以可观值/可控值引导D-驱赶和一致性操作,从而提高故障覆盖率,加快测试生成速度。DALG—EX18算法已用C语言在VAX 11/750机上实现,一些电路的实验结果表明,该算法是有效的。     

一种低功耗系统芯片的可测试性设计方案

低功耗技术,如多电源多电压和电源关断等的应用,给现代超大规模系统芯片可测试性设计带来诸多问题。为此,采用工业界认可的电子设计自动化工具和常用的测试方法,构建实现可测试性设计的高效平台。基于该平台,提出一种包括扫描链设计、嵌入式存储器内建自测试和边界扫描设计的可测性设计实现方案。实验结果表明,该方案能高效、方便和准确地完成低功耗系统芯片的可测性设计,并成功地在自动测试仪上完成各种测试,组合逻辑和时序逻辑的扫描链测试覆盏率为98.2%。     

Testing methodology: implications for the circuit designer

The complexity achievable within a custom chip or on a PCB loaded with standard combinational or sequential elements, even without the use of VLSI components such as microprocessors, requires the use of automatic methods for the generation of test patterns if the task is to be completed within an acceptable time and at an acceptable cost. This paper reviews the current status of some aspects of the test process as applied to such circuits, and of the principles of structured design methodologies intended to reduce the difficulties of test pattern generation (TPG). The paper starts by reviewing the fault models on which most automatic TPG (ATPG) methods are based, and goes on to discuss some of the available ATPG methods themselves. The problems involved in TPG for sequential circuits are briefly discussed to show the motivation behind structured design for testability using the scan-in scan-out (SISO) principle. The main implications of SISO are described, as are some of the applications of these principles to the construction of testable PCBs.     

用于密码芯片的前馈异或安全扫描结构

扫描结构在给密码芯片增加可测性的同时也可能被不当使用为旁路攻击路径,使密码芯片的密钥信息泄露.为解决这个问题,提出一种前馈异或安全扫描结构.首先将异或安全扫描寄存器引入扫描结构中,该结构对测试图形进行输入?输出线性变换,实现对测试图形的硬件加密;然后分析了该结构的安全性并给出其测试图形生成算法.实验结果表明,文中提出的安全扫描结构能抗击基于扫描结构的旁路攻击和复位攻击,并保留了传统扫描结构的高测试覆盖率.     

一个实用化的测试产生系统COMPA—ATPG

本文介绍了一个在康发工作站实现的测试产生系统COMPA-ATPGS。该系统以FAN算法为基础,通过对电路结构分析来产生组合电路的测试码,进而帮助设计者产生整个电路的测试码。实验证明,该系统对组合电路的故障覆盖率可达90％以上。     

Testability implications of performance driven logic synthesis

Retiming improves performance but also increases test generation time and decreases fault coverage. Research conducted at Carnegie Mellon and McGill Universities attempts to explain the impact of retiming on the testability of sequential logic circuits. A novel test preservation theorem suggests a powerful way to decrease the test generation cost of retimed circuits. The authors also discuss a recently recognized circuit attribute that better explains the complexity of structural, sequential automatic test pattern generation     

Implementing macro test in silicon compiler design

A testability strategy for a complex VLSI device that is implemented in the Piramid digital-signal-processor silicon compiler is presented. The macro test method proposed supports built-in self-test, scan test, restricted partial scan, and test-control logic at various levels in the design hierarchy. The strategy uses techniques such as a macro test plan, transfer information, and intermediate vector storage. The overhead from adding testability is only 10% of the total area and test-program generation is done with 100% fault coverage in a very short time, since there is no need for global test-pattern generation. A set of tools that guide the testability implementation from design to the final test program is described     

组合电路测试生成研究及实验

本文以门级组合电路为对象，以主路径敏化算法为基础，研究提高测试生成效率的策略，实现结果表明，按本文提出的策略所研制的测试生成系统，不仅效率较好，且得蝗测试集也较小。     

基于内建自测试的测试向量生成方法

内建自测试(BIST)方法是目前可测性设计(DFT)中最具应用前景的一种方法。BIST能显著提高电路的可测性,而测试向量的生成是关系BIST性能好坏的重要方面。测试生成的目的在于,生成可能少的测试向量并用以获得足够高的故障覆盖率,同时使得用于测试的硬件电路面积开销尽可能低,测试时间尽可能短。本文对几种内建自测试中测试向量生成方法进行了简单的介绍和对比研究,分析各自的优缺点,并在此基础上探讨了BIST面临的主要问题和发展方向。     

基于多扫描链的内建自测试技术中的测试向量生成

针对基于多扫描链的内建自测试技术,提出了一种测试向量生存方法。该方法用一个线性反馈移位寄存器（LFSR）作为伪随机测试向量生成器,同时给所有扫描链输入测试向量,并通过构造具有最小相关度的多扫描链克服扫描链间的相关性对故障覆盖率的影响。此外该方法经过模拟确定难测故障集,并针对这外难测故障集利用ATPG生成最小确定性测试向量集。最后丙依据得到的最小测试向量集来设计位改变逻辑电路,利用们改变逻辑电路控制改变扫描链上特定的值来实现对难测故障的检测,从而实现被测电路和故障完全检测。     

组合电路测试生成的任意路径敏化法

本文阐述了基于布尔函数的组合电路测试生成方法,给出了测试生成的基本运算规则及测试生成的算法－任意路径敏化法,该算法适用于布尔函数的任何表示形式,与基于布尔函数的其它算法相比,该算法不用复杂的布尔运算。只须按给出的规则作简单的判断和计算就可以生成给定邦联伯测试码,因而计算工作要小得多,该算法用于大型组合电路的测试生成,可以增加扇出分支处的一敏化条件。减少信号冲突和回溯次数。大大加快了大规模组合电路以及印制电路板的测试生成速度。     

基于扫描D触发器的可逆电路测试综合方法

为了实现可逆逻辑电路的可测性设计,充分利用可逆逻辑电路中存在的输出引脚,提出一种可逆逻辑电路测试综合方法.通过定义可逆逻辑门的可观性值和可控性值的计算方法,对可逆逻辑电路的可测性进行建模;通过插入观察点,制定了可逆组合逻辑电路可测性实现方案;通过对现有的D触发器进行改造并构建全新的扫描D触发器,制定了可逆时序电路的可测性逻辑实现方案;最后分析了扫描D触发器的工作特点,规范了测试步骤,建立一种可逆逻辑电路的测试综合方法.实验结果表明,与现有方法相比,文中方法插入观察点代价平均增加不到1%,但电路的可观性平均能得到24%的改善.     

Designing CMOS Circuits for Switch-Level Testability

Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level faults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. An inverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-on faults.     

A test-pattern-generation algorithm for sequential circuits

A deterministic test-pattern-generation algorithm for synchronous sequential circuits is presented. The algorithm, called Essential, takes advantage of a procedure for learning global implications. It uses static and dynamic dominance relationships among signals, the concept of the potential propagation path, and intelligent heuristics to guide and accelerate the decision-making process for deterministic automatic test pattern generation (ATPG). Essential is based on the well-known method of reverse time processing, but it applies forward processing within time frames to avoid disadvantageous a priori determination of a path to be sensitized or of a primary output to which the fault effects must be propagated. It is designed to exploit fully the sophisticated techniques used for combinational circuits in the Socrates ATPG system. Experimental results for sequential ATPG obtained with Essential (implemented in C on a Sequent Symmetry computer) are reported     

LOCST: A Built-In Self-Test Technique

A built-in self-test technique utilizing on-chip pseudorandom-pattern generation, on-chip signature analysis, a ``boundary scan' feature, and an on-chip monitor test controller has been implemented on three VLSI chips by the IBM Federal Systems Division. This method (designated LSSD on-chip self-test, or LOCST) uses existing level-sensitive scan design strings to serially scan random test patterns to the chip's combinational logic and to collect test results. On-chip pseudorandom-pattern generation and signature analysis compression are provided via existing latches, which are configured into linear-feedback shift registers during the self-test operation. The LOCST technique is controlled through the on-chip monitor, IBM FSD's standard VLSI test interface/controller. Boundary scan latches are provided on all primary inputs and primary outputs to maximize self-test effectiveness and to facilitate chip I/O testing. Stuck-fault simulation using statistical fault analysis was used to evaluate test coverage effectiveness. Total test coverage values of 81.5, 85.3, and 88.6 percent were achieved for the three chips with less than 5000 random-pattern sequences. Outstanding test coverage (≫97%) was achieved for the interior logic of the chips. The advantages of this technique, namely very low hardware overhead cost (≪2%), design-independent implementation, and effective static testing, make LOCST an attractive and powerful technique.     

Scan BIST with biased scan test signals

The conventional test-per-scan built-in self-test （BIST） scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flipflops are shifted out while shifting in the next test vector like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the test signals of the scan chains. Different biased random values are assigned to the test signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly, and most circuits can obtain complete fault coverage or very close to complete fault coverage.     

An Effective Test Generation Algorithm for Combinational Circuits

In this paper,an analysis of backtrack behavior in PODEM(the test generation algorithmfor combinational circuits presented by P.Goel)is given.It is pointed out that there are stillmany unnecessary backtracks in PODEM on some occasions.A new test generation algorithmnamed IPODEM is therefore proposed in this paper.IPODEM is an improvement over PODEMwith emphasis on backtrack of decision tree.A new backtrack approach is developed in thisalgorithm.It is shown that only O(j)of backtrack consumption is needed in IPODEMcompared with O(2~j)in PODEM on certain occasions.Experiments pointed out that theseoccasions appear in not small proportion.Several other techniques are applied in IPODEM toaccelerate test generation process in other aspects.Experimental results demonstrated thatIPODEM is faster than PODEM for both hard-testing and easy-testing single stuck fault,andthat the former has higher test coverage than the latter.     

系统芯片IP核透明路径构建中的可测性分析

系统芯片的设计方法为测试技术带来新挑战。知识产权模块（IP核）测试访问机制成为测试复用的关键。构建IP核透明路径会对电路的故障覆盖率产生影响。基于门级透明路径的构建方法,通过分析插入电路的控制门和多路器的激活和传播条件,对路径构建对于IP核单固定型故障覆盖率的影响进行分析,给出可测性条件和故障覆盖率的计算公式,无需故障仿真即可估计构造透明路径后电路的故障覆盖率。通过故障仿真实验,证明该故障覆盖率的分析和计算方法是有效的。     

A Complete Critical Path Algorithm for Test Generation of Combinational Circuits

It is known that critical path test generation method is not a complete algorithm for combinational circuits with reconvergent-fanout.In order to made it a complete algorithm,we put forward a reconvergent-fanoutoriented technique,the principal critical path algorithm,propagating the critical value back to primary inputs along a single path,the principal critical path,and allowing multiple path sensitization if needed.Relationship among test patterns is also discussed to accelerate test generation.     

A generalized fault simulator for combinational logic circuits

A generalized approach to the design of fault simulator using a library of simulation primitives is presented in this paper. A comprehensive set of simulation primitives has been developed using C programming language on the IBM PC. This library of simulation primitives has been used in realizing a fault simulator for automatic test pattern generation in combinational logic circuits. The fault simulator employs a combination of random pattern generation, concurrent fault simulation and the FAN algorithm for generating the complete set of test vectors to cover all the faults in the fault dictionary of the circuit under test. The library of simulation primitives is general enough to facilitate the development of fault simulators using any other test algorithms such as DALG or PODEM.