Temperature dependence of hot carrier effects in short-channelSi-MOSFETs

Full-band Monte Carlo simulations were carried out to investigate hot carrier effects associated with impact ionization under the lateral electric field profiles typical of submicrometer Si-MOSFETs. It is shown that the temperature dependence of the band-gap energy of Si plays an important role for hot carrier suppression at low temperature in submicrometer devices. On the other hand, as the device size shrinks into the sub-0.1 regime, in which the high-field region is comparable in size to or smaller than the energy relaxation length, the number of electrons with energy below the supply drain voltage becomes less sensitive to temperature. As a result, the suppression of impact ionization at low temperature in sub-0.1 μm devices could be ascribed to both quasi-ballistic transport characteristics and temperature-dependent band-gap energy     

Transient behavior of the kink effect in partially-depleted SOIMOSFET's

The behavior of transients in the drain current of partially-depleted (PD) SOI MOSFET's down to L_eff=0.2 μm is examined as a function of drain bias, gate pulses of varying magnitude (V_GS), pulse duration, and pulse frequency. At fixed V_DS, the gate is pulsed to values ranging from 0.1 V above V_T to V_GS=V_DS. A slow transient is seen when the drain is biased at a V_DS where the current kink is observable. This slow transient can be on the order of microseconds depending on the relative magnitude of the impact ionization rate. For short times after the pulse edge or for very short pulses at low frequencies, it is shown that the subthreshold drain current value can be very different from the corresponding DC, and that the kink characteristic of PD MOSFET's disappears. However, the kink values can be approached when the pulse frequency and/or duration applied to the gate is increased, due to the latent charge maintained in the floating body at higher frequencies. No transient current effects were observed in fully-depleted SOI MOSFET's     

A physically-based MOS transistor avalanche breakdown model

A physically based breakdown model for MOSFET's is presented to rectify the unexplained experimental breakdown behaviors. The drain avalanche breakdown in the MOS transistor can be caused by either infinite multiplication (MI) or finite multiplication with positive feedback of the substrate current (MF) due to the impact ionization in the pinch-off region. The breakdown voltages of these two modes of breakdown have different dependencies on the biasing conditions and device parameters. For MI mode of breakdown, the breakdown voltage increases slowly with the gate voltage and can be approximated by the drain saturation voltage plus a constant offset. For MF mode of breakdown, the breakdown voltage decreases as the drain saturation current becomes larger. The calculated breakdown characteristics agree well with the measured ones for devices with effective channel length in the range of 0.44~10 μm     

Short-channel-effect-suppressed sub-0.1-μm grooved-gate MOSFET'swith W gate

Grooved-gate Si MOSFET's with tungsten gates are fabricated using conventional manufacturing technologies, and their short-channel-effect-free characteristics are verified down to a source and drain separation of around 0.1 μm. Phase shift lithography followed by a side-wall oxide film formation technique achieves a spacing of less than 0.2 μm between adjacent elevated polysilicons, subsequently resulting in a sub-0.1-μm source and drain separation in the substrate. Short-channel effects, such as threshold voltage roll-off and punchthrough, are found to be completely suppressed. From device simulations, the potential barrier formed at each grooved-gate corner is considered to be responsible for the suppression of the short-channel effects     

0.25 μm gate length CMOS devices for cryogenic operation

Under cryogenic operation, a low V_th realizes a high speed performance at a greatly reduced power-supply voltage, which is the most attractive feature of Cryo-CMOS. It is very important in sub-0.25 μm Cryo-CMOS devices to reconcile the miniaturization and the low V_th. Double implanted MOSFET's technology was employed to achieve the low V_th while maintaining the short channel effects immunity. We have investigated both the DC characteristics and the speed performance of 0.25 μm gate length CMOS devices for cryogenic operation. The measured transconductances in the saturation region were 600 mS/mm for 0.2 μm gate length n-MOSFET's and 310 mS/mm for 0.25 μm gate length p-MOSFET's at 80 K. The propagation delay time in the fastest CMOS ring oscillator was 22.8 ps at V_dd=1 V at 80 K. The high speed performance at extremely low power-supply voltages has been experimentally demonstrated. The speed analysis suggests that the sub-l0 ps switching of Cryo-CMOS devices will be realized by reducing the parasitic capacitances and through further miniaturization down to 0.1 μm gate length or below     

A new approach to modeling the substrate current of pre-stressedand post-stressed MOSFET's

In this paper, we propose a closed form expression of a new and accurate analytical substrate current model for both pre-stressed and post-stressed MOSFET's. It was derived based on the concept of effective electric field, which gives a more reasonable impact ionization rate in the lucky-electron model. This effective electric field, composed by two experimentally determined parameters, can be regarded as a result of nonlocal heating effects within devices. This model shows a significant improvement to the conventional local field model. One salient feature of the present model is that it allows us to characterize the time evolution of the substrate current of stressed MOSFET's for the first time. Experimental verification for a wide variety of MOSFET's with effective channel lengths down to 0.3 μm shows that the new model is very accurate and is feasible for any kind of MOS device with different drain structures. The present model can be applied to explore the hot carrier effect in designing submicrometer MOS devices with emphasis on the design optimization of a device drain engineering issue. In addition, the present model is well suited for device reliability analysis and circuit level simulations     

Impact ionization and distribution functions in sub-micron nMOSFETtechnologies

The physics of impact ionization generated substrate current in 0.1 μm nMOSFET's technologies is clarified by comparison of experiment and full-band Monte Carlo (MC) simulation for a wide range of biases. Quasiballistic transport is confirmed. It is shown for the first time that these devices allow extraction of ionization probabilities near threshold from substrate current measurements     

Very high gain millimeter-wave InAlAs/InGaAs/GaAs metamorphicHEMT's

We report the first demonstration of W-band metamorphic HEMTs/LNA MMICs using an AlGaAsSb lattice strain relief buffer layer on a GaAs substrate. 0.1×50 μm low-noise devices have shown typical extrinsic transconductance of 850 mS/mm with high maximum drain current of 700 mA/mm and gate-drain breakdown voltage of 4.5 V. Small-signal S-parameter measurements performed on the 0.1-μm devices exhibited an excellent f_T of 225 GHz and maximum stable gain (MSG) of 12.9 dB at 60 GHz and 10.4 dB at 110 GHz. The three-stage W-band LNA MMIC exhibits 4.2 dB noise figure with 18 dB gain at 82 GHz and 4.8 dB noise figure with 14 dB gain at 89 GHz, The gain and noise performance of the metamorphic HEMT technology is very close to that of the InP-based HEMT     

Metallized ultra-shallow-junction device technology for sub-0.1μm gate MOSFET's

This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 μm MOSFET's. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability     

Ga2O3(Gd2O3)/InGaAsenhancement-mode n-channel MOSFETs

We have demonstrated the first Ga₂O₃(Gd₂O₃) insulated gate n-channel enhancement-mode In_0.53Ga_0.47As MOSFET's on InP semi-insulating substrate. Ga₂O₃(Gd₂ O₃) was electron beam deposited from a high purity single crystal Ga₅Gd₃O₁₂ source. The source and drain regions of the device were selectively implanted with Si to produce low resistance ohmic contacts. A 0.75-μm gate length device exhibits an extrinsic transconductance of 190 mS/mm, which is an order of magnitude improvement over previously reported enhancement-mode InGaAs MISFETs. The current gain cutoff frequency, f_t, and the maximum frequency of oscillation, f_max, of 7 and 10 GHz were obtained, respectively, for a 0.75×100 μm² gate dimension device at a gate voltage of 3 V and drain voltage of 2 V     

Optimization of gate-to-drain separation in submicron gate-lengthmodulation doped FET's for maximum power gain performance

This paper analyzes the effects of the separation between the gate and the drain electrodes on the high-frequency performance limitations of heterostructure MODFET's. Based on the effective gate-length and carrier velocity saturation concepts first the key small-signal equivalent network model parameters of the MODFET are calculated. The concept of open-circuit voltage gain, defined as the transconductance to output conductance ratio (g_m/g_o), has been exploited to determine the output conductance with a knowledge of the static electric field and potential at the edge of the gate on the drain side. By treating the c_oμ_n product as a function of the gate voltage, the drain current-voltage and transconductance characteristics have been effectively modeled for practical devices. By combining the effects of the intrinsic and parasitic equivalent network parameters this paper has determined the dependence of the g_m/g_o ratio, the gate capacitance to the feedback capacitance ratio, the unity current gain frequency (f_r) and the maximum frequency of oscillations (f _max) on the gate-to-drain separation (L_gd). MODFET's based on InAlAs/InGaAs heterostructures lattice-matched to InP substrate with gate-length values of 0.25 μm, 0.15 μm and 0.1 μm are considered for analyses. The optimum values of L_gd calculated are 600 Å, 420 Å, and 340 Å for the corresponding maximum f_max-values of 250, 370, and 480 GHz, respectively     

Low-voltage hot-electron currents and degradation indeep-submicrometer MOSFETs

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L _eff=0.15 μm and T_ox=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO₂ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 μm) and oxide thicknesses     

Hot-carrier effects and reliable lifetime prediction in deepsubmicron N- and P-channel SOI MOSFETs

Hot-carrier effects are thoroughly investigated in deep submicron N- and P-channel SOI MOSFETs, for gate lengths ranging from 0.4 μm down to 0.1 μm. The hot-carrier-induced device degradations are analyzed using systematic stress experiments with three main types of hot-carrier injections-maximum gate current (V_g≈V_d ), maximum substrate current (V_g≈V_d/2) and parasitic bipolar transistor (PBT) action (V_g≈0). A two-stage hot-carrier degradation is clearly observed for all the biasing conditions, for both N- and P-channel devices and for all the gate lengths. A quasi-identical threshold value between the power time dependence and the logarithmic time dependence is also highlighted for all the stress drain biases for a given channel length. These new findings allow us to propose a reliable method for lifetime prediction using accurate time dependence of degradation in a wide gate length range     

0.18-μm fully-depleted silicon-on-insulator MOSFET's

High-performance 0.18-μm gate-length fully depleted silicon-on-insulator (FD-SOI) MOSFET's were fabricated using 4-nm gate oxide, 35-nm thick channel, and 80-nm or 150-nm buried oxide layer. An elevated source/drain structure was used to provide extra silicon during silicide formation, resulting in low source/drain series resistance. Nominal device drive currents of 560 μA/μm and 340 μA/μm were achieved for n-channel and p-channel devices, respectively, at a supply voltage of 1.8 V. Improved short-channel performance and reduced self-heating were observed for devices with thinner buried oxide layers     

Enhancement mode metamorphicAl0.67In0.33As/Ga0.66In0.34As HEMT on GaAs substrate with high breakdown voltage

This paper presents original and experimental results provided by E-mode Al_0.67In_0.33As/Ga_0.66In_0.34 As metamorphic HEMT. The devices exhibit good dc and rf performances. The 0.4 μm gate length devices have saturation current density of 355 mA/mm at +0.6 V gate-to-source voltage. The Schottky characteristic is a typical reverse gate-to-drain breakdown voltage of -16 V. It is the first time, to our knowledge, that gate current issued from impact ionization have been observed in these devices versus gate to drain extension. These results are the first reported for E-mode Al _0.67In_0.33As/Ga_0.66In_0.34As MM-HEMTs on GaAs substrate     

Short channel characteristics of Si MOSFET with extremely shallowsource and drain regions formed by inversion layers

The influence of extremely shallow source and drain junctions on the short channel effects of Si MOSFET's are experimentally investigated. These extremely shallow junctions are realized in MOSFET's with a triple-gate structure. Two subgates formed as side-wall spacers of a main gate induce inversion layers which work as the virtual source and drain. Significant improvement in threshold voltage roll-off and punchthrough characteristics are obtained in comparison with conventional MOSFET's whose junctions are formed by ion implantation: threshold voltage roll off is suppressed down to a physical gate length of 0.1 μm while punchthrough is suppressed down to 0.07 μm, the minimum pattern size delineated. It is also demonstrated experimentally that the carrier concentrations in the source and drain do not have any influence on the short channel effects     

Design optimization of high-performance low-temperature 0.18 μmMOSFETs with low-impurity-density channels at supply voltage below 1 V

A 0.18 μm nMOS structure with a vertically nonuniform low-impurity-density channel (LIDC) at 77 K has been studied at supply voltage below 1 volt. An abrupt Gaussian profile is used in the channel. The investigation is based on two-dimensional (2-D) energy transport simulation with appropriate models to account for quantum and low-temperature freeze-out effects. The study focuses on achieving high driving capability and low off-current at low supply voltage and on minimizing short-channel effects. Some guidelines are proposed for improving device performance and suppressing short-channel effects of the LIDC MOS devices. It is shown that at 77 K the optimized nonuniform LIDC 0.18 μm nMOS structure with an abrupt impurity channel profile at supply voltage as low as 0.9 V is able to provide a saturation drain current comparable to that of a room-temperature LIDC 0.1 μm nMOS device at 1.5 V. Furthermore, the 77 K LIDC 0.18 μm nMOS consumes considerably lower dynamic and standby power than the room-temperature 0.1 μm nMOS. These results suggest that the LIDC MOS structure with an abrupt channel profile is very suitable for low-power and high-speed ULSI applications at low temperature     

1.5 nm direct-tunneling gate oxide Si MOSFET's

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 μm, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA/μm and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 μm at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used     

Some CMOS device constraints at low temperatures

Two of the CMOS device constraints at low temperatures have been identified, namely, the transconductance and the breakdown voltage roll-off. In the short channel devices, the transconductance first increases then decreases with the decreasing temperature. This transconductance roll-off phenomenon is likely caused by the parasitic series resistance in the source and drain regions. The breakdown voltage of the MOSFET's due to the parasitic bipolar transistor action decreases with the decreasing temperature, which is caused by the increase of the impact ionization rate at low temperatures.     

Impact ionization and transport in the InAlAs/n+-InPHFET

We have carried out an experimental study exploring both impact ionization and electron transport in InAlAs/n⁺-InP HFET's. Our devices show no signature of impact ionization in the gate current, which remains below 17 μA/mm under typical bias conditions for L_g=0.8 μm devices (60 times lower than for InAlAs/InGaAs HEMT's). The lack of impact ionization results in a drain-source breakdown voltage (BV_DS) that increases as the device is turned on, displaying an off-state value of 10 V. Additionally, we find that the channel electron velocity approaches the InP saturation velocity of about 10⁷ cm/s (in devices with L_g<1.6 μm) rather than reaching the material's peak velocity. We attribute this to the impact of channel doping both on the steady-state peak velocity and on the conditions necessary for velocity overshoot to take place. Our findings suggest that the InP-channel HFET benefits from channel electrons which remain cold even at large V_GS and V_DS making the device well-suited to power applications demanding small I_G, low g_d, and high BV_DS