一种用于硬实时Java处理器的类转换器设计及实现

通过分析Class文件处理过程及其中影响实时性的操作，提出一种用于硬实时Java处理器的类转换器，它读取标准Class文件，处理并生成适合Java处理器直接执行的内存映像文件．由于装载、连接过程中大量操作（如符号引用的解析）都由类转换器提前处理完毕，使得Java处理器操作大为简化．同时，由于所有影响Java处理器实时性的操作也由类转换器提前处理，Java处理器最坏情况执行时间（Worst Case Execution Time）完全可预测．     

实时Java平台的类预处理器研究

设计并实现一种针对32 bit嵌入式实时Java平台的类预处理器,通过把标准class文件转换成适合Java处理器——Jpor32直接执行的内存映像,将在运行时动态装载和解析class的工作交由类预处理器提前完成,从而消除影响运行时实时性的一些操作,并降低Java处理器的设计复杂性。     

实时Java平台的类预处理器研究

设计并实现一种针对32 bit嵌入式实时Java平台的类预处理器,通过把标准class文件转换成适合Java处理器——Jpor32直接执行的内存映像,将在运行时动态装载和解析class的工作交由类预处理器提前完成,从而消除影响运行时实时性的一些操作,并降低Java处理器的设计复杂性。     

WCET可预测的Java指令集硬件实现

为能以硬件方式直接执行CISC结构的Java字节码,设计并实现适用于32位嵌入式实时Java平台的JPOR-32指令集。分析Java虚拟机规范中各Java字节码的功能和实现原理,设定执行每条指令时信号和数据在Java处理器数据通路上的变化,采用微指令方式执行复杂指令,简单指令直接执行,从而使JPOR-32的指令集具有RISC特性。实验结果验证了指令集的正确性及其最坏情况执行时间(WCET)的可预测性。     

一种用于硬Java实时平台的非堆内存模型

针对Java实时规范中的非堆内存抽象,讨论实现中的不确定因素以及运行时不可预测的时间特性,提出并实现了一种用于硬Java实时平台的非堆内存模型.模型基于硬Java实时平台预处理机制的支持,采用一种基于静态约束的安全访问检查算法,将运行时单亲规则及赋值规则检查等影响系统实时性的操作在运行前完成,保证了运行时的可预测.同时,针对当前关于静态分析方法研究中多不支持作用域多线程共享的现状,模型在不改变实时Java句法及编程模式的前提下,保留了对作用域多线程共享的支持.     

嵌入式Java处理器的方法调用机制

Java语言和Java处理器在实时嵌入式系统开发中的应用受到广泛关注。传统Java虚拟机的方法调用机制采用动态装载迟解析的执行方式,使得最坏情况执行时间(WCET)难以预测。针对该问题,提出一种提前解析-微程序执行的改进方法。将传统方法调用中的符号引用转化为直接调用,以微程序的方式运行在硬件处理器上,使执行限制在可预知的时钟周期内。实验结果证明,改进方法调用机制在执行时间上满足线性关系,具备良好的WCET可预测性。     

JVM实时内存管理模型的设计与实现

本文根据Java实时规(RTSJ)的要求,设计并实现了一个Java虚拟机实时内存管理模型.该模型包含了RTSJ内存管理机制实现的各个基本要点,如内存区域(Memory Area)的分配机制,领域堆栈(Scope Stack)的维护,使用Display树的内存引用检查等.实验结果表明该模型满足RTSJ内存管理实时性的要求.     

基于FPGA的Java处理器设计

针对Java技术在嵌入式领域的广泛应用,设计了一个适用于低端嵌入式设备的32位环境的Java处理器JPOR。该处理器由FPGA芯片实现,采用一种新的Java栈结构,指令系统简洁,可以直接执行Java字节码,能够对实时Java规范(RTSJ)提供有效支持。在Xilinx SPARTAN-3平台上通过了功能仿真,表明该Java处理器能够在低成本的FPGA芯片中实现。     

一种实时JAVA处理器的数据通路研究

FPGA具有灵活性高、设计周期短、成本低、风险小等优势,因此现已成为芯片设计的热点.该文设计了一种能在FP-GA芯片中实现的32位Java处理器JPOR(Java Processor Optimized For RTSJ)的数据通路,可以对实时Java规范提供有效支持.提供一种嵌入式实时系统的Java平台,该处理器具有指令系统简洁,直接执行JAVA字节码,提供对线程调度和管理的硬件支持等优点.     

面向WCET分析的实时多核体系结构研究

随着工艺技术的发展以及嵌入式实时应用范围的不断扩大和需求的不断提升,多核处理器必将凭其高性能和低功耗特性应用到嵌入式实时领域中。但是,多核处理器体系结构很难甚至无法满足实时系统的实时限制和对WCET的可预测性要求。从多核中的共享资源入手,分析多核中的片上共享资源（共享Cache、片上互连）和片外共享资源（片外存储）对WCET分析的影响,探讨了各种干扰下的WCET分析方法。介绍了两种多核WCET分析模型：多核静态WCET分析模型和多核混合WCET分析模型;同时,针对嵌入式实时应用提出了多核设计原则。     

Simulation of safety-critical,real-time Java: A case study of dynamic analysis of scoped memory consumption

For critical, real-time applications, scoped memory management in Real-Time Specification for Java (RTSJ) achieves a level of predictability not found in applications that use garbage collection techniques. However, a scoped memory model creates new challenges for developers. First, the reference rules between scopes constrain the design of the application’s memory model. Second, there is no abstract model for scoped memory that can be applied to different applications. Third, deciding on the appropriate number of scopes and which objects or threads should be allocated into those scopes are not straightforward tasks and require tools to assist. This paper presents a simulation of a railway control system executed on the Sun RTS2.2 virtual machine; it illustrates how simulation of critical safety real-time applications in Java can be used to investigate the implementation of possible scoped memory design models and their memory consumption in multi-threaded environments. The simulation demonstrates that a developer is able to compare and choose the most appropriate scoped memory design model that achieves the least memory footprint. Results showed that the memory design model with a higher number of scopes achieved the least memory footprint. However, the number of scopes per se does not always indicate a satisfactory memory footprint; choosing the right objects/threads to be allocated into scopes is an important factor to be considered.     

A comparison of instruction memories from the WCET perspective

Hard real-time systems demand high performance in combination with a timing predictable program execution. The performance of a system in the worst-case, represented by its worst case execution time (WCET), highly depends on the design of the memory subsystem. In this paper we focus on the instruction memory hierarchy and quantify the impact of different on-chip instruction memories on the worst-case timing of the system. A function-based dynamic instruction scratchpad (D-ISP), an instruction cache, and static instruction scratchpads using basic-block-based and function-based assignment algorithms are compared. Therefore, we provide WCET bounds for systems with different on-chip instruction memories and different off-chip memory timings.We show that for small memory sizes a static instruction scratchpad usually outperforms the other memories in terms of the WCET estimate. However, with increasing memory sizes the D-ISP is able to reach lower WCET bounds. An instruction cache can only provide lower WCET bounds than the other memories, if no suitable assignment for the static instruction scratchpads is found or if the D-ISP suffers from thrashing or frequently loads unused code.     

Worst-case execution-time analysis for embedded real-time systems

In this article we give an overview of the worst-case execution time (WCET) analysis research performed by the WCET group of the ASTEC Competence Centre at Uppsala University. Knowing the WCET of a program is necessary when designing and verifying real-time systems. The WCET depends both on the program flow, such as loop iterations and function calls, and on hardware factors, such as caches and pipelines. WCET estimates should be both safe (no underestimation allowed) and tight (as little overestimation as possible). We have defined a modular architecture for a WCET tool, used both to identify the components of the overall WCET analysis problem, and as a starting point for the development of a WCET tool prototype. Within this framework we have proposed solutions to several key problems in WCET analysis, including representation and analysis of the control flow of programs, modeling of the behavior and timing of pipelines and other low-level timing aspects, integration of control flow information and low-level timing to obtain a safe and tight WCET estimate, and validation of our tools and methods. We have focussed on the needs of embedded real-time systems in designing our tools and directing our research. Our long-term goal is to provide WCET analysis as a part of the standard tool chain for embedded development (together with compilers, debuggers, and simulators). This is facilitated by our cooperation with the embedded systems programming-tools vendor IAR Systems.     

嵌入式实时操作系统的分析评测方法

使用WCET(Worst-case execution time)分析工具Bound-T,分析典型实时操作系统(RTMES和uClinux)的关键模块代码,在系统运行在硬件上之前分析其机器码,给出整体系统的最坏执行时间.在系统的WCET达到要求之后,再通过实验使用benchmark,评测操作系统的典型实时性能指标,给出两个嵌入式实时操作系统的实时性能对比,并分析RTEMS(Real Time Executive for Multiprocessor Systems)的优势所在.     

Static worst-case execution time analysis of the μ C/OS-II real-time kernel

Worst-case execution time (WCET) analysis is one of the major tasks in timing validation of hard real-time systems. In complex systems with real-time operating systems (RTOS), the timing properties of the system are decided by both the applications and RTOS. Traditionally, WCET analysis mainly deals with application programs, while it is crucial to know whether RTOS also behaves in a timely predictable manner. In this paper, static analysis techniques are used to predict the WCET of the system calls and the Disable Interrupt regions of the μC/OS-II real-time kernel, which presents a quantitative evaluation of the real-time performance of μC/OS-II. The precision of applying existing WCET analysis techniques on RTOS is evaluated, and the practical difficulties in using static methods in timing analysis of RTOS are also discussed.     

基于JMF的多人视频聊天软件的设计与实现

多人视频聊天软件是网络环境与网络技术发展的产物,具有很高的应用需求和广阔的应用前景.JMF(Java媒体框架)是Java语言的扩展,专门用来处理时基媒体数据和实时媒体流.通过介绍JMF应用编程接口的结构特点,详细阐述了当前Internet网络多人视频聊天软件的工作原理、关键技术,及其基于JMF的具体实现.该软件具有跨平台可移植性.     

Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems

In real-time systems, time is usually so critical that other parameters such as energy consumption are often not even considered. However, optimizing the worst energy consumption case can be a key factor in systems with severe power-supply limitations. In this paper we study several memory architectures using combined time and energy optimization models for real-time multitasking systems. Each task is modeled using Lock-MS, a method to optimize the WCET of a task, with an added set of constraints to model in the same way the WCEC (worst case energy consumption). Our tested hardware components focus on instruction fetching, including a lockable cache, a line buffer and a sequential prefetch buffer. We test a variety of instruction fetch alternatives optimizing time and energy consumption. Our results show that the accuracy of the estimation of the number of context switches in the worst case may affect very much the resulting WCEC (up to 8 times in our experiments) and that optimizing the WCEC may provide similar execution times than optimizing the WCET, with up to 5 times less energy consumption Additionally optimization functions combining WCET and WCEC with different weights show very interesting WCET-WCEC trade-offs. This confirms that methodologies testing such optimizations at design time could be very helpful to provide a precise system set-up.