The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

Sub-100 nm CMOS circuit performance with high-K gate dielectrics

In this paper we look at the effect of fringing fields on the circuit performance by use of high permittivity (K) gate dielectrics in 70 nm CMOS technologies, from Monte-Carlo and mixed-mode simulations. Our results clearly show a decrease in the external fringing capacitance and an increase in the internal fringing capacitance, when the conventional SiO₂ is replaced by high-K gate dielectrics. It also indicates an optimum K value for a given technology generation in terms of circuit and device short-channel performance.     

Demonstration of Low Vt Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a Dy2O3 Cap Layer

This letter reports a novel approach to achieve low threshold voltage (Vt) Ni-fully-silicide (FUSI) nMOSFETs with SiON dielectrics. By using a dysprosium-oxide (Dy₂O₃) cap layer with a thickness of 5 Aring on top of the SiON host dielectrics, V_t,lin of 0.18 V for long-channel devices (L_g = 1 mum) using NiSi-FUSI electrode is obtained, satisfying the high-performance device requirements. The Vt modulation due to the Dy₂O₃ cap layer is also maintained in the short-channel devices (with an L_g,min of 90 nm as demonstrated in this letter). In particular, approximately 150times reduction in gate leakage current is seen while preserving the dielectric capacitance equivalent thickness after adding the Dy₂O₃ cap layer on SiON dielectrics, likely due to a high-k layer (DySiON) formation during device source/drain activation process. We also report that the Dy₂O₃ layer does not vitally degrade the device reliability, such as positive-bias temperature instability and time-dependant dielectrics breakdown.     

An improved two-frequency method of capacitance measurement forSrTiO3 as high-k gate dielectric

An improved two-frequency method of capacitance measurement for the high-k gate dielectrics is proposed. The equivalent circuit model of the MOS capacitor including the four parameters of intrinsic capacitance, loss tangent, parasitic series inductance, and series resistance is developed. These parameters can be extracted by independently measuring the capacitor at two different frequencies. This technique is demonstrated for high-k SrTiO₃ gate dielectrics and the results show that the calibrated capacitances are invariant over a wide range of frequency. In addition, the extracted loss tangent, inductance and resistance are independent on gate voltage and frequency. The effect of series resistance on the frequency dispersion of the capacitance can be also explained by this model. These results indicate that this modified technique can be incorporated in the routine capacitance-voltage (C-V) measurement procedure providing the physically meaningful data for the high-k gate dielectrics     

先进的Hf基高k栅介质研究进展

随着CMOS器件特征尺寸的不断缩小,SiO2作为栅介质材料已不能满足集成电路技术高速发展的需求,利用高k栅介质取代SiO2栅介质成为微电子技术发展的必然.但是,被认为最有希望替代SiO2的HfO2由于结晶温度低等缺点,很难集成于现有的CMOS工艺中,新型Hf基高k栅介质的研究成为当务之急.据报道,在HfO2中引入N、Si、Al和Ta可大大改善其热力学稳定性,由此形成的高k栅介质具有优良的电学特性,基本上满足器件的要求.本文综述了这类先进的Hf基高k栅介质材料的最新研究进展.     

Analysis of the Effects of Fringing Electric Field on FinFET Device Performance and Structural Optimization Using 3-D Simulation

In this paper, the potential impact of parasitic capacitance resulting from fringing field on FinFET device performance is studied in detail using a 3-D simulator implemented with quantum-mechanical models. It was found that fringing field from gate to source contributes significantly to FinFET performance and speed. The strength of fringing field is closely related to device features such as gate-dielectric thickness, the spacer width, fin width and pitch, as well as the gate height. For undoped fin with underlapping (nonoverlapping source/drain) gate, a thinner spacer with higher kappa value enhances the gate control of short-channel effects (SCEs) and reduces the source-to-drain leakage current. Our results also suggest that reducing the high- gate-dielectric thickness is no longer an effective approach to improve performance in small FinFET devices due to the strong fringing effect. However, the introduction of thin metal gate in a multifin device was found beneficial to device speed without compromising on current drive and SCE.     

Frequency-dependent capacitance reduction in high-k AlTiOx and Al2O3 gate dielectrics from IF to RFfrequency range

We have characterized the capacitance and loss tangent for high-k Al₂O₃ and AlTiO_x gate dielectrics from IF (100 KHz) to RF (20 GHz) frequency range. Nearly the same rate of capacitance reduction as SiO₂ was demonstrated individually by the proposed Al₂O₃ and AlTiO_x gate dielectrics as frequency was increased. Moreover, both dielectrics preserve the higher k better than SiO₂ from 100 KHz to 20 GHz. These results suggest that both Al₂O₃ and AlTiO_x are suitable for next generation MOSFET application into RF frequency regime     

Enhancement-Mode Buried-Channel $hbox{In}_{0.7} hbox{Ga}_{0.3}hbox{As/In}_{0.52}hbox{Al}_{0.48}hbox{As}$ MOSFETs With High- $kappa$ Gate Dielectrics

The operation of long- and short-channel enhancement-mode In_0.7Ga_0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have V_t= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm²/Vldrs. For a gate length of 260 nm, the short-channel devices have V_t=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.     

On the Suitability of a High- $k$ Gate Dielectric in Nanoscale FinFET CMOS Technology

The impact of a high-k gate dielectric on the device and circuit performances of nanoscale double-gate (DG) FinFET CMOS technology is examined via physics-based device/circuit simulations. DG FinFETs are designed with high k at the high- performance 45-nm node of the 2005 Semiconductor Industry Association International Technology Roadmap for Semiconductors (ITRS; L_g = 18 nm), and are compared with a pragmatic design in which the traditional SiON (or SiO₂) gate dielectric is retained and kept relatively thick to avoid excessive gate tunneling current. Whereas it is presumed that a high-k dielectric, if and when adequately integrated, will significantly enhance CMOS scalability and performance, we show that there are heretofore unacknowledged compromising effects associated with it that undermine this enhancement. In fact, our results show that for DG FinFET CMOS, a high-k gate dielectric actually undermines speed performance while giving little improvement in scalability relative to the pragmatic design, whereas the latter can be scaled, with good performance, to the end of the ITRS.     

Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-$kappa$ Gate Dielectrics

In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO₂ and HfSiO_x, high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher I_on/I_off current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V_th), relative to conventional deposited-SiO₂, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiO_x, as the gate dielectric had ca. 1.73 times the mobility (mu_FE) relative to that of the deposited-SiO₂ TFTs; in contrast, the HfO₂ TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO₂ TFTs. The immunity of the HfSiO_x, TFTs was better than that of the HfO₂ TFTs-in terms of their V_th shift, SS degradation, mu_FE degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiO_x, rather than HfO₂, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.     

金属栅/高k基FinFET研究进展

对比传统的平面型晶体管,总结了三维立体结构FinFET器件的结构特性。结合MOS器件栅介质材料研究进展,分别从纯硅基、多晶硅/高k基以及金属栅/高k基三个阶段综述了Fin-FET器件的发展历程,分析了各阶段FinFET器件的材料特性及其在等比缩小时所面临的关键问题,并着重从延迟时间、可靠性和功耗三方面分析了金属栅/高k基FinFET应用于22 nm器件的性能优势。基于短沟道效应以及界面态对器件性能的影响,探讨了FinFET器件尺寸等比缩小可能产生的负面效应及其解决办法。分析了FinFET器件下一步可能的发展方向,主要为高迁移率沟道材料、立体型栅结构以及基于新原理的电子器件。     

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits

Intrinsic carbon-nanotube field-effect transistors (CNFETs) have been shown to have superior performance over silicon transistors. In this letter, we provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device (gate) width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.     

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I_dsat of 820 μA/μm at V_ds=V_gs=1.2 V and T _ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm     

Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials

Fin Field Effect Transistors (FinFETs) are used for Complementary Metal Oxide Semiconductor applications beyond the 45?nm node of the Semiconductor Industry Association (SIA) roadmap because of their excellent scalability and better immunity to short channel effects. This article examines the impact of high-k dielectrics on FinFETs. The FinFET device performance is analysed for On Current, Off Current, I _on/I _off ratio, drain induced barrier lowering, electrostatic potential along the channel, electric field along the channel, transconductance, output resistance, intrinsic gain, gate capacitance and transconductance generation factor, by replacing the conventional silicon dioxide gate dielectric material, with various high dielectric constant materials. Nanosize ZrO₂ (zirconium-di-oxide) is found out to be the best alternative for SiO₂ (silicon-di-oxide). It is also observed that the integration of high-k dielectrics in the devices significantly reduces the short channel effects and leakage current. The suitability of nanoscale FinFETs is observed with the help of an inverter circuit and their gain values are calculated for circuit applications.     

Comparison of the scaling characteristics of nanoscale SOI N-channel multiple-gate MOSFETs

As MOSFET scaling pushes channel lengths below 65 nm, device designs utilizing fully depleted silicon-on-insulator (SOI) technology and employing two or more gates are becoming increasingly attractive as a means to counteract short channel effects. The presence of multiple gates enhances the total control that the gate exercises on the channel region and the SOI technology allows for a significant reduction in the junction capacitance. In combination, these two factors result in devices that exhibit superior characteristics to the conventional planar MOSFET. This paper compares the variation in the switching performance of the three leading multi-gate MOSFET designs, namely the FinFET, TriGate, and Omega-gate. A 3-dimensional, commercial numerical device simulator is employed to investigate the device characteristics using a common set of material parameters, device physics models, and performance metrics. Examined initially are the short-channel effects including the subthreshold slope (S) and the drain-induced barrier lowering as the gate length is scaled down to 20 nm. Subsequently investigated and compared are the effects of scaling of the fin’s body width and height, the oxide thickness, and channel doping. The investigation reveals that the Omega-gate MOSFET shows the best scaling characteristics at a particular device dimension with the TriGate device showing the least variation in characteristics as device dimensions vary.     

Effective Work Function Engineering of TaxCy Metal Gate on Hf-Based Dielectrics

This letter reports the engineering of effective work function (EWF) for tantalum carbide (TaC) metal gate on high-k gate dielectrics. The dependence of EWF on Si concentration in HfSiO as well as nitridation techniques is revealed. The EWF was extracted by both terraced oxide and terraced high-k techniques with the bulk and interface charges taken into account. The incorporation of Si in Hf-based dielectrics results in an increase of EWF, while the presence of N tends to decrease the EWF. Plasma nitridation is found to be more effective in lowering the EWF than a thermal nitridation. The phenomena can be explained by the modification of TaC/high-k interface dipole moment, which arises from the electronegativity difference for various interface bonds. Based on the above findings, we proposed a novel approach to reduce the EWF of TaC on HfSiON by using a thin HfO₂ cap layer after optimizing the nitridation. The MOSFET results show that this technique is able to achieve a lower V_t without degrading the device performance     

Empirically Verified Thermodynamic Model of Gate Capacitance and Threshold Voltage of Nanoelectronic MOS Devices With Applications to HfO2 and ZrO2 Gate Insulators

A thermodynamic variational model derived by minimizing the Helmholtz free energy of the MOS device is presented. The model incorporates an anisotropic permittivity tensor and accommodates a correction for quantum-mechanical charge confinement at the dielectric/substrate interface. The energy associated with the fringe field that is adjacent to the oxide is of critical importance in the behavior of small devices. This feature is explicitly included in our model. The model is verified using empirical and technology-computer-aided-design-generated capacitance-voltage data obtained on MOS devices with ZrO₂, HfO₂, and SiO₂ gate insulators. The model includes considerations for an interfacial low-k interface layer between the silicon substrate and the high-k dielectric. This consideration enables the estimation of the equivalent oxide thickness. The significance of sidewall capacitance effects is apparent in our modeling of the threshold voltage (V_th) for MOS capacitors with effective channel length at 30 nm and below. In these devices, a variation in high-k permittivity produces large differences in V_th. This effect is also observed in the variance of V_th, due to dopant fluctuation under the gate.     

Influences of structure around gate-edge on high electric field strength in MISFETs with high-k gate dielectrics

In this paper, dependences of electric field strength around gate-edge in gate dielectrics of MISFETs with high-k gate dielectrics on design parameters are studied. It is newly found that locations of sidewall/gate dielectric interfaces relative to gate electrode edges are critical to electric field strength of high-k MISFETs. Electric field can be as high as 4 MV/cm, which could have large influences on the yield of large scale integrated circuits (LSIs) with high-k gate dielectrics. An explanation of this phenomenon is given by considering discontinuity in electric field at interfaces between two materials with different dielectric constants. It is clarified that an electrical potential of side and top surfaces of gate dielectrics is strongly affected by the discontinuity of electric field strength at interfaces. As a result, electric field strength around gate electrode edges critically depends on locations of sidewall/gate dielectrics interfaces relative to gate electrode edges. Based on the physical considerations, a structure, in which gate sidewalls are also made of high-k materials, is studied from the viewpoint of electric field strength around gate electrode edges. It is shown that this structure effectively suppresses electric field strength around gate edges.     

Design of CMOS Transistors to Maximize Circuit FOM Using a Coupled Process and Mixed-Mode Simulation Methodology

Calibrated process and device CMOS modules were integrated into a mixed-mode simulation setup to study the circuit figure of merit (FOM). Switching delay from typical two-input NAND, two-input NOR, and inverter circuits built and simulated in the device simulator Dessis, including both intra and intercell capacitances and resistances show strong dependence on the drain-induced barrier lowering and associated short-channel electrostatics. The analysis presented in this letter identifies, for a given set of leakage and process constraints, an optimal gate length$(L_g)$that maximizes circuit FOM. The analysis also highlights, for the first time, that the optimal$L_g$for maximizing circuit FOM is much longer than that required for maximizing the device performance. The optimal$L_g$for maximum circuit FOM is determined by a complex tradeoff between reduced capacitance, increased short-channel effect, and reduced mobility.