共查询到20条相似文献,搜索用时 93 毫秒
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封装热应力是导致MEMS器件失效的主要原因之一,本文设计了一种MEMS高g加速度传感器,并仿真研究了传感器在封装过程中的热应力及影响其大小的因素。根据封装工艺,建立设计的高g加速度传感器封装的有限元模型,利用AN-SYS软件仿真传感器在不同的贴片工艺中受到的热应力及影响热应力的因素。结果显示,在封装中,与直接贴片到管壳底部相比,MEMS高g加速度传感器芯片底面键合高硼硅玻璃后再贴片到管壳底部时,封装热应力可从135MPa降低到33MPa;在贴片工艺中,基板的热膨胀系数和贴片胶的弹性模量、热膨胀系数及厚度是影响封装热应力的主要因素;在健合工艺中,基板和键合温度主要影响到热应力的大小。 相似文献
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CSP技术是目前微电子封装领域中的研究热点之一,是未来高密度电子封装技术的主流和发展方向,有着非常广阔的应用前景。通过对系统关键部件的工艺设计研究,主要包括工艺设计原理和封装结构、制造工艺、力学和电学性能分析和试验、关键部件的焊接可靠性等方面,建立了关键部件工艺实现的思路、方法和数学模型,进而建立起系统的有限元模型。在系统有限元模型的基础上,利用有限元仿真软件对系统进行了仿真分析。工艺设计就是解决和预防这些问题出现的过程。完成的实装样品经严格测试和用户使用,性能稳定、可靠,证明工艺设计合理,工艺参数把握准确。 相似文献
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3D封装是一种小尺寸、轻重量、低功耗、低成本的先进封装工艺,结合其在实际应用中通常出现的可靠性问题,从非破坏性与破坏性两方面对可用于3D封装故障隔离与故障分析的方法展开介绍.通过精确定位来暴露失效位置,使用开放性高阻故障隔离、短路故障隔离、无损及高分辨率成像技术等方法,来实现非破坏性故障隔离与分析;通过破坏性的制样和物... 相似文献
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随着计算机技术和IT技术的发展,对电路元器件的封装提出了更好的要求。期中SMT技术得到了广泛的应用,SMT封装对在高密度、高引出端数和高性能方面要求的提高,发展了陶瓷焊球阵列(CBGA)技术,本文重点介绍了陶瓷焊球(CBGA)的工艺以及封装技巧和返修方法。 相似文献
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微电子封装中,芯片银导电胶粘接工艺的质量会直接影响集成电路的可靠性。针对银导电胶粘接工艺的可靠性问题,本文提出了一种基于PFMEA的芯片粘接工艺风险识别方法,通过开展潜在失效模式分析,找到了芯片粘接工艺中的高风险环节,并制定了相应控制方法,有效提升了芯片粘接工艺质量,为微电子封装工艺开展PFMEA分析提供参考依据。 相似文献
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越来越多的高密度、多功能和小型化需求给封装和基板都带来了新的挑战,很多新的封装技术也应运而生,包括引起众多关注的埋入式封装技术.在本文中,我们首先对埋入封装技术的优势、挑战以及发展现状进行了介绍.然后通过将功能性有源器件埋入到有机基板中的尝试说明了设计、制造和测试埋入式封装这一新兴技术的可行性.制定一个切实可行的解决方案,有利于降低制造成本和市场的产品开发周期.我们提出的这种埋入式板级封装技术,与传统的封装和基板工艺都兼容.此外,本文设计了将功能性的MOSFET有源芯片埋入到有机基板中的板级封装模块结构,对该模块进行了热机械仿真分析,找到了最大应力点,优化了工艺设计.最后,结合传统的基板工艺,制备了埋入式板级封装样品,并完成了埋入式板级封装模块的电阻通断测试和功能测试,验证了该工艺设计的可行性. 相似文献
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Today's increased power and packaging densities demand designers' attention to the effects of heat on ICs. The authors review thermal and electrothermal simulation and measurement methods, thermal package characterization, and the concept and techniques of design for thermal testability 相似文献
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Addressing fundamental challenges to designing high-performance ICs in nanometer-scale technologies, the authors advocate a flexible approach to limiting both dynamic and static power. They recommend global-signaling strategies to curb communication power requirements and thermal management techniques to ease the burden on packaging 相似文献
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《Expert systems with applications》2007,32(1):151-156
Packaging is classified as one of back-end processes in the integrated circuits (ICs) manufacturing, highly capital-intensive and involves complex processes. Unlike the front-end process that fabricates wafers, the back-end process is rarely uniform. Because of the complexity of the process and increasing variety of products, the packaging foundry occasionally encounters complaints that can be categorized into classes depending on the loss. We apply rough set theory to discover important attributes leading to complaints and induce decision rules based on the data of a Taiwanese IC packaging foundry that ranks one of the largest in the world. The data contain 454 records and each record includes 11 condition attributes as well as one decision attribute characterizing the class. We first obtain important set of attributes that ensures high quality of classification, and then we generate rules for each class of complaints. The strongest rules obtained relate to two attributes, number of pins and wire bonding, which are important technological factors in the packaging process. These rules are presented to the foundry’s staffs who believe that the rules are potentially applicable for the future to prevent the complaints. 相似文献
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3D System-on-Chip technologies for More than Moore systems 总被引:1,自引:0,他引:1
Peter Ramm Armin Klumpp Josef Weber Maaike M. V. Taklo 《Microsystem Technologies》2010,16(7):1051-1055
3D integration is a key solution to the predicted performance problems of future ICs as well as it offers extreme miniaturization
and cost-effective fabrication of More than Moore products. Through silicon via (TSV) technologies enable high interconnect
performance compared to 3D packaging. At present TSVs are associated with a relatively high fabrication cost, but research
world wide strive to bring the cost down to an acceptable level. An example of a 3D System-on-Chip (3D-SOC) technology is
to introduce a post backend-of-line TSV process as an optimized technology for heterogeneous system integration. The introduced
ICV-SLID process, that combines both TSVs and bonding, enables 3D integration of fabricated devices. Reliability issues related
to thermo-mechanical stress caused by the TSV formation and the bonding are considered. 3D-SOC technology choices made to
realize a heterogeneous ultra-small IC stack for a wireless tire pressure monitoring system (TPMS) as an automotive application
are described. 相似文献
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We carried out Brownian dynamics simulations to investigate the mechanism of chain length recognition observed in the formation of inclusion complexes (ICs) between cyclodextrins (CDs) and polymer chains. In our simulations, we used rings and chains as models to represent CDs and polymer chains, respectively. We used two types of chains with different lengths to determine which chain was preferred by the rings to form ICs. At low concentration of rings, we observed that almost all the rings formed ICs with the long chains. Chain length recognition could be reproduced in our simulation, and it occurred because of the difference in the inclusion time between the long chains and the short chains in the ICs. On the other hand, at high concentration of rings, the number of rings forming ICs with the long chains increased, and pseudo-polyrotaxanes (PPRXs) were formed. ICs were also formed with the short chains, because the inclusion time for each ring contained in the PPRXs reduced with an increase in the number of rings therein, and then, the dissociated rings formed ICs with the short chains. As a result, chain length recognition was not observed. From these results, we conclude that the difference in the inclusion time between the rings and the chains controls chain length recognition. 相似文献
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In this paper, we present a detailed and systematic overview of communication security aspects of Multi-Processor Systems-on-Chip (MPSoC) and the emerging potential threats on the novel Cloud-of-Chips (CoC) paradigm. The CoC concept refers to highly scalable and composable systems, assembled not only at system design-time using RTL, like traditional SoC, but also at integrated circuit (IC) packaging time thanks to 3D-IC integration technology. Practical implementation of CoC systems needs to solve the problem of scalable, configurable and secure communication not only between different functional blocks in a single ICs, but also between different ICs in a single package, and between different packages on the same or different PCBs and even between different systems. To boost such extremely flexible communication infrastructure CoC system relies on Software-Defined Network-on-Chip (SDNoC) paradigm that combines design-time configurability of on-chip systems (NoC) and highly configurable communication of macroscopic systems (SDN). This study first explores security threats and existing solutions for traditional MPSoC platforms. Afterwards, we propose SDNoC as an alternative to MPSoC communication security, and we further extend our discussion to CoC systems to identify additional security concerns. Moreover, we present a comparison of SDNoC based approach over existing approaches and discuss its potential advantages. 相似文献
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Three-dimensional integrated circuits (3D ICs) are suitable alternatives to traditional two-dimensional (2D) ICs by leveraging its advantage of better performance and packaging; therefore, they have been highly considered by researchers. On the other hand, emerging network-on-chip (NoC) based many-core chips provides great potential for running multiple applications simultaneously. However, using this approach leads to the increase of the interference between applications, resulting in lowering the performance of each application. Hence, mapping tasks belonging to various applications onto the nodes of an architecture is a very important issue. In this study, based on partitioning concept, a novel methodology for mapping of multiple applications at run-time onto an irregular wireless 3D NoC-based multiprocessor system-on-chip (MPSoC) platform in which more than one task can be supported by each processing element (PE) was presented. In the second algorithm (enhanced irregular-partitioning best neighbor), according to the number of applications running simultaneously, the partitioning of network will be dynamically changed to minimize the communication overhead and congestion on the NoC that leads to more efficient task mapping. The simulation results reveal that the second proposed algorithm (enhanced IPBN) in comparison with NPBN (non-partitioning best neighbor) algorithm and our first proposed algorithm (basic IPBN) enhances the performance by decreasing the total execution time, average hop count, average channel load and energy consumption. 相似文献
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Alex Ching‐Wei Lin Ting‐Kuo Chang Chueh‐Kuei Jan Meng‐Hsun Hsieh Chung‐Yang Tsai James Shih‐Chang Chang Alan Yaw‐Ming Tsai 《Journal of the Society for Information Display》2006,14(4):353-362
Abstract— A 3.5‐in. QVGA‐formatted driving‐circuit fully integrated LCD has been developed using low‐temperature poly‐Si (LTPS) technology. This display module, in which no external ICs are required, integrates all the driving circuits for a six‐bit RGB digital interface with an LTPS device called a “FASt LDD TFT” and achieves a high‐quality image, narrow frame width, and low power consumption. The LTPS process, device, and circuit technologies developed for system‐on‐glass LCD discussed. The development phase of LTPS circuit integration for system‐on‐glass LCDs is also reviewed. 相似文献