MEMS高g加速度传感器封装热应力的研究

封装热应力是导致MEMS器件失效的主要原因之一,本文设计了一种MEMS高g加速度传感器,并仿真研究了传感器在封装过程中的热应力及影响其大小的因素。根据封装工艺,建立设计的高g加速度传感器封装的有限元模型,利用AN-SYS软件仿真传感器在不同的贴片工艺中受到的热应力及影响热应力的因素。结果显示,在封装中,与直接贴片到管壳底部相比,MEMS高g加速度传感器芯片底面键合高硼硅玻璃后再贴片到管壳底部时,封装热应力可从135MPa降低到33MPa;在贴片工艺中,基板的热膨胀系数和贴片胶的弹性模量、热膨胀系数及厚度是影响封装热应力的主要因素;在健合工艺中,基板和键合温度主要影响到热应力的大小。     

一种基于CSP技术的模块系统设计

CSP技术是目前微电子封装领域中的研究热点之一，是未来高密度电子封装技术的主流和发展方向，有着非常广阔的应用前景。通过对系统关键部件的工艺设计研究，主要包括工艺设计原理和封装结构、制造工艺、力学和电学性能分析和试验、关键部件的焊接可靠性等方面，建立了关键部件工艺实现的思路、方法和数学模型，进而建立起系统的有限元模型。在系统有限元模型的基础上，利用有限元仿真软件对系统进行了仿真分析。工艺设计就是解决和预防这些问题出现的过程。完成的实装样品经严格测试和用户使用，性能稳定、可靠，证明工艺设计合理，工艺参数把握准确。     

灌封技术对MEMS高g加速度传感器性能影响研究

针对恶劣环境下高频信号的干扰与由封装引起的结构失效,设计了一种MEMS高g加速度传感器,通过灌封实现机械滤波,保证封装的可靠性。根据传感器封装工艺,利用ANSYS软件建立有限元模型,仿真分析了灌封技术对传感器结构和性能。结果表明：灌封技术可提高传感器的高过载能力和输出灵敏度,灌封弹性模量相对较大、密度相对较小的灌封胶可提高传感器的高过载能力和灵敏度。     

MEMS耐高温压力传感器封装工艺研究

为解决特种压力传感器结构的封装难题,提出了三种能够适用于200°C高温条件下的先进封装技术.通过有限元模拟,确定了采用低温玻璃键合技术对多种压力传感器进行封装,分析得出了适合的中间键合层厚度.选定了高强度低膨胀基底合金材料,制定了低温玻璃键合的工艺流程,采用先进的丝网印刷工艺确保中间键合层厚度.实验表明经过该工艺封装的压力传感器在高温下具有可靠的性能,能满足现代工业测量需求.     

黑瓷封装工艺研究

伴随着微电子封装行业的迅猛发展,一批新兴的封装方式涌现出来,但黑瓷封装依靠不可替代的特性依然在军、民品封装中具有广阔市场,因此对其封装工艺进行研究有着重要的意义。根据对黑瓷封装特性的研究,设计出了满足黑瓷封装特性的工艺温度曲线,通过封盖试验,找出各相关因素（氮气,温度,加热时间）对黑瓷封装效果的影响。     

高量程MEMS加速度计封装工艺研究

对一种先进的双悬臂梁高量程MEMS加速度计的单芯片封装工艺进行了失效机理分析。手工粘贴芯片盖板可靠性不高,加速度计失效是由于胶粘剂(粘贴胶或灌封胶 )从芯片盖板和芯片的间隙流淌进入悬臂梁的过载保护间隙,阻碍了悬臂梁的摆动。高量程加速度计采用单芯片封装方法时,存在芯片正面和背面保护的可靠性问题,更好的封装方法是采用圆片级封装。黑胶不适宜用作加速度计的贴片胶,至少使用聚酰亚胺膜作背面保护时如此。     

3D封装的故障隔离与故障分析

3D封装是一种小尺寸、轻重量、低功耗、低成本的先进封装工艺,结合其在实际应用中通常出现的可靠性问题,从非破坏性与破坏性两方面对可用于3D封装故障隔离与故障分析的方法展开介绍.通过精确定位来暴露失效位置,使用开放性高阻故障隔离、短路故障隔离、无损及高分辨率成像技术等方法,来实现非破坏性故障隔离与分析;通过破坏性的制样和物...     

CBGA阵列的组装技术

随着计算机技术和IT技术的发展,对电路元器件的封装提出了更好的要求。期中SMT技术得到了广泛的应用,SMT封装对在高密度、高引出端数和高性能方面要求的提高,发展了陶瓷焊球阵列（CBGA）技术,本文重点介绍了陶瓷焊球（CBGA）的工艺以及封装技巧和返修方法。     

基于PFMEA的集成电路芯片银导电胶粘接工艺可靠性研究

微电子封装中,芯片银导电胶粘接工艺的质量会直接影响集成电路的可靠性。针对银导电胶粘接工艺的可靠性问题,本文提出了一种基于PFMEA的芯片粘接工艺风险识别方法,通过开展潜在失效模式分析,找到了芯片粘接工艺中的高风险环节,并制定了相应控制方法,有效提升了芯片粘接工艺质量,为微电子封装工艺开展PFMEA分析提供参考依据。     

新型埋入式板级封装技术

越来越多的高密度、多功能和小型化需求给封装和基板都带来了新的挑战,很多新的封装技术也应运而生,包括引起众多关注的埋入式封装技术.在本文中,我们首先对埋入封装技术的优势、挑战以及发展现状进行了介绍.然后通过将功能性有源器件埋入到有机基板中的尝试说明了设计、制造和测试埋入式封装这一新兴技术的可行性.制定一个切实可行的解决方案,有利于降低制造成本和市场的产品开发周期.我们提出的这种埋入式板级封装技术,与传统的封装和基板工艺都兼容.此外,本文设计了将功能性的MOSFET有源芯片埋入到有机基板中的板级封装模块结构,对该模块进行了热机械仿真分析,找到了最大应力点,优化了工艺设计.最后,结合传统的基板工艺,制备了埋入式板级封装样品,并完成了埋入式板级封装模块的电阻通断测试和功能测试,验证了该工艺设计的可行性.     

Tracing the thermal behavior of ICs

Today's increased power and packaging densities demand designers' attention to the effects of heat on ICs. The authors review thermal and electrothermal simulation and measurement methods, thermal package characterization, and the concept and techniques of design for thermal testability     

低温玻璃浆料圆片级真空封装的研究

研究了玻璃浆料在低温下真空封装MEMS器件的工艺。封装过程中,采用了丝网印刷技术,丝网的线宽设计为100μm,印刷后玻璃浆料线宽为160μm左右,从而能够减小封装器件的尺寸,节省成本;另外,对玻璃浆料键合工艺做了研究,找到了较好的工艺条件,采用该工艺(预烧结温度425℃,键合温度430℃),得到的封装结构具有较高的封接强度(剪切力>20 kgf)和良好的真空度,测得的漏率为10-9 cm3/s。     

Power-driven challenges in nanometer design

Addressing fundamental challenges to designing high-performance ICs in nanometer-scale technologies, the authors advocate a flexible approach to limiting both dynamic and static power. They recommend global-signaling strategies to curb communication power requirements and thermal management techniques to ease the burden on packaging     

Applying rough sets to prevent customer complaints for IC packaging foundry

Packaging is classified as one of back-end processes in the integrated circuits (ICs) manufacturing, highly capital-intensive and involves complex processes. Unlike the front-end process that fabricates wafers, the back-end process is rarely uniform. Because of the complexity of the process and increasing variety of products, the packaging foundry occasionally encounters complaints that can be categorized into classes depending on the loss. We apply rough set theory to discover important attributes leading to complaints and induce decision rules based on the data of a Taiwanese IC packaging foundry that ranks one of the largest in the world. The data contain 454 records and each record includes 11 condition attributes as well as one decision attribute characterizing the class. We first obtain important set of attributes that ensures high quality of classification, and then we generate rules for each class of complaints. The strongest rules obtained relate to two attributes, number of pins and wire bonding, which are important technological factors in the packaging process. These rules are presented to the foundry’s staffs who believe that the rules are potentially applicable for the future to prevent the complaints.     

3D System-on-Chip technologies for More than Moore systems

3D integration is a key solution to the predicted performance problems of future ICs as well as it offers extreme miniaturization and cost-effective fabrication of More than Moore products. Through silicon via (TSV) technologies enable high interconnect performance compared to 3D packaging. At present TSVs are associated with a relatively high fabrication cost, but research world wide strive to bring the cost down to an acceptable level. An example of a 3D System-on-Chip (3D-SOC) technology is to introduce a post backend-of-line TSV process as an optimized technology for heterogeneous system integration. The introduced ICV-SLID process, that combines both TSVs and bonding, enables 3D integration of fabricated devices. Reliability issues related to thermo-mechanical stress caused by the TSV formation and the bonding are considered. 3D-SOC technology choices made to realize a heterogeneous ultra-small IC stack for a wireless tire pressure monitoring system (TPMS) as an automotive application are described.     

Simulation of chain length recognition observed in formation of inclusion complex

We carried out Brownian dynamics simulations to investigate the mechanism of chain length recognition observed in the formation of inclusion complexes (ICs) between cyclodextrins (CDs) and polymer chains. In our simulations, we used rings and chains as models to represent CDs and polymer chains, respectively. We used two types of chains with different lengths to determine which chain was preferred by the rings to form ICs. At low concentration of rings, we observed that almost all the rings formed ICs with the long chains. Chain length recognition could be reproduced in our simulation, and it occurred because of the difference in the inclusion time between the long chains and the short chains in the ICs. On the other hand, at high concentration of rings, the number of rings forming ICs with the long chains increased, and pseudo-polyrotaxanes (PPRXs) were formed. ICs were also formed with the short chains, because the inclusion time for each ring contained in the PPRXs reduced with an increase in the number of rings therein, and then, the dissociated rings formed ICs with the short chains. As a result, chain length recognition was not observed. From these results, we conclude that the difference in the inclusion time between the rings and the chains controls chain length recognition.     

静电吸附对全自动粘片的影响及控制方法

静电是电子封装中重要的防控点,不仅对芯片电性能有致命威胁,其静电力学效应引起的吸附作用更会严重干扰小尺寸芯片的全自动组装,降低产品的成品率和一致性,为提升有效的静电防护能力,保证集成电路封装质量及可靠性,通过研究静电吸附的基本原理,说明小尺寸芯片更容易产生静电吸附效应的原因,列举控制和消除静电的方法,阐述静电吸附对全自...     

Exploring the security landscape: NoC-based MPSoC to Cloud-of-Chips

In this paper, we present a detailed and systematic overview of communication security aspects of Multi-Processor Systems-on-Chip (MPSoC) and the emerging potential threats on the novel Cloud-of-Chips (CoC) paradigm. The CoC concept refers to highly scalable and composable systems, assembled not only at system design-time using RTL, like traditional SoC, but also at integrated circuit (IC) packaging time thanks to 3D-IC integration technology. Practical implementation of CoC systems needs to solve the problem of scalable, configurable and secure communication not only between different functional blocks in a single ICs, but also between different ICs in a single package, and between different packages on the same or different PCBs and even between different systems. To boost such extremely flexible communication infrastructure CoC system relies on Software-Defined Network-on-Chip (SDNoC) paradigm that combines design-time configurability of on-chip systems (NoC) and highly configurable communication of macroscopic systems (SDN). This study first explores security threats and existing solutions for traditional MPSoC platforms. Afterwards, we propose SDNoC as an alternative to MPSoC communication security, and we further extend our discussion to CoC systems to identify additional security concerns. Moreover, we present a comparison of SDNoC based approach over existing approaches and discuss its potential advantages.     

Mapping multiple applications onto 3D NoC-based MPSoCs supporting wireless links

Three-dimensional integrated circuits (3D ICs) are suitable alternatives to traditional two-dimensional (2D) ICs by leveraging its advantage of better performance and packaging; therefore, they have been highly considered by researchers. On the other hand, emerging network-on-chip (NoC) based many-core chips provides great potential for running multiple applications simultaneously. However, using this approach leads to the increase of the interference between applications, resulting in lowering the performance of each application. Hence, mapping tasks belonging to various applications onto the nodes of an architecture is a very important issue. In this study, based on partitioning concept, a novel methodology for mapping of multiple applications at run-time onto an irregular wireless 3D NoC-based multiprocessor system-on-chip (MPSoC) platform in which more than one task can be supported by each processing element (PE) was presented. In the second algorithm (enhanced irregular-partitioning best neighbor), according to the number of applications running simultaneously, the partitioning of network will be dynamically changed to minimize the communication overhead and congestion on the NoC that leads to more efficient task mapping. The simulation results reveal that the second proposed algorithm (enhanced IPBN) in comparison with NPBN (non-partitioning best neighbor) algorithm and our first proposed algorithm (basic IPBN) enhances the performance by decreasing the total execution time, average hop count, average channel load and energy consumption.     

LTPS circuit integration for system‐on‐glass LCDs

Abstract— A 3.5‐in. QVGA‐formatted driving‐circuit fully integrated LCD has been developed using low‐temperature poly‐Si (LTPS) technology. This display module, in which no external ICs are required, integrates all the driving circuits for a six‐bit RGB digital interface with an LTPS device called a “FASt LDD TFT” and achieves a high‐quality image, narrow frame width, and low power consumption. The LTPS process, device, and circuit technologies developed for system‐on‐glass LCD discussed. The development phase of LTPS circuit integration for system‐on‐glass LCDs is also reviewed.