Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the g_m/I_D characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the g_m/I_D characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.     

Analysis of aging effects - From transistor to system level

Due to shrinking feature sizes in integrated circuits, additional reliability effects have to be considered which influence the functionality of the system. These effects can either result from the manufacturing process or external influences during the lifetime such as radiation and temperature. Additionally, modern technology nodes are affected by time-dependent degradation i.e. aging.Due to the age-dependent degradation of a circuit, processes on the atomic scale of the semiconductor material lead to charges in the oxide silicon interface of CMOS devices, altering the performance parameters of the device and subsequently the behavior of the circuit. With the continuous downscaling of modern semiconductor technologies, the impact of these atomic scale processes affecting the overall system characteristics becomes more and more critical. Therefore, aging effects need to be assessed during the design phase and actions have to be taken guaranteeing the correct system functionality throughout a system's lifetime.This work presents methods to investigate the influence of age-dependent degradation as well as process-variability on different levels. An operating-point dependent sizing methodology based on the g_m/I_D-method extended to incorporate aging, which aims at developing aging-resistent circuits is presented. Additionally, the sensitivity of circuit performances in regard to aging can be determined. In order to investigate the reliability of a complex system on behavioral level, a modeling method to represent the performance of system components in dependence of aging and process variability is introduced.     

Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the g_m/I_D characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the g_m/I_D characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.     

A new systematic design approach for low-power analog integrated circuits

In this paper, a new design approach for systematic design and optimization of low-power analog integrated circuits is presented based on the proper combination of a simulation-equation based optimization algorithm using geometric programming as an optimization approach and HSPICE as a simulation and verification tool by a knowledge-based transistor sizing tool which uses physical-based gm/I_D characteristic in all regions of transistor operation to increase the accuracy in a reasonable simulation time. The proposed design methodology is successfully used for automated design and optimization of an operational amplifier with hybrid-cascode compensation using 0.18 μm CMOS technology parameters with the main purpose of minimizing the power consumption of the circuit.     

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a g_m/I_D based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.     

Impact of technology scaling on thermal behavior of leakage current in sub-quarter micron MOSFETs: perspective of low temperature current testing

The increase in the off-state current for sub-quarter micron CMOS technologies is making conventional I_DDQ testing ineffective. Since natural process variation together with low-V_TH devices can significantly increase the absolute leakage value and the variation, choosing a single threshold for I_DDQ testing is impractical. One of the potential solutions is the cooling of the chip during current testing. In this paper we analyze the impact of CMOS technology scaling on the thermal behavior of different leakage current mechanisms in n-MOSFETs and estimate the effectiveness of low temperature I_DDQ testing. We found that the conventional single threshold low temperature I_DDQ testing is not effective for sub-quarter micron CMOS technologies and propose the low temperature ΔI_DDQ test method. The difference between pass and fail current limits was estimated more than 200× for 0.13-μm CMOS technology.     

Analog/RF Study of Self-aligned In<Subscript>0.53</Subscript>Ga<Subscript>0.47</Subscript>As MOSFET with Scaled Gate Length

This study presents the impact of gate length scaling on analog and radio frequency (RF) performance of a self- aligned multi-gate n-type In_0.53Ga_0.47As metal oxide semiconductor field effect transistor. The device is fabricated using a self-aligned method, air-bridge technology, and 8 nm thickness of the Al₂O₃ oxide layer with different gate lengths. The transconductance-to-normalized drain current ratio (g _m/I _D) method is implemented to investigate analog parameters. Moreover, g _m and drain conductance (g _D) as key parameters in analog performance of the device are evaluated with g _m/I _D and gate length variation, where g _m and g _D are both showing enhancement due to scaling of the gate length. Early voltage (V _EA) and intrinsic voltage gain (A _V) value presents a decreasing trend by shrinking the gate length. In addition, the results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.     

Highly linear wide input range CMOS OTA architectures operating in subthreshold and strong inversion

A very low distortion low-voltage CMOS OTA with very wide g_m adjustment and input range is presented. It is based on a fixed gain novel highly linear voltage-to-current conversion input stage and uses electronically programmable current mirrors to achieve very wide transconductance gain adjustment range. The OTA input range remains approximately constant with g_m adjustment. Bandwidth and input signal range can be adjusted independent of g_m. Simulations results in 0.5 μm CMOS technology with ±1 V supplies and 1 V input range are presented which confirm the characteristics of the proposed structure.     

Performance comparison of channel engineered deep sub-micrometer pseudo SOI n-MOSFETs

In this paper, with the help of extensive TCAD simulations, a novel channel and source/drain (S/D) impurity profile engineering has been proposed for pseudo SOI MOSFET structures in order to reduce their junction capacitances. It has been shown that this approach leads to improved performance and lower power dissipation for sub 100 nm CMOS technologies. These pseudo SOI structures studied in this work are referred to as the Source Drain On Depletion Layer (SDODEL) MOSFETs in the earlier studies. We have investigated DC characteristics and analog performance parameters in Single Halo SDODEL MOSFET, Double Halo SDODEL MOSFET and compared their performance with Double Halo MOSFETs (which will henceforth be referred to as Control MOSFETs) with extensive process and device simulations. Our results shows that, in Single Halo SDODEL MOSFET there is significant improvement in the intrinsic device performance for analog applications (such as device gain, g_m/I_D etc.) for the sub 100 nm technologies.     

Equivalent input spectrum and drain current spectrum for 1/ƒ noise in short channel MOS transistors

Flicker noise in MOS transistors can be evaluated by measuring the spectrum S_ID of the drain current fluctuation or the spectrum Sve of an equivalent gate fluctuation. We show here that experimental variations of are in good agreement with g_m² by considering a model of the transconductance g_m which takes into account the variations of the channel carriers mobility with the surface electric field. The model agrees with the experimental results obtained on short channel MOS transistors which exhibit large variations of mobility with the gate voltage. The validity of physical interpretations of noise data on MOS transistors is examined.     

An ultra low power CMOS pA/V transconductor and its application to wavelet filters

Two compact ultra low-power CMOS triode transconductor topologies denoted VLPT-g_m and Delta-g_m are proposed. In both circuits, input transistors are kept in the triode region to benefit from the lowest g_m/I_D ratio. This allows achieving a small-signal transconductance g_m down to hundreds of pA/V, making such transconductors attractive for the synthesis of g_m-C filters with cut-off frequencies in the range of Hz and sub-Hz. The g_m value is adjusted by a well defined aspect-ratio (W/L) and drain-source voltage V_DS, the latter a replica of the tuning voltage V_TUNE imposed as drain-source voltage of input devices. VLPT-g_m reaches a minimum g_m of 1 nA/V, whereas Delta-g_m exhibits a g_m as low as 400 pA/V. Input-referred noise spectral density is typically 12.33 μV/Hz^1/2 @ 1 Hz and 93.75 μV/Hz^1/2 @ 1 Hz for VLPT-g_m and Delta-g_m, respectively. In addition, setting their g_m equal to 1 nA/V and arranging them as first-order lossy integrators, Delta-g_m presents higher bandwidth with respect to VLPT-g_m. Cut-off frequencies are 1.33 kHz and 24 kHz for VLPT-g_m and Delta-g_m integrators, respectively. Finally, as an application example, both transconductors were used as building blocks to realize a 6th-order wavelet g_m-C filter. For both approaches, THD was kept below 1% for signal swings up to 200 mV_pp.The design complies with a 1.5 V supply and a 0.35 μm CMOS process and features an overall power consumption of 51 and 114 nW, respectively for VLPT-g_m and Delta-g_m filters.     

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g_m), the gain per unit current (g_m/I_ds), the intrinsic gain (g_mR_o), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, g_m/I_d and g_m are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.     

Novel analysis and optimization of gm-boosted common-gate UWB LNA

This paper focuses on the design optimization of g_m-boosted common gate (CG) CMOS low-noise amplifier (LNA) for ultra-wideband (UWB) wireless technology. In this regard, a detailed novel analysis of the UWB g_m-boosted CG amplifier topology is presented, which includes the finite g_ds (=1/r_eds) effects. For UWB systems, signal-to-noise ratio (SNR) can be defined as the matched filter bound (MFB). Using this definition, the noise performance of the UWB CG LNA in the presence of the g_m-boosting gain and the input noise-matching network are analyzed. It is found that the optimal noise factor of the UWB LNA collapses to the published narrowband g_m-boosted CG LNA noise factor when an assumption of narrowband is applied. It is also proved that the noise performance of the g_m-boosted UWB CG LNA is independent of the bandwidth of the input UWB signal. A new technique is presented for the design of optimal noise-matching network using passive components at the input of the UWB CG LNA. In this regard, role of the g_m-boosting stage and its effect on the SNR and the gain of the overall system are analyzed, and, in addition, its non-idealities are simulated in detail.     

Modeling transistor variation using α-power formula and its application to sensitivity analysis on harmonic distortion in differential amplifier

We propose a statistical MOSFET model using the ??-power equation for the I _D ?CV _GS curves of a transistor to make it easier to deal with transistor variations using hand calculations. We evaluated the impact of the transistor variation (mismatch) on the harmonic distortion (HD) in a differential amplifier using the statistical ??-power model along with a sensitivity simulation using SPICE. We found that the driver transistor variation majorly impacted on the 2nd HD in the differential gain, which was approximately proportional to the transistor current mismatch, whether the mismatch was induced by the threshold voltage variation or by the current factor variation. We further evaluated the HD by directly using the experimental I _D ?CV _GS curves to obtain more accurate values. The ??-power model, fitted to g _m ?CV _GS curves, described the HD more precisely, to make it more agreeable with the results obtained from the experimental data, when we used the differential current equation as a function of the transconductance (g _m ), its derivative $ \left(g_{m}^{\prime}\right) $ and their variations (??g _m and ?? $g_{m}^{\prime}\, $ ).     

The meta-stable dip (MSD) effect in SOI FinFETs

The meta-stable dip (MSD) effect is demonstrated and characterized in SOI FinFETs. With ascending scan of front-gate voltage (V_G1), the magnitude of drain current (I_D) tends to be fixed within a specific region of the front-gate voltage and this leads to a dip of transconductance (g_m). The dip width can be modulated through a control of bias condition or measurement speed such as back-gate voltage (V_G2), drain voltage (V_D) and step size of the front-gate voltage. From the dual-gate transient measurement, it is found that the MSD effect is highly dependent on the floating-body effect. In SOI FinFETs, the MSD effect is significantly affected by the fin width due to the fringing electric field of the lateral gates.     

Impact of bias condition on 1/f noise of dual-gate depletion type MOSFET in linear region and consequences for noise diagnostic application and modelling

This paper presents experimental and numerical results for 1/f noise of depletion-type dual-gate MOSFET (DGMOSFET) in the linear region of the output I_D-V_DS characteristics. In this region, both DGMOSFET inner transistors operate in either linear or non-linear region each. Gate-to-gate interelectrode spacing influence is taken into account in I_D-V_DS modelling with the effective parameter m_eff = μ_eff2L_eff1/μ_eff1L_eff2. For low bias conditions, the parameter m_eff can be reduced to the ratio of inner transistors channel effective lengths. A model for the normalized 1/f noise parameter and methodology for its calculation valid for the DGMOSFET linear region have been proposed. Due to interdependence of the inner transistors bias condition, their participation in total noise is controlled by weighting factors. This fact must be taken into account in the noise diagnostic procedure for DGMOSFET analysis.     

Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation

This paper investigates and compares the impacts of metal-gate work-function variation on important analog figures-of-merit (FOMs) for TFET and FinFET devices using 3-D atomistic TCAD simulations. Our study indicates that, at 0.6 V supply voltage and 0.2 V gate-voltage overdrive, TFET exhibits superior variation immunity regarding transconductance to drain–current ratio (g_m/I_DS), output resistance (R_out) and intrinsic gain, and comparable variability in g_m and cutoff frequency (f_T) as compared with the FinFET counterparts. In addition, how the correlations between pertinent parameters (e.g., g_m and R_out) impact the variation immunity of important analog FOMs are analyzed. Our study may provide insights for low-voltage analog design using TFET/FinFET technologies.     

On <Emphasis Type="Italic">g</Emphasis><Subscript>m</Subscript>-boosted follower-amplifier and its novel circuit transformation based mid-band derivations

This brief paper investigates the small-signal mid-band behavior of g _m-boosted follower-amplifiers which has not been explored previously and whose analysis is not available in text-books or any other source. Both g _m-boosted source follower and g _m-boosted emitter follower are considered in the mid-band analysis. A novel circuit/source transformation based “pictorial” technique with progressively simplified circuit diagrams is employed for this mid-band analysis which generally eliminates the need for solving nodal or mesh equations. Final expression is often achieved by inspection of the simplified circuit without the need for circuit analysis. The paper also discusses g _m-boosted BiCMOS follower amplifier using substrate PNP device in a pure CMOS process. The analysis demonstrates that the unity gain accuracy of follower-amplifier can be considerably enhanced using the g _m-boosting technique without sacrificing bandwidth.     

Systematic approach for IG-FinFET amplifier design using gm/Id method

In this paper, a systematic approach has been used to apply gm/Id method for the design of Independent Gate (IG) FinFET amplifiers. The design of high-performance amplifiers using g_m/I_d method has been successfully applied to nanometer devices. IG-FinFETs have been widely used in digital circuit implementations. However, the application of IG-FinFETs in analog circuits is limited and brings many advantages including low power, low voltage operation of transistors. Independent gates of FinFET can receive different voltages that facilitate low voltage operation of the circuit. Simulation-based g_m/I_d method has been applied to IG-FinFET transistors and a systematic methodology has been developed for the design of IG-FinFET amplifiers. The Berkeley BSIM-IMG 55 nm technology parameters have been used for HSPICE simulations. The designed amplifier has a DC gain of about 45 dB while consuming 6.5 µW from single 1 V power supply.