高k栅介质薄膜材料研究进展

金属-氧化物-半导体场效应晶体管(MOSFET),要求其器件特征尺寸越来越小,当光刻线宽小于100nm尺度范围后,栅介质氧化物层厚度开始逐渐接近(1～1.5)nm,这时电子的直接隧穿而导致栅极漏电流随栅氧化层厚度的下降而指数上升,此外,当栅氧化层薄到一定程度后,其可靠性问题,尤其是与时间相关的击穿及栅电极中的杂质向衬底的扩散等问题,将严重影响器件的稳定性和可靠性.因此需要寻找一种具有高介电常数的新型栅介质材料来替代SiO2,在对沟道具有相同控制能力的条件下(栅极电容相等),利用具有高介电常数的介质材料(一般称为高k材料)作为栅介质层可以增加介质层的物理厚度,这将有效减少穿过栅介质层的直接隧穿电流,并提高栅介质的可靠性.本文介绍了高k栅介质薄膜材料的制备方法,综述了高k栅介质薄膜材料研究的应用要求及其研究发展动态.     

隧穿结对具有中间层的非晶硅/微晶硅叠层电池的影响

为了改善非晶硅/微晶硅叠层电池的载流子输运效果,将隧穿结引入到具有中间层结构的叠层电池中,研究了隧穿结的结构、掺杂浓度、厚度等条件对叠层电池性能的影响.实验结果表明,叠层电池中引入隧穿结构成“隧穿结-中间层”结构,可以进一步改善电池性能,经过结构和参数优化的隧穿结可以提高子电池的电流密度匹配度,提升叠层电池转换效率.加...     

固-固结构声子晶体中SH波的色散关系及其全反射隧穿

利用边界条件推导出SH波在多层介质系统中的转移矩阵,得出了SH波在一维固-固结构声子晶体中的色散函数。利用色散函数研究了SH波在一维固-固结构声子晶体中的全反射隧穿效应,得出SH波的全反射隧穿导带的特征:全反射隧穿导带的频率中心随入射角的增加而向高频方向移动,全反射隧穿导带的频率宽度随入射角的增加而减小;全反射隧穿导带的频率中心和频率宽度都随周期厚度的增加而减小。     

金属/绝缘体/金属(Al/Al2O3/Au)隧道结的发光衰减机制

结合Al/Al2 O3 /Au结构MIM(metal/insulator/metal)隧道结I U特性、深度Auger谱及结发光后结面透明度的测试与观察 ,对其发光衰减机制进行了研究。结果表明 ,由于MIM结工作时 ,通过隧道电流等产生的大量焦耳热引起底电极Al膜不断氧化 ,中间栅Al2 O3 的厚度不断增加 ,从而使得隧穿电子激发表面等离极化激元 (surfaceplasmonpolariton ,SPP)的强度不断变弱 ,引起SPP耦合发光的强度不断衰减     

SiCl4/H2为气源低温沉积多晶硅薄膜低温电学特性的研究

对用SiCl4/H2为源气体、采用等离子体增强化学气相沉积(PECVD)技术制备的多晶硅薄膜进行了低温电学特性的研究.实验结果表明,多晶硅薄膜的暗电导强烈依赖于温度,在300～90K的温度范围内呈现不同的导电特性.对多晶硅薄膜,其导电特性还与晶化率有关,晶化率越大电导率越大.测量数据表明,低晶化率薄膜电输运主要由电子热发射跃过势垒所贡献,但对于高晶化率的薄膜要同时考虑电子隧穿对电导的影响.     

SiO2层上沉积的纳米多晶硅薄膜及其特性

采用低压化学气相沉积(LPCVD)系统以高纯SiH4为气源,在p型10.16 cm<100>晶向单晶硅衬底SiO2层上制备纳米多晶硅薄膜,薄膜沉积温度为620℃,沉积薄膜厚度分别为30 nm、63 nm和98 nm.对不同薄膜厚度的纳米多晶硅薄膜分别在700℃、800℃和900℃下进行高温真空退火.通过X射线衍射(XRD)、Raman光谱、扫描电子显微镜(SEM)和原子力显微镜(AFM)对SiO2层上沉积的纳米多晶硅薄膜进行特性测试和表征,随着薄膜厚度的增加,沉积态薄膜结晶显著增强,择优取向为<111>晶向.通过HP4145B型半导体参数分析仪对沉积态掺硼纳米多晶硅薄膜电阻I-V特性测试发现,随着薄膜厚度的增加,薄膜电阻率减小,载流子迁移率增大.     

薄膜厚度对PZT/STO铁电电容器隧穿电阻的影响

结合Landau-Devonshire自由能理论和晶格模型,研究了PbZr1-xTixO3(PZT)/SrTiO3(STO)复合薄膜中PZT和STO厚度对铁电隧道结极化强度、电导和隧穿电阻等的影响。模拟结果表明,随着层数增加,极化强度增大;平均极化强度随着PZT厚度增加而增强,随着STO厚度增加而减弱;随着PZT和STO厚度增加,电导减小,隧穿电阻率增加;当厚度变化相同时,PZT引起电导的变化大,隧穿电阻率变化小。考虑薄膜面积的影响,当薄膜面积从无限大变成有限大时,极化强度、电导和隧穿电阻均减小。     

64K DRAM多晶硅条宽控制及高选择性技术

一、引言64K DRAM-CM4864(64K动态随机存贮器)是目前国内集成度最高、线条最窄的超大规模集成电路(VLSJ)。在芯片面积为(3.93×7.56)mm~2上集成了15万多个元件。它采用了双层多晶硅结构、SiO_2/Si_3N_4/SO_2复合栅工艺、PSG(磷硅玻璃)平坦化技术。其场氧层厚度为9500(?)、一次多晶厚度为5000(?)、二次多晶厚度为3800(?)、PSG厚度为12000(?)、Al-Si(Si含量为1.2%)厚度为10000～11000(?)。在所有这些高低不平的     

非挥发浮栅存储器用PtAu纳米颗粒单层膜的制备

将Langmuir-Blodgett（LB）膜等化学方法应用于非挥发浮栅存储器制备工艺中．采用反相微乳液方法合成的分散良好的PtAu纳米颗粒粒径约为5m,并应用LB膜方法在存储器隧穿氧化层上制备了PtAu纳米颗粒的单层膜．采用SEM对LB膜的表面形貌进行观测,研究了表面压对成膜质量的影响,结果表明在表面压为15mN／m时可获得密度为10^11cm^-2均匀分布的PtAu纳米颗粒单层二维阵列,可应用于非挥发性金属纳米颗粒浮栅存储器,并成功拓展了LB膜等化学方法的应用范围．     

石墨衬底上多晶硅厚膜的生长及性质分析

以石墨片为衬底,利用磁控溅射技术生长多晶硅籽晶层,退火处理后用CVD制备多晶硅厚膜。XRD测试结果表明,在籽晶层上外延多晶硅厚膜具有高度的(220)取向,这说明外延层的择优取向延续了籽晶层的取向。SEM测试结果表明,石墨片上多晶硅外延层生长良好,说明石墨片作为廉价衬底之一,有望投入工业化生产,以降低太阳能电池的制作成本。     

Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter.     

Effects of tunnel oxide process on SONOS flash memory characteristics

In this paper, various process conditions of tunnel oxides are applied in SONOS flash memory to investigate their effects on charge transport during the program/erase operations. We focus the key point of analysis on Fermi-level (E_F) variation at the interface of silicon substrate and tunnel oxide. The Si-O chemical bonding information which describes the interface oxidation states at the Si/SiO₂ is obtained by the core-level X-ray photoelectron spectroscopy (XPS). Moreover, relative E_F position is determined by measuring the Si 2p energy shift from XPS spectrums. Experimental results from memory characteristic measurement show that MTO tunnel oxide structure exhibits faster erase speed, and larger memory window during P/E cycle compared to FTO and RTO tunnel oxide structures. Finally, we examine long-term charge retention characteristic and find that the memory windows of all the capacitors remain wider than 2 V after 10⁵ s.     

Memory characteristics of Al<Subscript>2</Subscript>O<Subscript>3</Subscript>/LaAlO<Subscript>3</Subscript>/SiO<Subscript>2</Subscript> multilayer structures with tunnel oxide thickness variation

Charge trap flash (CTF) memory devices are candidates to replace NAND flash devices. In this study, Pt/Al₂O₃/LaAlO₃/SiO₂/Si multilayer structures with lanthanum aluminate charge traps were fabricated for nonvolatile memory device applications. An aluminum oxide film was used as a blocking oxide for low power consumption in the program/erase operation and to minimize charge transport through the blocking oxide layer. The thickness of SiO₂ as tunnel oxide layer was varied from 30 to 50 Å. Thicknesses of oxide layers were confirmed by high resolution transmission electron microscopy (HRTEM) and all the samples showed amorphous structure. From the C–V measurement, a maximum memory window of 3.4 V was observed when tunnel oxide thickness was 40 Å. In the cycling test for reliability, the 30 Å tunnel oxide sample showed a relatively large memory window reduction by repeated program/erase operations due to the high electric field of ~10 MV/cm through tunnel oxide. The other samples showed less than 10% loss of memory window during 10⁴ cycles.     

Characterization of tunnel-oxide degradation due to plasma field oxide recess in flash memory devices

This paper presents the characterization of degradation of tunnel oxide during plasma recess of field oxide films for Shallow Trench Isolation (STI) in sub 30 nm flash memory devices. Simple plasma charge damage monitor wafers with Metal-Oxide-Semiconductor (MOS) capacitor structures were used to analyze the mechanisms of degradation of tunnel oxide due to process-induced charging damage. We characterized the gate leakage currents and breakdown voltages of MOS capacitors with area antennas after performing the plasma process for field oxide recess of STI with various etching conditions in a dual-frequency capacitively coupled plasma reactor. The results showed that the degradation was strongly dependent on plasma non-uniformity, which could be improved by optimizing the radio-frequency and biasing power. Especially, we found that RF biasing power caused stress-induced leakage currents due to dielectric breakdown by the leakage current originating from the electrostatic chuck.     

Fabrication and program/erase characteristics of 30-nm SONOS nonvolatile memory devices

In this paper, we have fabricated nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices by means of the sidewall patterning technique. The fabricated SONOS devices have a 30-nm-long and 30-nm-wide channel with 2.3/12/4.5-nm-thick oxide/nitride/oxide film on fully depleted-silicon-on-insulator (FD-SOI) substrate. The short channel effect is well suppressed though devices have very short channel length and width. Also, the fabricated SONOS devices guarantee good retention and endurance characteristics. In 30-nm SONOS devices, channel hot electron injection program mechanism is inefficient and 2-b operation based on localized carrier trapping in the nitride film is difficult. The erase speed is improved by means of band-to-band (BTB) assisted hole injection mechanism. In 30-nm SONOS devices, program and erase operation can be performed efficiently with improved erase speed by combination of Fowler-Nordheim (F-N) tunneling program and BTB assisted hole injection erase mechanism because the entire channel region programmed by F-N tunneling can be covered by two-sided hole injection from source and drain.     

Improved electrical and reliability characteristics in metal/oxide/nitride/oxide/silicon capacitors with blocking oxide layers formed under the radical oxidation process

We propose a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) structure whose blocking oxide is formed by radical oxidation on the silicon nitride (Si3N4) layer to improve the electrical and reliability characteristics. We directly compare the electrical and reliability properties of the MONOS capacitors with two different blocking oxide (SiO2) layers, which are called a "radical oxide" grown by the radical oxidation and a "CVD oxide" deposited by chemical vapor deposition (CVD) respectively. The MONOS capacitor with a radical oxide shows a larger C-V memory window of 3.6 V at sweep voltages from 9 V to -9 V, faster program/erase speeds of 1 micros/1 ms at bias voltages of -6 V and 8 V, a lower leakage current of 7 pA and a longer data retention, compared to those of the MONOS capacitor with a CVD oxide. These improvements have been attributed to both high densification of blocking oxide film and increased nitride-related memory traps at the interface between the blocking oxide and Si3N4 layer by radical oxidation.     

Scaling considerations for sub-90 nm split-gate flash

A systematic methodology is presented to scale split-gate (SG) flash memory cells in the sub-90 nm regime within the presently known scaling constraints of flash memory. The numerical device simulation results show that the high performance sub-90 nm NOR-type SG cells can be achieved by a suitable channel and source-drain engineering. An asymmetric channel doping profile along with ultra-shallow source-drain junctions was used to achieve the target drain programming voltage (V_sp) for an efficient cell programming while keeping the cell breakdown voltage, BV > V_sp, with tolerable leakage currents. The study shows that with properly optimised technology parameters, 65 nm SG-NOR flash memory can be achieved with an adequate cell read current, a tolerable programmed cell leakage current at the read condition and efficient write and erase times.     

Analysis of the energy distribution of interface traps related to tunnel oxide degradation using charge pumping techniques for 3D NAND flash applications

The energy distribution and density of interface traps (D_it) are directly investigated from bulk-type and thin-film transistor (TFT)-type charge trap flash memory cells with tunnel oxide degradation, under program/erase (P/E) cycling using a charge pumping (CP) technique, in view of application in a 3-demension stackable NAND flash memory cell. After P/E cycling in bulk-type devices, the interface trap density gradually increased from 1.55 × 10¹² cm⁻² eV⁻¹ to 3.66 × 10¹³ cm⁻² eV⁻¹ due to tunnel oxide damage, which was consistent with the subthreshold swing and transconductance degradation after P/E cycling. Its distribution moved toward shallow energy levels with increasing cycling numbers, which coincided with the decay rate degradation with short-term retention time. The tendency extracted with the CP technique for D_it of the TFT-type cells was similar to those of bulk-type cells.     

Write/erase degradation and disturb effects in source-side injection flash eeprom devices

An in-depth analysis of the write/erase degradation of source-side injection flash EEPROM devices is performed, which reveals two mechanisms underlying this degradation: a decrease of the charge per cycle on the floating gate, accompanied by the series effect of oxide and interface charges locally trapped above the channel. In addition, the main disturb effects are characterized and shown to be non-critical for reliable cell operation.     

Preparation and photoelectrocatalytic properties of polyaniline/layered manganese oxide self-assembled film

The composite material of polyaniline (PANI)/layered manganese oxide film electrode was prepared by the layer-by-layer adsorption technique. The corresponding photoelectrocatalytic activity was studied for the degradation of Rhodamine B (RhB) under visible light irradiation (λ > 400 nm). The efficiency of the self-assembled film to assist photodegradation of RhB improved significantly with an applied potential of 0.9 V vs. standard calomel electrode. The results showed that PANI could enhance the efficiency of photon harvesting, and the impressed current could reduce the chance of electron-hole recombination. A synergetic effect was found between PANI and MnO₂. This study proposed an effective material for the photoelectrocatalytic degradation of RhB under visible light irradiation.