Silicon nanocrystal memories: a status update

In the last decade, the silicon nanocrystal memory technology has received widespread interests from the scientific community working in the field of non-volatile solid-state memories, considering it as a feasible candidate for the post-Flash scenario. The immunity to stress-induced leakage current and the reduction of parasitic floating-gate capacitive couplings make the nanocrystal technology very attractive, especially when considering the CMOS compatible process flow. However, many open issues still exist for its development, first of all concerning its scaling perspectives. Starting from the discussion of the basic principles of nanocrystal storage, in this paper we review the major benefits and the open challenges of the silicon nanocrystal memory technology.     

Nano-scaled chalcogenide-based memories

Today phase change memory (PCM) technology has reached product maturity at 90 and 65 nm nodes, while the 45 nm node is under development and is expected to enter in the market soon. The continuous decrease of the cell size with scaling leads to an effective active area as small as 150 nm(2) and an active volume involved in the phase transformation of about 10(4) nm(3), thus entering definitively into the nanotechnology world. At this extremely reduced dimension, the reliability of the device must be carefully investigated. In this work we show that the cycling performance of the device is well maintained, not being a problem for either the bipolar transistor or the storage element. The phase transition from the amorphous to the crystalline state is, of course, one of the most interesting phenomena, impacting cell retention capability and device performance. The stochastic nature of nano-nuclei percolation in the amorphous matrix is shown as an important ingredient in the retention of PCM devices. The related dispersion in crystallization times is analyzed through a crystallization Monte Carlo model and a physical insight into nucleation and growth mechanisms is provided.     

Ultrashort SONOS memories

We report the operational characteristics of ultrashort SONOS memories down to /spl sim/30-nm effective gate length. Good sub-threshold swing, good drain-induced barrier lowering (/spl sim/120 mV/decade), and /spl sim/2.4 V of memory window down to the smallest dimensions demonstrate the improvements that result from a thin tunneling oxide and a large trapping center density. The use of distributed defects and thin tunneling oxide is reflected in a memory window that is stable up to at least 10/sup 5/ cycles for the smallest devices. The smallest structures tested employ /spl sim/75 electrons for memory storage, which allows for device to device reproducibility. The capture and emission processes asymmetries point to the differences in the energy parameters of the two processes. The smallest structures, however, do show loss of retention time compared to the larger structures, for the same oxide-nitride-oxide stack thickness, and this is believed to arise from higher leakage due to higher defects distribution in the gate insulators from process-induced damage. All tested devices, down to /spl sim/30-nm effective gate length, show very good endurance characteristics.     

印片机的核心——电子光阀

1、电子光阀的作用 人们在照相时需根据光线的强弱情况确定光圈大小及快门的速度,以适应胶卷的感光度拍出美丽的像片.电影胶片的印制是根据底片的密度、颜色及印片机速度确定每个画面的光号值.光阀就像照相机快门的B门,根据光号值控制红、绿、蓝色光量,使电影胶片正确感光.照相机的快门只有一个,用它来控制曝光量;而印片机的光阀有三个,分为红、绿、蓝色三种光阀,分别控制红、绿、蓝单色光的通过量,最终相加合成为总光,通过曝光窗给电影胶片曝光.照相时是胶卷底片不动快门闪动进行曝光.印片机印片时是曝光窗不动胶片进行连续(或间歇)运动曝光.光阀就像照相机的B门是常开的.     

Semiconductors for optical memories

Optical nano-structures can be produced in semiconducting materials by exposure to focused beams of energetic ions. By proper choice of implantation conditions, pixel densities reach ultra-high values of 10¹⁰–10¹² pix/cm². Silicon and diamond constitute excellent recording media with practically unlimited life times of the implanted patterns. Thus, ionography with these media provides a perfect tool for safe mass storage of archival data.     

Floating gate memories reliability

Besides conventional IC failure mechanisms, the floating gate (FG) device reliability is affected by data retention, characteristic of non-volatile memories, and endurance, typical of electrically erasable arrays. The subjects of this work are EPROM and flash EEPROM, the leading and most promising devices among the FG non-volatile memories. The degradation mechanisms observed in programming and erasing steps are investigated. EPROM data retention is associated with intrinsic and defect related charge loss with both electronic and ionic processes involved. Experimental results are presented. The reliability problems associated with repeated write/erase cycles are introduced, and their effects on EEPROM endurance discussed. Finally, a fishbone diagram for data retention is proposed. The complexity of technology and the cell scaling down with increasing chip size impose lower failure rate goals and reliability becomes integrated within the manufacturing process.     

Evaluation of multilevel memories

Proposed memory hierarchy technologies and configurations are usually evaluated by repeated running of "typical" jobs through simulated hierarchies while various parameters are adjusted. Simulation is too slow to be a tool for selecting among the choices in 1) technologies to be included, 2) implementation of each technology, and 3) management of data flow in the hierarchy. Four current hardware-managed hierarchies are described in a manner which parameterizes their design. The evaluation process is described in terms of address traces, hit ratios, and system cost performance. Stack processing is then described as a replacement for simulation that obtains hit-ratio data 1000 times faster than before. Finally, an example is given to illustrate how to select between two competing technologies, how to design the best hierarchy, and how to determine the information flow which optimizes the total cost performance of the system.     

Ge-nanodot multilayer nonvolatile memories

1-5 period multilayers of Ge nanodots (NDs) for nonvolatile memories have been self-assembled by ion beam sputtering deposition of an ultra-small amount of Ge between SiO(2) layers at room temperature without post-annealing. High-resolution transmission electron microscopy demonstrates the existence of Ge ND layers well defined with respect to the SiO(2)/Si interface. The memory window that is estimated by capacitance-voltage hysteresis is proportional to the period, and finally reaches a plateau of about 11?V asymptotically over three periods. The program speed is enhanced over the full pulse-time range by increasing bias voltage or period. The charge-loss speed in the programmed state is slower in the samples with larger period. These memory properties are discussed based on possible physical mechanisms.     

Woven thin-film wire memories

Extraordinary advances in electronic computers can be expected with the development of newer types of quick-access memories. Much research is being carried out, at present, on the use of magnetic thin-films for magnetic memories. Since many elements must be employed, it is desirable that each bit be absolutely reliable, simple, inexpensive, and suitable for mass production. Through basic experiments, the authors have confirmed the possibility of utilizing a fine diameter wire whose surface has been continuously coated or electroplated with a ferromagnetic thin-film for high-speed memories. Sample woven-type memory matrices, 50 by 50 bits, 64 by 100 bits, and 100 by 100 bits, were constructed using 0.2-mm diameter coated wires for digit and sense circuit operation, and 0.07-mm insulated wires for the drive circuit operation. Tests on the relation between the writing, the drive pulse currents, and the output voltages revealed many superior features not found heretofore in other types of thin-film memories. Means are being devised for the weaving methods and for the elimination of mutual interference between adjacent bits. This paper also discusses the characteristics of the coated wire and the performance of samples constructed for practical use.     

Nanoionics-based resistive switching memories

Many metal-insulator-metal systems show electrically induced resistive switching effects and have therefore been proposed as the basis for future non-volatile memories. They combine the advantages of Flash and DRAM (dynamic random access memories) while avoiding their drawbacks, and they might be highly scalable. Here we propose a coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms. The ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed by local redox processes. From this insight, we take a brief look into molecular switching systems. Finally, we discuss chip architecture and scaling issues.     

Scaling limits of resistive memories

This paper is intended to provide an expository, physics-based, framework for the estimation of the performance potential and physical scaling limits of resistive memory. The approach taken seeks to provide physical insights into those parameters and physical effects that define device performance and scaling properties. The mechanisms of resistive switching are based on atomic rearrangements in a material. The three model cases are: (1) formation of a continuous conductive path between two electrodes within an insulating matrix, (2) formation of a discontinuous path of conductive atoms between two electrodes within an insulating matrix and (3) rearrangement of charged defects/impurities near the interface between the semiconductor matrix and an electrode, resulting in contact resistance changes. The authors argue that these three model mechanisms or their combinations are representative of the operation of all known resistive memories. The central question addressed in this paper is: what is the smallest volume of matter needed for resistive memory? The two related tasks explored in this paper are: (i) resistance changes due to addition or removal of a few atoms and (ii) stability of a few-atom system.     

Single-mask bubble memories: Bit/Chip organization with decoding

Progress in element and chip design of single-mask bubble chips, based on drive-field operation, is reported. Three new elements, which have been successfully operated, are presented. (i) The replicator copies bubble streams for one propagation direction; when used in combination with the sense of rotation of the drive field it can serve as a bit generator. (ii) The λ-creator can selectively shift a bit over one propagation period. It can be applied in a decoder organization which permits rapid access to stored information. (iii) A current-controlled splitter-type generator was designed, which takes current pulses of about 60 mA for creating new bubbles.