Graded-junction gate/n- overlapped LDD MOSFET structuresfor high hot-carrier reliability

A newly developed gate/n^- overlapped LDD MOSFET was investigated. The MOSFET was fabricated by an oblique rotating ion implantation technique. A formula for the impurity ion profile was derived to analyze the lowering of substrate current and improvement of the degradation caused by the hot-carrier effect of the MOSFET. It was proved that the impurity ion profile near the drain edge is remarkably graded in the directions along channel and toward substrate even just after the implantation, so that the maximum lateral electric field is relaxed as compared with conventional LDD MOSFETs. Also, the maximum point of the lateral electric field at the drain edge is located apart from the main path of the channel current     

A new approach for characterizing structure-dependent hot-carriereffects in drain-engineered MOSFET's

In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N_it ) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N_it distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N_it spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

包含衬底电流的LDD MOSFET输出I-V特性的经验模型分析

采用双曲正切函数的经验描述方法和器件物理分析方法,建立了适用于亚微米、深亚微米的LDD MOSFET输出I-V特性解析模型,模型中重点考虑了衬底电流的作用.模拟结果与实验有很好的一致性.该解析模型计算简便,对小尺寸器件中的热载流子效应等能够提供较清晰的理论描述,因此适用于器件的优化设计及可靠性分析.     

包含衬底电流的LDD MOSFET输出I-V特性的经验模型分析

采用双曲正切函数的经验描述方法和器件物理分析方法 ,建立了适用于亚微米、深亚微米的 L DD MOSFET输出 I- V特性解析模型 ,模型中重点考虑了衬底电流的作用 .模拟结果与实验有很好的一致性 .该解析模型计算简便 ,对小尺寸器件中的热载流子效应等能够提供较清晰的理论描述 ,因此适用于器件的优化设计及可靠性分析     

轻掺杂漏(LDD)MOSFET的数值模拟

轻掺杂漏(LDD)MOSFET是一种已用在VLSI中的新型MOSFET结构.为了有效地进行LDD MOSFEI的优化设计,我们在二维数值模拟器MINIMOS的基础上,修改了边界条件及输入输出格式,考虑了轻掺杂区的杂质分布,研制成功了一种既适用于常规以MOSFET,又适用于LDD MOSFET的二维数值模拟程序FD-MINIMOS.应用该程序对LDD MOSFET的一系列直流特性模拟的结果表明,不同的轻掺杂浓度对于抑制沟道电场及热电子效应具有不同的效果,为轻掺杂区优化设计提供了重要信息.     

基于DCIV法对pMOSFET热载流子损伤的研究

利用新型的直流电流电压(DCIV)法研究了热载流子应力下的亚微米pMOSFET的氧化层陷阱电荷和表面态产生行为,并对热载流子应力下pMOSFET的阈值电压和线性区漏端电流的退化机制做出了物理解释.实验发现在栅极电压较高的热载流子应力条件下,热载流子引发表面态密度随时间变化的两个阶段:第一阶段,电负性的氧化层陷阱电荷起主导作用,使线性区漏端电流随时间增加;第二阶段,表面态逐渐起主导作用,导致线性电流随时间逐渐减小.     

Numerical simulation of avalanche hot-carrier injection in short-channel MOSFET's

Based on two-dimensional MOSFET simulation, the substrate and gate currents resulting from impact ionization generated electron-hole pairs and their injection into the gate oxide are calculated. The improved injection model uses a nonMaxwellian distribution function and considers separate contributions to the gate current from both thermionic-emission and oxide-barrier tunneling. A fine structure in experimentally observed I/sub g//sup e/ vs. v/sub g/ curves for thin-oxide devices at v/sub g/ approximately=2.3v/sub d/ is simulated. Simulation of a lightly doped drain (LDD) MOSFET also reveals the unusual feature of a double hump in the substrate current and an abrupt increase of the gate current beginning at v/sub g/ approximately=3/2v/sub d/.<>     

MOSFET substrate current model for circuit simulation

A simple, accurate MOSFET substrate current model suitable for a circuit simulator is presented. The effect of substrate bias on substrate current is modeled without introducing additional parameters. The accuracy of this model is demonstrated by its ability to fit the experimental data for both standard and LDD devices with average errors of less than 6%. The new model is compared with the substrate current models reported in the literature. In addition, the temperature dependence of the substrate current in the range of 0-120°C is also modeled. The new model has been implemented in a circuit-level hot-electron reliability simulator, and the results obtained from simulation of an inverter circuit are presented     

A new method for characterizing the spatial distributions ofinterface states and oxide-trapped charges in LDD n-MOSFETs

Previous studies showed that simultaneous determination of the interface states (Nit) and oxide-trapped charges (Q_ox) in the vicinity of the drain side in MOS devices was rather difficult. A new technique which allows a consistent characterization of the spatial distributions of both hot-carrier-induced Nit and Q_ox is presented. Submicron LDD n-MOS devices were tested and charge pumping measurements were performed. The spatial distributions of both Nit and Q _ox have been justified by two-dimensional (2-D) device simulation of the I-V characteristics for devices before and after the stress. Comparison of the drain current characteristics between simulation and experiment shows very good agreement. Moreover, results show that fixed-oxide charge effect is less pronounced to the device degradation for the experimental LDD-type n-MOS devices     

Hot-electron-induced degradation of conventional, minimum overlap,LDD and DDD N-channel MOSFETs

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n^- doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n⁺ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n^- doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe     

An efficient method for characterizing time-evolutional interfacestate and its correlation with the device degradation in LDD n-MOSFETs

A new characterization method is proposed to study the relationship between the hot-carrier-induced interface state N_it (x) and the device drain current degradation of submicron LDD n-MOSFETs. In this method, by making use of the conventional charge pumping measurement in combination with the power-law dependence of interface damages on stress time, the spatial distribution N_it(x) and the effective damaged length L_dam can be easily extracted. The time evolution of the interface state generation and its correlation with the device degradation can then be well explained. It is worthwhile to note that this newly developed method requires no repetitive charge pumping measurements, and hence avoids he likely imposition of re-stress on tested devices. By combining the characterized L_dam and N_it quantitatively, the results show that the damage at L_dam and V_GS≈V _DS/2 is most highly localized among various stress biases, which can explain why the generated interface states will dominate the device drain current degradation at this bias after long-term operating conditions     

Hot carrier hardness analysis of submicrometer LDD devices

A detailed analysis of the degradation of various lightly doped drain (LDD) devices is presented. Technology parameters that are varied are gate length, LDD n-dose, and energy for devices with 20-nm gate oxide. Different DC stress conditions are investigated. To gain insight into the degradation process a simulation tool is used that self-consistently calculates the oxide damage during a DC stress experiment. This enables the location and amount of oxide charges and interface states due to hot carrier injection to be obtained. The relationship between stress-induced damage and device hot carrier hardness is discussed     

Hot-carrier injection suppression due to the nitride-oxide LDDspacer structure

The hot-carrier effects in silicon nitride lightly doped drain (LDD) spacer MOSFETs are discussed. It is found that the oxide thickness under the nitride film spacer affects the hot-carrier effects. The thinner the LDD spacer oxide becomes, the larger the initial drain current degradation becomes at the DC stress test and the smaller the stress time dependence becomes. After the DC stress test, reduced drain current recovers at room temperature. These phenomena are due to the large hot-carrier injection into the LDD nitride spacer, because the nitride film barrier height is much less than the silicon oxide barrier height. Therefore, it is necessary to form the LDD spacer oxide, in order to suppress the large hot-carrier injection in the nitride film LDD spacer MOSFET. The drain current shift mechanism in the nitride spacer MOSFETs is discussed, considering the lucky electron model     

A new assessment of the self-limiting hot-carrier degradation inLDD NMOSFET's by charge pumping measurement

By progressively lowering the gate-base level in the charge pumping (CP) measurement, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer-oxide regions, extending the interface that can be probed. This constitutes the basis of a new technique that separates the hot-carrier-induced interface states in the respective regions. Linear drain current degradation, measured at low and high gate bias, provides clear evidence that interface state generation initiates in the spacer region and progresses rapidly into the overlap/channel regions with stress time in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction     

热载流子效应对CCD片上放大器寿命的影响

针对CCD片上放大器的寿命进行了研究。通过设计独立的MOSFET,使用衬底电流模型进行热载流子效应分析,研究其特性参数Gm退化量与退化时间关系,由此评价组成CCD片上放大器的寿命。研究结果表明,CCD片上放大器寿命随着栅长的减小而降低,制作LDD结构可提高CCD片上放大器寿命。     

A unified model for the self-limiting hot-carrier degradation inLDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V_d, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V_d's, along the stress time axis, until the characteristics merge into a single curve     

Features and mechanisms of the saturating hot-carrier degradationin LDD NMOSFETs

Propagation of defects from the sub-spacer region to the gate-overlapped LDD region in NMOSFETs is modeled using measurements and 2-D device simulation. It is argued that the saturation of degradation is caused by the saturating nature of this degradation length, as opposed to decreasing lateral electric field maxima (E_m) or increasing barrier height (φ_it) to defect creation. Two stage hot-carrier degradation was observed in our LDD NMOSFETs. The early mode (1000-3000 s) of the degradation is characterized by a sharp rate of degradation of the linear transconductance (g_m), and a reduction in the substrate current (I_B). In order to locate and quantify defects produced in this early mode degradation phase, we use the results of a combination of the floating gate technique and simultaneous measurements of the reverse (source and drain interchanged) saturation g_m's. These results help us build a 2-D simulation framework involving trapped negative charges in the oxide in the drain-side gate-edge region, partly under the gate and partly in the spacer region. We then use 2-D simulation and other measurements such as linear and saturation current degradation, I_B degradation, and charge pumping to confirm the location of the defects and help estimate their quantity. Simulation results also help us build an analytical model for defect propagation from the early mode to the late mode. The analytical model is seen to explain many features of the saturating nature of hot-carrier degradation     

亚微米、深亚微米LDD MOSFET的衬底电流模型中特征长度改进的描述

建立了衬底电流模型中特征长度参数的改进描述,该参数的引入使衬底电流模型能够有效地适用于从微米尺寸到亚微米、深亚微米尺寸的LDD MOSFET.在以双曲正切函数描述的I-V特性基础上,该解析模型的运算量远低于基于数值分析的物理模型,其中提取参数的运用也大大提高了模型的精度,模拟结果与实验数据有很好的一致性.     

MOSFET drain engineering analysis for deep-submicrometerdimensions: a new structural approach

A new MOS transistor structural approach (hot-carrier-induced MOSFET) capable of substantially suppressing adverse hot-carrier effects, while maintaining the other desired performance and manufacturability characteristics of deep-submicrometer MOSFETs (L _gate⩽0.35 μm) is described. This structure is unique in having a lower doped N^- region located behind (or above) a very shallow, steeply profiled source/drain junction. In contrast, LDD types of MOSFETs have an N^- region with a more graded doping profile immediately adjacent to the channel region. The simulated characteristics of the HCS MOSFET structure indicate approximately one order of magnitude less substrate current in comparison to an LDD type of MOSFET whose structure and doping parameters are optimized for combined performance, reliability, and manufacturability. In terms of combined performance, reliability, and manufacturability, the HCS MOSFET should permit MOSFET devices to be more successfully scaled at deep-submicrometer dimensions