Charge-coupled analog-to-digital converter

Reports on the experimental results of a 4-bit charge-coupled A/D converter which was proposed earlier by the authors, and has been implemented in a monolithic chip form. It was fabricated using p-channel CCD technology and has a die size of 4200 mil/SUP 2/. The typical operating frequency range was from 250 Hz to 100 kHz. A discussion is made on a layout technique to conserve the nominal binary ratio of (8:4:2:1) among the areas of four charge-measuring potential wells (M wells). The effect of `dump slot', which has been hypothesized as the cause of excessive nonlinearity (/spl ges/1/2 LSB) in the A/D conversion, is described. A novel input scheme called `slot zero insertion', which has been devised to circumvent the `dump slot' effect, is described.     

Optical-spectrum-encoded analog-to-digital converter

A novel optical-spectrum-encoded(OSE) analog-to-digital converter(ADC) is proposed in this letter. To simply exemplify the conversion idea,a 5-bit device structure consisted of Fabry-Perot interferometers(FPI) is analyzed and numerically simulated. The dependence of peak-transmission wavelength on modulation voltage in an electro-optical FPI and the dependence of transmitted power on incident light wavelength in an FPI are discussed and utilized to implement OSEADC. A linearly tunable mode-locked laser,as a voltage-wavelength transformer and a sampler,and chirped grating FPIs,as an encoder array,can be used to obtain much greater sampling rate and bit-resolution.     

事件驱动型的模数转换器设计

本文提出了一种适用于医疗信号处理的事件驱动型模数转换器(Level Crossing ADC)的电路,电路去掉了传统ADC固有的采样模块,采用1-bit DAC电路,低电源电压的架构.本设计采用SMIC 0.18μm CMOS工艺,电源电压为0.8V,单输入通道,在MATLAB的数据处理结果表明,整个电路共消耗功耗为0...     

逐次逼近（SAR）模数转换器进展

介绍了逐次逼近模数转换器（SAR－ADC）的原理结构和研究现状,主要对SAR－ADC 中的DAC、比较器、校准方法等主要模块进行了讨论。基于精度、速度、功耗的考虑,分别对SAR－ADC中的DAC结构进行分析比较,其多采用分段电容阵列或差分电容阵列。简述了比较器在功耗、速度、精度方面的结构调整。基于降低非理想效应,提高精度目的,对比分析了3种校准方法。为不同电路选择适当校准提供参考依据。最后总结了目前SAR－ADC的发展趋势。     

An electrooptic analog-to-digital converter

A new type of analog-to-digital converter, the basic element of which is an array of electrooptic waveguide modulators, is described. Higher conversion rates and simplicity are potential advantages in comparison with conventional electronic conversion techniques.     

An analog-to-digital converter with Golomb-Rice output codes

An analog-to-digital converter with data compression capabilities is described. By sharing circuits between an integrating converter and a Golomb-Rice encoder it is possible to jointly perform the tasks of quantization and coding. The Golomb-Rice codes are generated during the conversion cycle by employing a shift register and a digital multiplexer. The final codeword is read out serially from the shift register. The converter can also work in a noncompressing mode. This design provides a compact circuit suitable for on-sensor compression. Simulations at the system and transistor level corroborate the validity of the design.     

High-speed,high-resolution analog-to-digital converter with prediction

A fast analog method of input-signal prediction is proposed for predictive ADCs, which are noted for not using a sample-and-hold amplifier. The prediction method is implemented in a 100-MHz, 14-bit ADC to be manufactured by 0.25-μm process technology. A block diagram of the ADC is presented, together with a circuit diagram of the differentiator used in its analog relative prediction unit. The performance of the ADC is estimated with simulation tools from Cadence Design Systems.     

A time-based energy-efficient analog-to-digital converter

Dual-slope converters use time to perform analog-to-digital conversion but require 2/sup N+1/ clock cycles to achieve N bits of precision. We describe a novel current-mode algorithm that also uses time to perform analog-to-digital conversion but requires 5N clock cycles to achieve N bits of precision via a successive subranging technique. The algorithm requires one asynchronous comparator, two capacitors, one current source, and a state machine. Amplification of two is achieved without the use of an explicit amplifier by simply doing things twice in time. The use of alternating voltage-to-time and time-to-voltage conversions provides natural error cancellation of comparator offset and delay, 1/f noise, and switching charge-injection. The use of few components and an efficient mechanism for amplification and error cancellation allow for energy-efficient operation: in a 0.35-/spl mu/m implementation, we were able to achieve 12 bit of DNL limited precision or 11 bit of thermal noise-limited precision at a sampling frequency of 31.25 kHz with 75 /spl mu/W of total analog and digital power consumption. These numbers yield a thermal noise-limited energy efficiency of 1.17 pJ per quantization level, making it one of the most energy-efficient converters to date in the 10-12 bit precision range.     

A time coding analog-to-digital converter

An idea for a time-coding analog-to-digital converter using an exponential voltage sweep is presented. The technique inherently offers the possibility of convenient automatic recalibration in order to compensate for long-term drift. Thus, the converter is particularly well suited for on-line use in automatic digital data reduction systems. Attention is paid to the calibration and use of the converter. A design procedure is suggested and the obtainable accuracy evaluated in terms of the design parameters. Some comments are made concerning the merits of the scheme as compared with the most common existing systems.     

16-channel oversampled analog-to-digital converter

Oversampled analog-to-digital conversion has been demonstrated to be an effective technique for high resolution analog-to-digital (A/D) conversion that is tolerant to process imperfections. The area and power budget of conventionally designed oversampled analog-to-digital converters has precluded their application from areas where a large number of low frequency signals need to be converted simultaneously. A new oversampled A/D design methodology is proposed to cut the area and power budget per channel of an oversampled analog-to-digital converter. The design and implementation of a 16-channel oversampled analog-to-digital converter is presented which can be used as the core of the multichannel data acquisition system. The prototype achieved 80 dB of signal-to-noise-plus-distortion over 1 kHz, -80 dB of crosstalk and used less than 20 mW of power excluding clock generation     

A low-power reconfigurable analog-to-digital converter

A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta-sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phase-locked loop (PLL). This converter also incorporates several power-reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0-10 MHz over a resolution range of 6-16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta-sigma mode, it achieves a maximum signal-to-noise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of ±0.55 LSBs and ±0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with 24.6 mW of power     

A low-power 12-b analog-to-digital converter with on-chip precisiontrimming

The design and performance of a 12-b charge redistribution analog-to-digital converter (ADC) is described. The architecture is chosen to minimize power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a 1-μm CMOS process. It converts at a 200-kHz rate with a power dissipation of 10 mW     

A monolithic CMOS 20-b analog-to-digital converter

The authors present a monolithic 20-b analog-to-digital converter (ADC) based on an oversampling feedback architecture. The converter consists of a time-continuous integrator at the input, a pulsewidth modulator in the forward branch of the loop (corresponding to a 10-b ADC), and a 1-b DAC (digital-to-analog converter) to generate the feedback voltage. The digital evaluation is carried out with a uniformly weighted rectangular window filter. The circuit is implemented in a standard 2-μm CMOS n-well process and requires 14 mm² of silicon, including the pads. Measurement results are presented that demonstrate the feasibility of this architecture for 20-b accuracy. The complete circuit has a power consumption of 6.7 mW     

An optical analog-to-digital converter for bitwise coding

It is proposed an optical ADC for bitwise coding, which is applied for both electric and optic signals conversion to binary code. ADC operation speed is comparative with purely optic information processing devices.     

基于MATLAB的1.5位/级10位流水线结构模数转换器系统仿真

提出了利用MATLAB提供的SIMULINK工具箱，对1．5位／级10位流水线结构模数转换器系统进行仿真的新方法。用SIMULINK建立起每级的仿真模型，并将其封装成一个模块，然后把9级模块级联起来，建立起系统的模型。运行结果表明，该方法是可行的。     

V-I converter with high linearity and bandwidth

A transconductor circuit is presented in which the high linearity and bandwidth of the V-I conversion is achieved by means of a highly linear, low-gain current-mode feedback loop. While a spurious free dynamic range of /spl sim/88 dB can be achieved in a bandpass application centred at 100 MHz, the noise integrated from the 95-105 MHz band limits the signal-to-noise ratio to /spl sim/70 B.     

Delta-sigma modulator of the analog-to-digital converter with ternary data encoding

The results of the development of the delta-sigma modulator of the analog-to-digital converter with ternary data encoding are presented in the paper. The oversampling ratio is 54; the clock frequency selected is 100 MHz. The suggested circuit engineering solutions are designed for manufacturing using the standard 0.18 μmMOS technology and bipolar power of ±0.9 V. Circuit performance capability is confirmed by the simulation results.     

The algorithmic model of a pipelined analog-to-digital converter

The results of using an algorithmic macromodel of an analog-to-digital converter (ADC) of the pipelined type during the development of intellectual-property blocks for analog-to-digital conversion are presented. The results of calculations are presented.     

Time-bandwidth product of the photonic time-stretched analog-to-digital converter

The time-bandwidth product of the photonic time-stretched system is modeled in terms of physical system parameters. Using the time-bandwidth product as figure-of-merit, the performances of optical double-sideband and single-sideband (SSB) intensity modulation are compared, and optical SSB intensity modulation is identified as a potential solution to extend the system's time-bandwidth product. An SSB-modulated time-stretched system is theoretically analyzed and experimentally demonstrated. As an important practical consideration, the analytical model relating the system performance to the phase and amplitude mismatches in the SSB modulator is presented. The results show that the system is tolerant to such unavoidable mismatches. Experiments using commercially available components suggest that the dispersion-induced power penalty can be kept below 2.5 dB over 4 - 20 GHz bandwidth for any stretch factor. Additional experiments demonstrating 120-GSamples/s real-time digitization of a 20-GHz SSB-modulated signal are also reported.     

An 8-bit 100-MHz full-Nyquist analog-to-digital converter

An 8-bit 100-MHz full-Nyquist analog-to-digital (A/D) converter using a folding and interpolation architecture is presented. In a folding system a multiple use of comparator stages is implemented. A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. However, every quantization level requires a folding stage, thus no reduction in input circuitry is found. Interpolation between the outputs of the folding stages generates additional folding signals without the need for input stages. A reduction in input circuitry equal to the number of interpolations is obtained. The converter is implemented in an oxide-isolated bipolar process, requiring 800 mW from a single 5.2-V supply. A high-level model describing distortion caused by timing errors is presented. Considering clock timing accuracies needed to obtain the speed requirement, this distortion is thought to be the main speed limitation