Photosensitivity n-channel ZnO phototransistor for optoelectronic applications: Modeling of ZnO TFT

The zinc oxide semiconductor thin film transistor was fabricated on a SiO₂/Si substrate by sol gel method. The ZnO film is consisted of nanofibers with the changing diameter along the fibers. Electrical characteristics of the zinc oxide transistor under dark and white light illuminations were analyzed. The mobility value of the ZnO TFT was found to be 1.86 × 10⁻² cm²/V s. The ZnO thin film transistor works in an n-channel operational mode because the drain current increases with the positive gate voltages. A significant increase in the drain current of ZnO TFT is observed with a maximum photosensitivity of 100 under visible light illumination. It is concluded that the ZnO thin film transistor can be used in visible photo-detecting device applications.     

Growth and fabrication of AlGaN/GaN HEMT based on Si(1 1 1) substrates by MOCVD

AlGaN/GaN high electron mobility transistor (HEMT) hetero-structures were grown on the 2-in Si (1 1 1) substrate using metal-organic chemical vapor deposition (MOCVD). Low-temperature (LT) AlN layers were inserted to relieve the tension stress during the growth of GaN epilayers. The grown AlGaN/GaN HEMT samples exhibited a maximum crack-free area of 8 mm×5 mm, XRD GaN (0 0 0 2) full-width at half-maximum (FWHM) of 661 arcsec and surface roughness of 0.377 nm. The device with a gate length of 1.4 μm and a gate width of 60 μm demonstrated maximum drain current density of 304 mA/mm, transconductance of 124 mS/mm and reverse gate leakage current of 0.76 μA/mm at the gate voltage of −10 V.     

Chemisorption sensing and analysis using silicon cantilever sensor based on n-type metal-oxide-semiconductor transistor

This paper presents a silicon cantilever sensor based on n-type metal-oxide-semiconductor transistor for chemical sensing and analysis using the chemisorption-induced surface stress sensing principle. The cantilever is along the 〈1 0 0〉 crystal orientation of the (1 0 0) silicon, and the transistor channel is parallel to as well as located at the rear part of the cantilever to obtain high stress sensitivity. The gold film deposited on the bottom surfaces of cantilevers is chemically functionalized with a self-assembled monolayer of 4-mercaptobenzoic acid via the Au-SH covalent bonding. The vapor phase chemical sensing experiments with acetone, ethanol, nitroethane and water vapor as targets are performed. The observed response differentiation implies that the molecular interaction mechanisms between different chemical molecules are different.     

Electrical transport properties in electroless-etched Si nanowire field-effect transistors

We report the electrical transport of the Si nanowires in a field-effect transistor (FET) configuration, which were synthesized from B-doped p-type Si(1 1 1) wafer by an aqueous electroless etching method based on the galvanic displacement of Si by the reduction of Ag⁺ ions on the wafer surface. The FET performance of the as-synthesized Si nanowires was investigated and compared with Ag-nanoparticles-removed Si nanowires. In addition, high-k HfO₂ gate dielectric was applied to the Si nanowires FETs, leading to the enhanced performance such as higher drain current and lower subthreshold swing.     

The Effects of Mechanical Uniaxial Stress on Junction Leakage in Nanoscale CMOSFETs

This paper reports the influences of uniaxial mechanical stress on the reverse-biased source/drain to substrate junction leakage of state-of-the-art 65 nm CMOS transistors. For n-channel metal-oxide-semiconductor (NMOS) transistors, the band-to-band tunneling (BTBT) dominates the junction leakage current due to heavily doped junction and pocket implants. However, for p-channel metal-oxide-semiconductor (PMOS) transistors with embedded SiGe source/drain, the leakage current is found to result from both BTBT and generation current due to defects generated in the SiGe layer and at the SiGe/Si interface. A four-point bending technique is used to apply mechanical uniaxial stress on NMOS and PMOS devices along the longitudinal direction. It was found that the leakage current of both devices increases (decreases) with applied uniaxial compressive (tensile) stress, and that the strain sensitivity of the junction leakage of NMOS transistors is much weaker than that of PMOS transistors. By combining the bending technique with process strained Si (PSS) technology, additional stress was applied to NMOS and PMOS with high built-in stress to investigate the characteristics of junction leakage under extremely high uniaxial stress. It is shown that uniaxial tensile stress can both enhance the NMOS device performance and decrease the junction leakage. However, for the PMOS, there exists a tradeoff between boosting the transistor performance and decreasing the junction leakage current, so there is a limit in the amount of compressive stress that can be beneficially applied.     

Characterization of GeSn materials for future Ge pMOSFETs source/drain stressors

In order to outperform current uniaxial compressively strained Silicon channel pMOSFET technology (with embedded SiGe source/drain), switching to strained Ge channel is mandatory. GeSn materials, having larger lattice parameter than Ge, are proposed in this article as embedded source/drain stressors for Ge channels. Our simulation results indicate that a minimum of 5% Sn is required in the GeSn source/drain to build a competitive strained Ge pMOSFETs with respect to strained Si channels. Therefore the compatibility of GeSn (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation and NiGeSn formation) has been studied. A low thermal budget has been determined for those processes on GeSn alloys: temperatures must be lower than 600 °C for B activation and lower than 450 °C for NiGeSn formation.     

Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers

A comprehensive quantum anisotropic transport model for holes was used to study silicon PMOS inversion layer transport under arbitrary stress. The anisotropic band structures of bulk silicon and silicon under field confinement as a twodimensional quantum gas are computed using the pseudopotential method and a six-band stress-dependent k.p Hamiltonian. Anisotropic scattering is included in the momentum-dependent scattering rate calculation. Mobility is obtained from the Kubo–Greenwood formula at low lateral field and from the fullband Monte Carlo simulation at high lateral field. Using these methods, a comprehensive study has been performed for both uniaxial and biaxial stresses. The results are compared with device bending data and piezoresistance data for uniaxial stress, and device data from strained Si channel on relaxed SiGe substrate devices for biaxial tensile stress. All comparisons show a very good agreement with simulation. It is found that the hole band structure is dominated by 12 “wings,” where mechanical stress, as well as the vertical field under certain stress conditions, can alter the energies of the few lowest hole subbands, changing the transport effective mass, density-of-states, and scattering rates, and thus affecting the mobility.     

Sensitivity enhancement of a flexible MEMS strain sensor by a field effect transistor in an all organic approach

We report a low-cost piezoresistive nanocomposite based organic micro electro mechanical system (MEMS) strain sensor that has been combined to an organic field effect transistor (OFET) with the objective of amplifying the sensitivity of the sensor. When the MEMS cantilever is strained by a mechanical deflection, the resulting variation of resistivity influences the gate voltage (V_GS) of the OFET and, hence, changes the drain current (I_DS) of the transistor. The present combination allows an enhancement of sensitivity to strain by a factor 3.7, compared to the direct detection of resistance changes of the nanocomposite. As a consequence, a low limit of detection of 24 ppm has been estimated in terms of strain transduction efficiency. Furthermore, the organic microsystem exhibits a short response time and operates reversibly with an excellent robustness.     

High performance submicrometer pentacene-based organic thin-film transistor using planar bottom-contact structure

This paper presents a pentacene-based organic thin-film transistor (OTFT) with a submicrometer channel length of 0.5 μm that uses a planar bottom-contact (pBC) structure to achieve high electrical performance. The performance of the submicrometer OTFT is dominantly influenced by the growth continuity of pentacene near the edge of the source/drain (S/D). The pBC structure with a bilayer dielectric can provide a continuous plane for improving the growth continuity and quality of pentacene near the edge of the S/D. This results in high electrical performance for the submicrometer OTFT with pBC structure, such as a mobility of 0.14 cm²/V s and an on/off current ratio of 1.9 × 10⁵.     

Potential of low-voltage organic transistors with high on-state drain current for temperature sensor development

Organic transistors with high on-state drain current at gate and drain voltages of −2 V fabricated on polyethylene naphthalate foils were investigated for sensor development. Two aspects were studied: (a) the ability of such transistors to raise the sensitivity of a temperature sensor and (b) the bias stress stability of the transistors subjected to square voltage pulses that turned them on and off repeatedly. To demonstrate the first aspect, the voltage-amplifying ability of the organic transistor was used to increase the response to the temperature, ordinarily achieved with a thermistor. To achieve voltage amplification, the transistor must have on-state drain current of at least 20 μA at gate and drain voltages of −2 V. Two transistors with on-state drain current of ~60 and ~120 μA were tested, leading to voltage gain of −2.8 and −4.9 V/V, respectively, thus increasing the sensitivity of the temperature sensor by a factor of up to 5. To study the second aspect, the same square voltage pulses were concurrently applied to the gate and drain electrodes, causing the transistor to turn on and off repeatedly. The turn-on and turn-off voltages were −2 and 0 V respectively and four different pulse periods were used: T of 5, 20, 40 and 60 s. For each T, 1000 pulses with turn-on time of 1 s and varying turn-off times were applied to the transistors, leading to the aggregate net stress time of 1000 s in all cases. The changes in the on-state drain current, threshold voltage, and field-effect mobility depended on T, in spite of the net stress time being the same. The reduction in the on-state drain current did not exceed 17%, stabilization was also observed after about 500 cycles in some cases, and the maximum drop occurred for medium T, thus making T = 60 s a favorable condition for sensor operation.     

Effect of H2O evolving from TEOS based SiO2 film on the EEPROM cell characteristic

In this paper, we investigate the effect of water (H₂O) molecules evolving from silicon dioxide (SiO₂) film deposited by low pressure chemical vapor deposition (LPCVD) at 670 °C on the transistor characteristic of an electrically erasable programmable read only memory (EEPROM) cell. Fourier Transform Infra red (FT-IR) analysis reveals that H₂O is captured during film deposition and diffused to silicon surface during high thermal processing. The diffused H₂O molecules lower threshold voltage (V_t) of cell transistor and, thus, leakage current of the cell transistor is increased. In erased cell, V_t lowering is 0.25 V in which it increases leakage current of cell transistor from 1 to 100 pA. This results in the lowering of high voltage margin of a 512 Kb EEPROM from 2.8 to 2.6 V at 85 °C.     

Evaluation of gate oxide breakdown effect on cascode class E power amplifier performance

A CMOS cascode class E power amplifier has been designed at 5.2 GHz. Its RF performances such as output and power-added efficiency have been examined in ADS simulation. The layout parasitic is accounted for in the post-layout simulation. Time-dependent drain-source voltage waveforms indicate that the drain of cascode transistor is subject to much higher voltage stress than that of main transistor. Analytical equation of output power including impact of gate-oxide breakdown is developed and compared with RF simulation results. Good agreement between the model predictions and ADS simulation is obtained. The gate-drain breakdown of the cascode transistor decreases the output power and power-added efficiency of the power amplifier significantly when the breakdown resistance is below 1 kΩ.     

延续摩尔定律的新材料——应变Si

介绍了应变Si材料的需求背景和必要性.阐述了在MOS器件中使用衬底致双轴应变后器件性能的改善,在总结了与工艺致单轴应变相比衬底致双轴应变的不足以及工艺致单轴应变的优势之后,讲述了基于SiGe源漏和基于双应力线的两种工艺致单轴应变技术及其对MOS器件性能的提高.简单介绍了国际上近年来对应变Si材料与器件的研究发展状况和应变Si技术达到的各种水平,以及国内对应变Si的研究状况,并对应变Si技术的使用优势和应用前景做了简单分析.     

Evaluation of electron irradiated embedded SiGe source/drain diodes by Raman spectroscopy

The stress evolution of Si_0.75Ge_0.25 layers for Si_0.75Ge_0.25 source/drain (S/D) diodes, which have been irradiated at room temperature with 2-MeV electrons, is investigated using Raman spectroscopy measurements. According to Raman results for Si_0.75Ge_0.25/Si hetero-structures before and after irradiation, tensile stress was induced in the silicon substrate under the Si_0.75Ge_0.25 layer. Before irradiation, the range of tensile stress estimated by the peak shift of the Raman spectrum was −110 to −10 MPa for several measurement patterns. After irradiation, the tensile stress was relaxed in all measurement patterns though the compressive stress status in the Si_0.75Ge_0.25 layer was not changed. The stress relaxation in the silicon substrate amounted to about 10 MPa as a maximum. The influence of the irradiation on the stress relaxation in the silicon substrate, could be explained because the electron irradiation at 2-MeV can easily penetrate through the studied 140 nm Si_0.75Ge_0.25 layers.     

Influence of γ-ray total dose radiation effect on the hot carrier gate current of the uniaxial strained Si nano-scale NMOSFET

The carrier microscopic transport process of uniaxial strained Si n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) has been analyzed under γ-ray radiation. The variation of oxide-trapped charge (N_ot) and interface-trap charge (N_it) with the total dose has also been investigated. An analytical model of hot carrier gate current of the uniaxial strained Si nanometer scale NMOSFET has been developed with the degradation due to the total dose irradiation taken into consideration. Based on the model, numerical simulation has been carried out by Matlab. The influence of the total dose, geometry and physics parameters on gate current was simulated. Furthermore, to evaluate the validity of the model, the simulation results were compared with experimental data, and good agreements were confirmed. Thus, the proposed model provides good reference for research on irradiation reliability and application of strained integrated circuit of uniaxial strained Si nanometer scale n-channel metal-oxide-semiconductor field-effect transistor.     

A novel field effect transistor with dielectric polymer gel

A novel organic-field effect transistor (OFET) has been fabricated. This device is original in the sense that it can be produced in ambient conditions with facile and cost-effective methods. Experimental results surprisingly revealed a high mobility value at the order of 0.38 cm²/Vs, and the gate voltage is also found to be lower than 1 V. The device exhibited excellent transistor characteristics at low voltages. Threshold voltage is around 0.26 V with 10³ on/off ratio. The device design is based on high effective capacitance value of a polymer gel, 1 μF, which is sandwiched between glass substrates on which source and drain electrodes were constructed.     

Investigation of high-performance sub-50 nm junctionless nanowire transistors

The performances of the junctionless nanowire transistor (JNT) are evaluated under high-performance (HP) ITRS device technical requirements for the 25 nm technology node. The electrical characteristics of the devices are obtained from numerical simulations. The threshold voltage of JNT can be easily adjusted by changing different variable parameters such as fin width, fin thickness, doping concentration, gate oxide thickness and gate work function. The variation of threshold voltage with physical parameters is analyzed. The current drive is controlled by doping concentration and nanowire size. For gate length down to 25 nm, a 30-40% increase in drain current is also reported by using a fin aspect ratio of 2 instead of 1. Additional source and drain implantation can be applied to improve the current drive.     

A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-/spl mu/m single-gate low-power SRAM device

A new double offset-implanted (DOI) technology, which can effectively suppress the gate-induced drain-leakage (GIDL) current of buried-channel PMOS transistor in small-size CMOS devices, is proposed and developed with a 0.12-/spl mu/m single-gate low-power SRAM device. The DOI scheme is characterized by the usage of the silicon nitride etch-stopper for the formation of borderless W-contact as offset spacer without supplementing auxiliary processes at p+ source/drain (S/D) implantation process after the n+ S/D one. It is assured that the DOI technology makes the gate-to-S/D overlap controllable, so that the GIDL current of PMOS transistor can remarkably be reduced. Furthermore, the enhancement of CMOS transistor performance was possible by reducing the sidewall reoxidation thickness of the gate-poly Si and optimizing the implantation conditions with this technology.     

Temperature behavior and modeling of ohmic contacts to Si implanted n-type GaN

The behavior of an ohmic contact to an implanted Si GaN n-well in the temperature range of 25-300 °C has been investigated. This is the sort of contact one would expect in many GaN based devices such as (source/drain) in a metal-oxide-semiconductor transistor. A low resistivity ohmic contact was achieved using the metal combination of Ti (350 Å)/Al (1150 Å) on a protected (SiO₂ cap) and unprotected samples during the post implantation annealing. Sheet resistance of the implanted layer and metal-semiconductor contact resistance to N⁺ GaN have been extracted at different temperatures. Both, the experimental sheet resistance and the contact resistance decrease with the temperature and their characteristics are fitted by means of physical based models.     

Control of threshold voltage and improved subthreshold swing in enhancement-mode InGaP/InGaAs metal-oxide-semiconductor pseudomorphic high-electron-mobility transistor

The InGaP/InGaAs metal-oxide-semiconductor pseudomorphic high-electron-mobility transistor (MOS-PHEMT) with an oxidized GaAs gate by liquid phase oxidation (LPO) is demonstrated. With the help of the LPO, the threshold voltage (V_th) can be shifted positively to 0.07 V, and enhancement-mode MOS-PHEMT is fabricated. The device with a gate metal of 1 × 100 μm² shows a maximum transconductance of 171 mS/mm at V_DS = 5 V and a maximum drain current density of 182 mA/mm at V_GS = 2 V. It also exhibits a lower leakage current and an improved subthreshold swing compared to the referenced Schottky-gate InGaP/InGaAs PHEMT.