尘埃粒子计数器全粒径范围内计数效率的校准

为实现对尘埃粒子计数器全粒径范围内的计数效率校准,分别对尘埃粒子计数器(OPC)-凝结核粒子计数器(CPC)-气溶胶静电计(FCAE)的逐级溯源方法和光学显微镜计数方法进行技术研究,建立一套完整的校准方法和装置。结果表明:装置具有很好的溯源性,能保证国内关于尘埃粒子计数器计数效率的计量技术的准确性。     

瞬态波形记录仪中计数器的CPLD实现

本文介绍了采用CPLD实现瞬态波形记录仪计数器的三种方法由74系列的芯片构成原理图;由LPM库元件设计;采用VHDL(超高速集成电路硬件描述语言)进行计数器的设计.文中给出了前两种方法设计的计数器及仿真图形.经实际检验采用CPLD实现的计数器具有功能强大,易修改,抗干扰性强等优点.     

尘埃粒子计数器溯源过程中稀释控制系统的研究

目前被广泛认可的尘埃粒子计数量值溯源方法为:"尘埃粒子计数器(OPC)-凝结核粒子计数器(CPC)-气溶胶静电计(FCE)"的逐级溯源。在溯源过程中,不同型号尘埃粒子计数器和凝结核粒子计数器之间存在粒子测量浓度、流量之间不匹配等差异。本文通过介绍一套具有温度测量、气溶胶稀释、气体流量测量与控制等系统硬件电路,满足粒子计数器的溯源问题。     

动态光散射中基于光子计数率的噪声剔除方法

提出一种基于光子计数率的噪声剔除方法消除大颗粒的影响,通过监测每秒的光子计数,若某1s的光子计数明显高于之前5s光子计数的均值,则将这1s的光子计数剔除。分别在20、30、40°散射角度对测量介质为水、标称直径为21.3nm的金颗粒和90nm的标准颗粒进行测试。结果表明:该方法能有效剔除跳变较大的光子计数率,剔除噪声后的有效粒径和分散度都比较稳定,且接近标称值。     

试述计数板的抗干扰设计

8253可编程计数/定时器,有三个计数器是独立的16位减法计数器。计数器在编程写入初始值后,在某些方式下计数到0后自动预置,计数器连续工作。本文从硬件方面介绍了以8253可编程计数/定时器芯片设计的控制板,作为单晶炉等径生长控制系统中晶体生长的主要控制部件,在抗干扰设计方面所采取的技术。     

识别在用电能表的作弊手段及防范措施

一、各种作弊手段1．故意使计数装置停转。作弊者将在用电能表的计数器装置稍稍往外移出Inun，使齿轮与圆盘蜗杆脱离，用电时圆盘转动正常，计数器不计数。2．擅自更换计数器。有的将2（4）安培，常数为3op转／I瓦时电能表的计数装EE］＆成5（l）安培，常数为1200转／T瓦时的计数装置，可少计数近3／5以上。一般采用较高转数的计数器换成较低转数。3．调换电流线圈，将匝数多、铜丝细的电流线圈换成匝数少铜线粗的。有的将2（4）安培的电能表线圈调换成10（20安培电能表的电流线圈，使电能表慢转。4．调整计数器的累计计数机构。有的管电…     

凝结核粒子计数器的校准研究

<正>多年来,尘埃粒子计数器的校准一直是国际计量研究机构关注的重点。目前,被广泛认可的尘埃粒子计数量值溯源和校准方法为:"尘埃粒子计数器(OPC)——凝结核粒子计数器(Condensation particle counter,CPC)——气溶胶静电计(Faraday cup electrometer,FCE)"的逐级溯源方法。在该溯源链中通过凝结核粒子计数器将尘埃粒子计数器的测量结果溯源至气溶胶静电计,而气溶胶静电计通过测量带电颗粒所形成的电流得到粒子数量,最终使得测量值溯源     

高温气冷堆燃料装卸系统计数器电路改进设计

对10MW高温气冷堆(HTR-10)燃料装卸计数系统中采用涡流传感原理设计的原有计数器进行了优化--将原来的恒压源激励改进为恒流源激励,并且激励源的幅值和频率均变为可调,以提高系统的性能.对改进电路的实验电路板进行了在线实验,实验表明,改进的计数器计数准确,充分适应现场情况的复杂性,并增加了传感器的灵敏度,提高了系统的可靠性.     

燃气表电信号采样同步问题的研究

燃气表电子计量是指在表的某一周期运动部件上安装传感器,表在通过固定体积的气量时产生一个脉冲信号,再由单片机进行计数和数据处理。电子计量的特点是以基表为标准器,计量结果与机械计数器比对,因此要求在表的额定流量范围内电子计量必须与计数器同步。目前在国内,主流的采样技术是计数器采样和机芯采样。“机芯采样+软件修正误差技术”已经解决了不同步的问题,本文不作探讨。大部分IC卡和远传表采用的技术是在基表机械计数器上加装传感元件,随着计数器旋转而产生计数脉冲。IC卡表是由附属电路进行计数和数据处理,远传表则是将这个信号…     

电子计数器在火工品生产中的应用

在火工品生产中,经常要对产品进行计数,以便进行分装和统计产量。自动记数的方式大致可以分为机械式和电子式两类。机械式计数器简单直观,容易掌握,抗干扰。但是体积较大,有噪音,不容易和自动定量仪、计算机等装置接口。此外,易产生火花,不利于火工品安全生产。电子计数器却具有体积小、无噪音、易于和其它装置接口等优点,在生产中正日益广泛地被采用。电子计数器是由一些二极管、三极管和其他电子器件组成的计数系统。按其采样、转换、显示方式的不同,可以组合成多种型式的计数器。由于计数显示器已有多种定型产品,计数装置的设计,重点在于设计计数传感器。     

Magnetic bubble counting circuits

A new group of magnetic circuits that can count the number of magnetic bubbles and display them in any binary, ternary, ..., decimal basis is proposed. Feasibility of the concept was demonstrated by successful operation of a binary counter circuit. A design of a decimal counter is given.     

Digital Frequency Multiplier for Spectrum Measurement of Periodic Signals

Frequency multipliers find applications in the Fourier and Walsh spectrum measurements of periodic signals. Earlier digital frequency multipliers use two counters: 1) An upcounter which is partitioned into a fractional counter of kbits in cascade with an integral counter. This determines the period of the input signal by the number of clock pulses that are accumulated in a period of the signal. 2) A downcounter which is next fed from the same clock, and which is periodically preset to the contents of the integral counter whenever the downcounter reaches zero. In this process an error is introduced in the output frequency because the fractional counter contents are ignored in the frequency multiplication phase. To minimize this error, a high clock frequency is required so that the fractional count is small compared with the integral count. The maximum output pulse frequency is limited by the speed of the counters used. A new method is described which also uses the contents of the fractional counter. The clock frequency is reduced substantially and the maximum output pulse frequency is limited by the settling time of a D/A converter: If the settling time is 200 ns, the maximum output frequency is ten times that of earlier methods.     

Counting losses due to saturation effects of scintillation counters at high count rates

The counting statistics of a scintillation counter, with a preamplifier saturated by an overloading input, are investigated. First, the formulae for the variance and the mean number of counts, accumulated within a given gating time, are derived by considering counting-loss effects originating from the saturation and a finite resolving time of the electronic circuit. Numerical examples based on the formulae indicate that the saturation makes a positive contribution to the variance-to-mean ratio and that the contribution increases with count rate. Next the ratios are measured under high count rates when the preamplifier saturation can be observed. By fitting the present formula to the measured data, the counting-loss parameters can be evaluated. Corrections based on the parameters are made for various count rates measured in a nuclear reactor. As a result of the corrections, the linearity between count rate and reactor power can be restored.     

A Potentiometric Transducer for the Measurement of Very Low Speeds

A simple circuit for the measurement of very low angular speeds is described. It uses a potentiometric transducer along with a modified astable multivibrator. Using an up-down counter the speed measured can also be displayed.     

高速电路中的信号完整性及仿真

在高速印刷电路板设计过程中,高速电路设计的仿真显示出越来越重要的地位。利用仿真分析的方法,可以在PCB制作之前尽可能发现并解决隐藏的信号完整性和电磁兼容性问题,最大限度地减小产品设计失败概率,提高电路系统工作可靠性。通过采用PADS2004／hyperLynx软件对一高速DSP图像处理印刷电路板中的高速信号线的布局布线前的仿真,分析高速电路板中普遍存在的信号完整性、串扰等问题,并给出了相应的解决办法。     

多传感器数据融合技术在水泥袋计数器中的应用设计

针对当前水泥袋计数器计数误差较大的问题,设计了一套基于多传感器数据融合技术的水泥袋计数系统。系统采用光电开关传感器感知水泥袋的有无,用倾角传感器确定水泥袋是否叠袋,用光电编码器测量传输带实时速度来确定是否连袋,用单片机对采集到的3种传感器信息集中进行数字智能化处理,可精确计算经过传送带的水泥袋的数量。实验结果表明,该计数器系统运行稳定可靠,具有一定的推广价值。     

High-resolution of rotary encoder analog quadrature signals

The paper describes a software technique to provide high-resolution absolute angular measurements from the analog quadrature signals of a rotary encoder. The method uses digitized samples of the sinusoidal quadrature signals and the output of a divide-by-four counter circuit. Dynamic measurements on an external trigger signal are possible allowing instantaneous up-to-date angular readings even at high speed. The resolution and hysteresis errors are only dependent on the encoder itself and the bandwidth and resolution of the sampling circuitry. The scheme allows up to 135 degrees of counter hysteresis and delay without loss of precision, thus also affording excellent noise immunity. The theoretical resolution for a 12-bit digital conversion of the analog signals is 1/3360 of a pitch. Experimental results on an encoder built into a laser-tracking measurement system and using 81000 pitches show a unidirectional precision of 0.3 arcsec (rms), a mean bidirectional hysteresis of about 1 arcsec and a worst case variation for a stationary encoder shaft of 0.06 arcsec     

基于 CPLD 的水中主动声探测仪计数检波器设计

从提高水中主动声探测仪检波器的工作性能角度出发, 提出了一种能够克服传统二极管包络检波器缺点的计数检波器, 通过在 1 ms 时间内统计输入信号的脉冲个数, 来区分干扰脉冲和回波信号. 在 Xilinx foundation series3.1 软件平台上, 采用 VHDL(超高速硬件描述语言)和自顶向下的方法, 完成了基于 CPLD(可编程逻辑器件)的计数检波器设计, 并进行了逻辑仿真和水下静态试验. 结果表明, 基于 CPLD 的计数检波器设计功能正确, 具有一定的柔性和可升级性;起到检波和滤波的双重作用, 提高了电路的抗干扰能力;并且通过在整形电路中增加限幅放大器, 可以进一步提高计数检波器的性能.     

Anthocyanin-sensitized solar cells using carbon nanotube films as counter electrodes

Carbon nanotube (CNT) films have been used as counter electrodes in natural dye-sensitized (anthocyanin-sensitized) solar cells to improve the cell performance. Compared with conventional cells using natural dye electrolytes and platinum as the counter electrodes, cells with a single-walled nanotube (SWNT) film counter electrode show comparable conversion efficiency, which is attributed to the increase in short circuit current density due to the high conductivity of the SWNT film.     

Estimation and Analysis of Novel Dynamic Body Biased TSPC Design Technique

This paper targets to present energy efficient high speed true single phase clock dynamic circuit design technique, utilizing a novel body biasing tuner. The threshold voltage is controlled dynamically by dint of a novel body bias tuner so that performance of the circuit is enhanced in terms of power, delay, temperature, voltage, noise and corner variations. Power consumption and delay is computed and analysed for wide range of temperature and 40.78–95.5% saving in power delay product is obtained with the same. Quantification of bias voltage variation effect and process corners to find the effectiveness of the proposed design are examined and it is found to be performing consistently as compared with other techniques. Later on bouncing noise analysis is done for the valuation of noise in the circuit. Comparison of power delay product, transistor count and clock phase is done with several previously reported designs. Comprehensive simulation in cadence using 90 nm technology, shows that the proposed design vanquish conventional and other previously reported dynamic circuit design techniques in all aspect of circuit performance. Further, an arithmetic logic unit for measurement using sensors is implemented as a prolongation of the proposed dynamic circuit design technique.