Reactive Ion Etching of ITO Transparent Electrode of TFT—AMLCD in Ar／CF4 Plasma

Ｔhe pattern of ITO transparent electrode of pixel cells in TFTAMLCD is a critical step in the manufacturing process of flat panel display devices,the development of suitable plasma reactive ion etching is necessary to achieve high resolution display.In this work we investigated the Ar/CF4 plasma etching of ITO as function of different parameters.We demonstrated the ability of this plasma to etch ITO and achieved an etching rate of about 3.73nm/min,which is expected to increase for long pumping down period,and also through addition of hydrogen in the plasma.Furthermore we described the ITO etching mechanism in Ar/CF4 plasma.The investigation of selectivity showed to be very low over silicon nitride and silicon dioxide but very high over aluminum.     

Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor devices

A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl₃-based plasmas are applied to etch the TaN metal gate and find that BCl₃/Cl₂/O₂/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl₂ almost has no selectivity to Si substrate, BCl₃/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl₃/Cl₂/O₂/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.     

High-quality conformal silicon oxide films prepared by multi-step sputtering PECVD and chemical mechanical polishing

High-quality conformal oxide films were obtained by using multi-step sputtering (MSSP) plasma enhanced chemical vapor deposition (PECVD) process with argon ion sputtering and chemical mechanical polishing (CMP). The repeated deposition by plasma enhanced chemical vapor deposition (PECVD) and anisotropic etching of oxide films by multi-step sputtering PECVD improve the step coverage and gap filling capability significantly. The argon plasma treatment enhances the binding energy of Si-O in the SiO₂ network, and the temperature dependence of stress for MSSP oxide film showed no hysteresis after the heating cycle up to 440 °C. The stress-temperature slope of MSSP oxide film was found to be much less than that of conventional PECVD oxide film. The slope for 1.1 μm thick film is about 5.8×10⁵ dynes/cm²/°C which is smaller than that of thermally grown oxide film. It seems that MSSP oxide film reduces stress-temperature hysteresis and becomes more dense and void-free in the narrow gaps with inter-metal spacing of 0.5 μm. After filling of the narrow gap, we adopted the CMP process for global planarization and obtained good planarization performance. The uniformity of the film thickness was about 4% and the degree of the planarization was over 95% after CMP process.     

A Photoluminescence Study of Plasma Reactive Ion Etching-Induced Damage in GaN

Ga N films with reactive ion etching(RIE) induced damage were analyzed using photoluminescence(PL).We observed band-edge as well as donor-acceptor peaks with associated phonon replicas,all in agreement with previous studies.While both the control and damaged samples have their band-edge peak location change with temperature following the Varshni formula,its intensity however decreases with damage while the D–A peak increases considerably.Nitrogen post-etch plasma was shown to improve the band edge peak and decrease the D–A peak.This suggests that the N2 plasma has helped reduce the number of trapped carriers that were participating in the D–A transition and made the D°X transition more active,which reaffirms the N2post-etch plasma treatment as a good technique to heal the Ga N surface,most likely by filling the nitrogen vacancies previously created by etch damage.     

用于非易失性相变存储器中Si2Sb2Te5在CF4/Ar等离子体下的反应离子刻蚀

Phase change random access memory（PCRAM） is one of the best candidates for next generation nonvolatile memory,and phase change Si₂Sb₂Te₅ material is expected to be a promising material for PCRAM.In the fabrication of phase change random access memories,the etching process is a critical step.In this paper,the etching characteristics of Si₂Sb₂Te₅ films were studied with a CF₄/Ar gas mixture using a reactive ion etching system.We observed a monotonic decrease in etch rate with decreasing CF4 concentration,meanwhile,Ar concentration went up and smoother etched surfaces were obtained.It proves that CF4 determines the etch rate while Ar plays an important role in defining the smoothness of the etched surface and sidewall edge acuity.Compared with Ge₂Sb₂Te₅, it is found that Si₂Sb₂Te₅ has a greater etch rate.Etching characteristics of Si₂Sb₂Te₅ as a function of power and pressure were also studied.The smoothest surfaces and most vertical sidewalls were achieved using a CF₄/Ar gas mixture ratio of 10/40,a background pressure of 40 mTorr,and power of 200 W.     

Reactive Ion Etching of GaAs, GaSb, InP and InAs in Cl2／Ar Plasma

Reactive ion etching characteristics of GaAs,GaSb,InP and InAs using Cl_2/Ar plasma have been investigated,it is that,etching rates and etching profiles as functions of etching time,gas flow ratio and RF power.Etch rates of above 0.45 μm/min and 1.2 μm/min have been obtained in etching of GaAs and GaSb respectively, while very slow etch rates (<40 nm/min) were observed in etching of In-containing materials,which were linearly increased with the applied RF power.Etched surfaces have remained smooth over a wide range of plasma conditions in the etching of GaAs,InP and InAs,however,were partly blackened in etching of GaSb due to a rough appearance.     

Annealing before gate metal deposition related noise performance in AIGaN/GaN HEMTs

For a further improvement of the noise performance in A1GaN/GaN HEMTs, reducing the relatively high gate leakage current is a key issue. In this paper, an experiment was carried out to demonstrate that one method during the device fabrication process can lower the noise. Two samples were treated differently after gate recess etching： one sample was annealed before metal deposition and the other sample was left as it is. From a comparison of their Ig-Vg characteristics, a conclusion could be drawn that the annealing can effectively reduce the gate leakage current. The etching plasma-induced damage removal or reduction after annealing is considered to be the main factor responsible for it. Evidence is given to prove that annealing can increase the Schottky barrier height. A noise model was used to verify that the annealing of the gate recess before the metal deposition is really effective to improve the noise performance of AIGaN/GaN HEMTs.     

Optimization of dry etch process conditions for HgCdTe detector arrays

A key technology required for fabricating single and multi-band mesa photodiodes with pixel sizes less than or equal to 25 μm is the development of an anisotropic etch process for HgCdTe. The primary approach investigated for this purpose has been electron cyclotron resonance (ECR) dry etching. This paper reviews an experiment used to optimize the ECR etch process at Lockheed Martin IR Imaging Systems, Inc. and then the use of the process to produce state-of-the-art LW photodiodes. In this work, a Ar:H plasma was used in a Plasma Therm series 700 ECR plasma etcher. Reactor variables were optimized by a designed experiment against the following response parameters: anisotropy, etch uniformity and “damage,” as measured by the photodiode zero bias and reverses bias impedance characteristics. The critical process variables of Ar:H gas pressure, lower magnet current, and electrode height were all optimized. The optimized process parameters were then utilized to fabricate arrays with 80K cut-off wavelengths in excess of 11 μm, R₀As of 29 Ω-cm², Rd_20mV/Rd_0mV>13 and quantum efficiency>71%.     

沉积、退火条件以及刻蚀液对PECVD氮化硅薄膜湿法刻蚀速率的影响

The influence of deposition, annealing conditions, and etchants on the wet etch rate of plasma enhanced chemical vapor deposition （PECVD） silicon nitride thin film is studied. The deposition source gas flow rate and annealing temperature were varied to decrease the etch rate of SiNx：H by HF solution. A low etch rate was achieved by increasing the SiH4 gas flow rate or annealing temperature, or decreasing the NH3 and N2 gas flow rate. Concentrated, buffered, and dilute hydrofluoric acid were utilized as etchants for Sit2 and SiNx：H. A high etching selectivity of Sit2 over SiNx：H was obtained using highly concentrated buffered HE     

碳氟等离子体中CF2对SiO2，Si3N4和Si刻蚀的作用

The CF2 density and etch rate of SiO2, Si3N4 and Si are investigated as a function of gas pressure and O2 flow rate in fluorocarbon plasma. As the pressure increases, the self-bias voltage decreases whereas the SiO2 etch rate increases. Previous study has shown that SiO2 etch rate is proportional to the self-bias voltage. This result indicates that other etching parameters contribute to the SiO2 etching. Generally, the CF2 radical is considered as a precursor for fluorocarbon layer formation. At a given power, defluorination of fluorocarbon under high-energy ion bombardment is a main source of fluorine for SiO2 etching. When more CF2 radical in plasma, SiO2 etch rate is increased because more fluorine can be provided. In this case, CF2 is considered as a reactant for SiO2 etching. The etch rate of Si3N4 and Si is mainly determined by the polymer thickness formed on its surface which is dominated by the CF2 density in plasma. Etching results obtained by varying O2 flow rate also support the proposition.     

半导体芯片中等离子损伤的解决方案

在研发一套基于0.18μm工艺的全新半导体芯片时,由于芯片工艺的要求我们将标准0.18μm工艺流程中的接触孔蚀刻阻挡层由原来的UVSIN+SION改为SIN,但却引进了PID(等离子体损伤)的问题。当芯片的关键尺寸减小到0.18μm时,栅氧化层变得更薄,对等离子体的损伤也变得更加敏感。所以如何改善PID也成为这款芯片能否成功量产的重要攻坚对象。这一失效来源于接触孔阻挡层的改变,于是将改善PID的重点放在接触孔蚀刻阻挡层之后即后段工艺上。后段的通孔蚀刻及钝化层的高密度等离子体淀积会产生较严重的等离子体损伤,因此如何改善这两步工艺以减少等离子体损伤便成为重中之重。文中通过实验验证了关闭通孔过蚀刻中的磁场以及减小钝化层的高密度等离子体淀积中的溅射刻蚀功率可以有效改善芯片的等离子体损伤。通过这两处的工艺优化,使得PID处于可控范围内,保证了量产的芯片质量。     

The effects of reactive ion etching-induced damage on the characteristics of ohmic contacts to n-Type GaN

The effects of reactive ion etching n-GaN surfaces with both SiCl₄ and Ar plasmas have been investigated using transmission line measurements. The measurements were made from ohmic contacts consisting of Al (as-deposited) and Ti/Al (as-deposited and rapid thermal annealed). The contact resistance, specific contact resistance, and sheet resistance were investigated as functions of the dc plasma self-bias voltage and etch time. The contact resistance extracted from contacts fabricated on surfaces etched with SiCl₄ was found to be improved over the unetched samples for all conditions investigated. Dry etching the surface with Ar severely degraded the contact resistance over the unetched sample except at the lower self-bias voltages. Rapid thermal annealing of etched samples prior to Al deposition was found to be effective in removing some of the reactive ion etching/SiCl₄-induced damage.     

HDP-CVD STI oxide process with in situ post deposition laterally enhanced sputter etchback for the reduction of pattern-dependent film topography in deep submicron technologies

This paper introduces a postdeposition pattern-dependent topography-reduction enhancement to the high-density plasma chemical-vapor deposition (HDP-CVD)oxide profile for shallow trench isolation in deep submicron technologies. The enhancement is labeled "laterally enhanced sputter etchback" (L-SEB) and is carried out in situ in the HDP-CVD reactor after film deposition. The L-SEB is set up using O/sub 2/ and Ar at high O/sub 2/ flow. A design of experiment was run to search for optimum gas flow conditions. The optimized process is shown to yield significant lateral "pull-in" of the sizeable HDP oxide cones over large thin-oxide features and flattening of smaller cones over dense small features, without appreciable impact on field oxide (FOX) thickness or corner integrity. This contributes a significant improvement to an STI module that incorporates downstream planarization processes of reverse-tone etch (RTE) and chemical mechanical polishing (CMP). It also allows a start with a thinner film thickness and usage of a smaller lithography compensation factor for the reverse-tone mask, thus facilitating a smaller minimum feature for RTE exposure. These advantages enhance the manufacturability of the STI process module in terms of reducing the starting HDP film thickness,cutting down on etching and polishing times of RTE and CMP, respectively,and yielding better post-CMP within-die and within-wafer FOX uniformities.     

Characterization of the CH4/H2/Ar high density plasma etching process for HgCdTe

High density plasma etching of mercury cadmium telluride using CH₄/H₂/Ar plasma chemistries is investigated. Mass spectrometry is used to identify and monitor etch products evolving from the surface during plasma etching. The identifiable primary etch products are elemental Hg, TeH₂, and Cd(CH₃)₂. Their relative concentrations are monitored as ion and neutral fluxes (both in intensity and composition), ion energy and substrate temperature are varied. General insights are made into surface chemistry mechanisms of the etch process. These insights are evaluated by examining etch anisotropy and damage to the remaining semiconductor material. Regions of process parameter space best suited to moderate rate, anisotropic, low damage etching of HgCdTe are identified.     

Characterization of reactive ion etching-induced damage to n-GaN surfaces using schottky diodes

Dry etch-induced damage has been investigated using Pd Schottky diodes fabricated on n-type GaN surfaces that were etched by reactive ion etching in SiCl₄ and Ar plasmas. Damage was evaluated by measuring the current-voltage, current-voltage-temperature, and capacitance-voltage characteristics of the diodes. A plasma chemistry that includes a chemical etching component (SiCl₄) was found to significantly reduce the degree of induced damage in comparison to a chemistry that uses only a physical component (Ar). The effective barrier height, ideality factor, reverse breakdown voltage, reverse leakage current, and the effective Richardson coefficient of diodes etched under various plasma conditions are presented. The degree of etch-induced damage was found to depend strongly on the plasma self-bias voltage but saturates with etch time after an initial two-minute etch period. Rapid thermal annealing was found to be effective in improving the diode characteristics of the etched GaN samples.     

高Al组分AlGaN的ICP干法刻蚀

初步研究了采用Cl2 /Ar /He等离子体对MOCVD生长的背照射Al0. 45 Ga0. 55N材料的 ICP干法刻蚀工艺。采用离子束溅射生长的Ni作为刻蚀掩模,刻蚀速率随ICP直流偏压的增加而增加。采用传输线模型测量了刻蚀前后AlGaN材料方块电阻的变化,分析了干法刻蚀电学损伤与直流偏压的关系。用扫描电镜( SEM)观察了不同直流偏压下刻蚀台面形貌,并对其进行了分析。     

Comparison of plasma etch techniques for III–V nitrides

Fabrication of group-III nitride devices relies on the ability to pattern features to depths ranging from 1000 Å to >5 μm with anisotropic profiles, smooth morphologies, selective etching of one material over another and a low degree of plasma-induced damage. In this study, GaN etch rates and etch profiles are compared using reactive ion etch (RIE), reactive ion beam etching (RIBE), electron cyclotron resonance (ECR) and inductively coupled plasma (ICP) etch systems. RIE yielded the slowest etch rates and sloped etch profiles despite dc-biases >−900 V. ECR and ICP etching yielded the highest rates with anisotropic profiles due to their high plasma flux and the ability to control ion energies independently of plasma density. RIBE etch results also showed anisotropic profiles but with slower etch rates than either ECR or ICP possibly due to lower ion flux. InN and AlN etch characteristics are also compared using ICP and RIBE.     

HDP介质淀积引起的等离子充电损伤机制研究

高密度等离子体化学气相淀积(HDP CVD),具有卓越的填孔能力和可靠的电学特性等诸多优点,因此它被广泛应用于超大规模集成电路制造工艺中.本文研究了金属层间介质(IMD)的HDP CVD过程对栅氧化膜的等离子充电损伤.研究表明在HDP淀积结束时的光电导效应使得IMD层(包括FSG和USG)在较短的时间内处于导电状态,较大电流由IMD层流经栅氧化膜,在栅氧化膜中产生缺陷,从而降低了栅氧化膜可靠性.通过对HDP CVD结束后反应腔内气体组分的调节,IMD层的光电导现象得到了一定程度的抑制,等离子充电损伤得到了改善.     

InAs/GaSb超晶格探测器台面工艺研究

InAs/GaSb SLs探测器台面刻蚀常用的工艺有干法刻蚀和湿法刻蚀.研究了三种等离子刻蚀气体(Cl2基, Ar基和CH4基)对超晶格的刻蚀效果,SEM结果表明,CH4基组分能够得到更加平整的表面形貌和更少的腐蚀坑;之后采用湿法腐蚀工艺,用于消除干法刻蚀带来的刻蚀损伤,分别研究了酒石酸系和磷酸系两种腐蚀溶液的去损伤效果,结果表明,磷酸系腐蚀液的去损伤效果更好,且腐蚀速率更加稳定.采用优化的台面工艺制备了InAs/GaSb SLs探测器,其I-V特性曲线表明二极管具有较低的暗电流,其77 K时动态阻抗R0A =1.98104 cm2.     

Characterization of the CH4/H2/Ar high density plasma etching process for ZnSe

High density plasma etching of zinc selenide using CH₄/H₂/Ar plasma chemistries is investigated. Mass spectrometry, using through-the-platen sampling, is used to identify and monitor etch products evolving from the surface during etching. The identifiable primary etch products are Zn, Se, ZnH₂, SeH₂, Zn(CH₃)₂, and Se(CH₃)₂. Their concentrations are monitored as ion and neutral fluxes (both in intensity and composition), ion energy, and substrate temperature are varied. General insights about the surface chemistry mechanisms of the etch process are given from these observations. Regions of process parameter space best suited for moderate rate, anisotropic, and low damage etching of ZnSe are proposed. Code 6752 Code 6174