Stable field emission from planar-gate electron source with MWNTs by electrophoretic deposition

A planar-gate electron source with multi-wall carbon nanotubes (MWNTs) has been successfully fabricated by conventional magnetron sputtering, lithography and electrophoretic deposition (EPD). The optical microscopy showed that he MWNTs purified in H₂SO₄/HNO₃ solution were selectively deposited on cathode. High resolution transmission electron microscopy (HRTEM) images and Raman spectra demonstrated that some MWNTs was destroyed and generated some defect. Field emission results indicated that the emission current of this triode structure is completely controlled by gate voltage. The turn-on voltage of electrophoretic deposited MWNTs cathode at current density of 1 μA/cm² was lower than that of screen printed MWNTs cathode besides better emission uniformity. In addition, the emission current fluctuation was less than 3% for 400 min. All the results indicate that the fabricated electron emission source has a good field emission performance and long lifetime.     

一种P-GaN栅结合混合帽层结构的HEMT器件

为了进一步提升P-GaN栅HEMT器件的阈值电压和击穿电压,提出了一种具有P-GaN栅结合混合掺杂帽层结构的氮化镓高电子迁移率晶体管(HEMT)。新器件利用混合掺杂帽层结构,调节整体极化效应,可以进一步耗尽混合帽层下方沟道区域的二维电子气,提升阈值电压。在反向阻断状态下,混合帽层可以调节栅极右侧电场分布,改善栅边电场集中现象,提高器件的击穿电压。利用Sentaurus TCAD进行仿真,对比普通P-GaN栅增强型器件,结果显示,新型结构器件击穿电压由593 V提升至733 V,增幅达24%,阈值电压由0.509 V提升至1.323 V。     

带电子聚焦的氧化锌场发射背光源

液晶显示需要低功耗、均匀度好的光源作为背光源。为了降低功耗,提高显示图像质量,未来的液晶显示需要实现对背光源进行时间与阵列调制。对比现有的液晶显示用背光源,研究制备了氧化锌场发射光源。该光源采用氧化锌纳米针作为场发射阴极,采用平面栅极作为门电极调制结构实现亮度的连续可调,通过带有氧化镁二次电子发射层的金属栅网对电子进行聚焦实现光源的均匀照度。实验结果表明,带电子聚焦的氧化锌场发射光源具有较低的开启场强(1.1V/μm),较小的电压调制区间(小于150V),较高的发光强度(大于1 000cd/m2),且基于电子聚焦结构的设计,实现了光源的均匀稳定照度,可以提高液晶显示的图像质量。带电子聚焦结构的氧化锌场发射光源,既可实现对发光的时间与阵列调制,同时能提高发光的均匀性,将可作为液晶显示的理想背光源。     

平面栅型FED的模拟研究

采用ANSYS有限元分析软件对平面栅型场致发射显示器（FED）的阴极表面电场进行了模拟分析。通过研究栅极宽度、阴栅间隙及阴极宽度对阴极表面电场分布的影响．结果表明平面栅型FED为边缘发射型器件,阴极宽度的改变对阴极表面电场整体影响明显．而阴栅间隙是影响阴极边缘电场分布的主要因素。     

Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension

A novel cylindrical surrounding gate MOSFETs with electrically induced source/drain extension is proposed and demonstrated by numerical simulation for the first time. In the new device, a constant voltage is applied to the side-gate to form inversion layers acting as the extremely shallow virtual source/drain. Using three-dimensional device simulator, we have investigated the device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing, electrical field and carrier temperature. Based on our simulation results, we demonstrate that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.     

电泳法制备平栅极碳纳米管场发射阴极及场发射特性研究

采用电泳法在ITO玻璃基板上选择性制备了碳纳米管(CNTs)阴极薄膜,采用电子扫描(SEM)分析了CNTs薄膜的表面形貌,并测试了碳纳米管阴极的场致发射特性.结果表明,利用电泳法制得的碳纳米管阴极薄膜均匀性、致密性良好,且具有较大发射电流密度;通过控制共面栅控CNTs场发射阴极的栅极电位能够有效控制阴极的场发射电流密度...     

生长在钨丝上的碳纳米管发射显示阴极

通过化学气象沉积的方法用甲烷作为碳源在金属钨作为衬生长的碳纳米管,我们能发现碳纳米管与催化溶液(Fe(NO3)3·9H2O)在 2.5 摩尔的浓度.在金属钨做衬底的碳纳米管的场发射电流可以达到 100 微安时场发射增强因子大约为5008.通过用一个简单的玻璃真空管结构作为真空腔,我们可以证明场发射发光管和研究这个发光器件的特性.这个发现为制作一种新型的无汞的持久的发光器件成为可能而且有很高的发光性能.     

Design and simulation of a novel E-mode GaN MIS-HEMT based on a cascode connection for suppression of electric field under gate and improvement of reliability

We proposed a novel AlGaN/GaN enhancement-mode (E-mode) high electron mobility transistor (HEMT) with a dual-gate structure and carried out the detailed numerical simulation of device operation using Silvaco Atlas. The dual-gate device is based on a cascode connection of an E-mode and a D-mode gate. The simulation results show that electric field under the gate is decreased by more than 70% compared to that of the conventional E-mode MIS-HEMTs (from 2.83 MV/cm decreased to 0.83 MV/cm). Thus, with the discussion of ionized trap density, the proposed dual-gate structure can highly improve electric field-related reliability, such as, threshold voltage stability. In addition, compared with HEMT with field plate structure, the proposed structure exhibits a simplified fabrication process and a more effective suppression of high electric field.     

A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.     

复合多晶硅栅LDMOS的设计

提出了一种应用于射频领域的复合多晶硅栅LDMOS结构,并提出了具体的工艺实现方法。此结构采用栅工程的概念,设计的栅由S-gate和D-gate两块并列组成,S-gate用高功函数P型多晶硅材料,D-gate用低功函数N型多晶硅材料。MEDICI模拟结果表明,该结构能够降低沟道末端和漏极附近的最高电场强度,提高器件的跨导和截止频率;同时,还能够提高器件的击穿电压,并减小器件的热载流子效应。     

A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature

A novel U-shape buried oxide lateral double diffused metal oxide semiconductor (LDMOS) is reported in this paper. The proposed structure features ionized charges in both sides of dielectric between source and gate region to enhance the breakdown voltage. The dielectric between drain and drift region affects on the breakdown voltage by adding a new peak in the electric field profile. Two dimensional simulation with a commercial software tool predicts significantly improved performance of the proposed device as compared to conventional LDMOS structures.     

低电子亲和势内场发射阴极

平面阴极的场致发射显示器件由于性能优越、结构简单而具有很好的应用前景。这种器件要实用化,急需提高阴极的电子发射率。提出一种改进栅极结构的方法达到提高电子发射率的目的;介绍了双金属栅极的结构和制作工艺;阐述了利用两种金属的接触电位差降低阴极电子发射势垒的原理;解释了实验中低驱动电压时发射率提高较多的现象。与单金属极相比双金属栅极的阴极电子发射率提高了5倍以上。     

基于计算机仿真的ZnO场致发射显示器的研究

在Spindt结构仿真方法的基础上,将四针状纳米ZnO近似处理成尖锥结构,采用C语言程序编程,求解电位、电场分布、电子运动轨迹及发射电流密度。通过计算机模拟仿真,分析了栅极孔径、栅极电压以及阳极电压等对显示器性能的影响。在理论优化设计指导下,采用丝网印刷制作带孔的介质层,用电泳方法在阴极电极上沉积ZnO发射体,制成孔状金属栅三极结构显示屏。测试了显示器的电子发射调制性能,实验表明采用计算机仿真设计的三极结构ZnO场致发射显示器具有良好的场致发射性能。     

Novel fully self-aligned MESFET using source and drain regrown nonalloyed contacts by ALE

A new low temperature, nonalloyed, self-aligned FET process using regrowth technology on a patterned substrate has been demonstrated. A double 8-doped MESFET with regrown n⁺⁺ source and drain contact regions using atomic layer epitaxy (ALE) were fabricated and characterized. In this novel regrowth technique, a silicide gate was embedded by molybdenum and a side wall oxide to prevent any contamination or unwanted reaction during the ALE growth. Two main features associated with our process that makes it an attractive technology for more uniform device performance across a large area wafer are: a) the refractory gate/GaAs interface is not subjected to any high temperature process, and b) nonalloyed ohmic contacts are achieved without undesirable lateral diffusion of n⁺ regions caused by annealing of implanted source and drain. The preliminary unoptimized device results show a transconductance of 40 mS/mm for gate length of 0.65 μn.     

A novel high performance insulated gate bipolar transistor

For the first time, a new concept of LDE-IGBT (local drift-region enhanced IGBT) is proposed and verified by two-dimensional (2D) device-circuit mixed simulations. The structure of the proposed device is almost identical to that of the conventional IGBT, except for an additional n⁺ plugged region under the gate contact. The proposed device exhibits larger maximum operating current, meaning higher current capability, which is expected for high-power operation. The simulation results indicate the LDE-IGBT can obtain a low on-state voltage drop with negligible increase of turn-off time due to lower sensitivity of turn-off time to the novel structure. Therefore, the trade-off relation between on-state voltage and turn-off time is improved and decoupled efficiently. Finally, the effects of three novel structure parameters on the on-state voltage are demonstrated in detail.     

Low turn-on voltage field emission triodes with selective growth ofcarbon nanotubes

A low turn-on voltage, field emission triode array has been fabricated using the selective deposition of carbon nanotubes (CNTs) in a microwave plasma chemical vapor deposition (MPCVD) system. The field emission triodes exhibited a low turn-on voltage of 13 V and a large emission current of 23 μA with the gate voltage at 60 V. Short-term stress reveals a 10% current fluctuation within 1800 sec. The excellent electric properties suggest that the array shows potential for application in field emission displays and vacuum microelectronics     

Novel structure of GaAs-based interdigital-gated HEMT plasma devices for solid-state THz wave amplifier

Theoretical analysis of potential distribution in the interdigital-gated high electron mobility transistor (HEMT) plasma wave device was carried out. The dc I–V characteristics of capacitively coupled interdigital structure showed that uniformity of electric field under the interdigital gates was improved compared to the dc-connected interdigital gate structure. Admittance measurements of capacitively coupled interdigital gate structure in the microwave region of 10–40 GHz showed the conductance modulation by drain–source voltage. These results indicate the existence of plasma wave interactions.     

A novel field effect transistor with dielectric polymer gel

A novel organic-field effect transistor (OFET) has been fabricated. This device is original in the sense that it can be produced in ambient conditions with facile and cost-effective methods. Experimental results surprisingly revealed a high mobility value at the order of 0.38 cm²/Vs, and the gate voltage is also found to be lower than 1 V. The device exhibited excellent transistor characteristics at low voltages. Threshold voltage is around 0.26 V with 10³ on/off ratio. The device design is based on high effective capacitance value of a polymer gel, 1 μF, which is sandwiched between glass substrates on which source and drain electrodes were constructed.     

边缘注入对H型栅SOI pMOSFETs亚阈值泄漏电流的影响

就不同边缘注入剂量对H型栅SOI pMOSFETs亚阈值泄漏电流的影响进行了研究。实验结果表明不足的边缘注入将会产生边缘背栅寄生晶体管,并且在高的背栅压下会产生明显的泄漏电流。分析表明尽管H型栅结构的器件在源和漏之间没有直接的边缘泄漏通路,但是在有源扩展区部分,由于LOCOS技术引起的硅膜减薄和剂量损失仍就促使了边缘背栅阈值电压的降低。     

A New SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

To improve the characteristics of breakdown voltage and specific on‐resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon‐on‐insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on‐resistance. The breakdown voltage and the specific on‐resistance of the fabricated device is 352 V and 18.8 m·cm² with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on‐state is over 200 V and the saturation current at V_gs=5 V and V_ds=20 V is 16 mA with a gate width of 150 µm.