Complete test-set generation for bridging faults in combinational-logic circuits

The present paper describes some algorithms for generating complete test sets for bridging faults in combinational logic circuits. It is shown how the concept of Boolean difference, which is well understood in the case of stuck-type fault situations, can be employed to generate the complete test set for bridging faults in combinational networks. The cases of single bridging fault and multiple input bridging fault are dealt with. An algorithm is also described for generating the complete test set of a combinational logic circuit in which a single stuck-type fault occurs in the presence of a bridging fault.     

Detection of all single and multiple stuck-at faults in combinational digital circuits using index vector testing

A new method for the testing of combinational digital circuits is presented. The method is based on the concept of the ‘index vector’ of a switching function (Gupta 1987), and represents an extension of syndrome testing. A large percentage of syndrome untestable faults are found to be index vector testable. An approach to testing index vector untestable circuits that relies only on the function realized by the circuit and is independent of the circuit topology is presented. The method can be used for the detection of both single and multiple stuck-at faults in a combinational circuit.     

Easy Test Generation PLAs

Test Generation for large circuits may be extremely difficult.One of the approaches to alleviatingthis problem is to consider the difficulties during the design cycle.This paper proposes a design of EasyTest Generation Programmable Logic Arrays(ETG PLAs),for which test generation is basically notrequired,since a complete test set can be generated while the test is applied.This paper also presents aprocedure which makes a PLA an ETG PLA by following some design rules and providing reasonableextra hardware.     

基于多扫描链的内建自测试技术中的测试向量生成

针对基于多扫描链的内建自测试技术,提出了一种测试向量生存方法。该方法用一个线性反馈移位寄存器（LFSR）作为伪随机测试向量生成器,同时给所有扫描链输入测试向量,并通过构造具有最小相关度的多扫描链克服扫描链间的相关性对故障覆盖率的影响。此外该方法经过模拟确定难测故障集,并针对这外难测故障集利用ATPG生成最小确定性测试向量集。最后丙依据得到的最小测试向量集来设计位改变逻辑电路,利用们改变逻辑电路控制改变扫描链上特定的值来实现对难测故障的检测,从而实现被测电路和故障完全检测。     

完全自校验四余度容错系统设计

完全自校验四余度容错系统是由完全自校验电路管理一个传统的四余度容错系统组成,其中完全自校验电路的功能是用来检测冗余模块错误信息和校验电路本身的错误。错误信息指示主要依赖于错误信息输出,它可以用来产生停止信号来阻止错误的传播。校验电路内部错误产生的指示码和冗余模块错误信息无关,但是可以屏蔽冗余模块和完全自校验电路的错误。此系统具有很高的可用性和可维护性。     

模糊聚类与SVM诊断模拟电路单软故障的方法

针对低可测性模拟电路中存在的模糊组问题,提出一种模拟电路单个软故障诊断的方法．该方法对被测电路的故障进行模糊聚类,根据聚类的有效性指标自适应确定聚类数,并利用聚类的信息来确定可测元件集,引入支持向量机对故障进行分类识别．支持向量机结构简单、泛化能力强．最后,以模拟和混合信号测试标准电路证实了文中方法的有效性．     

A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults

A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits.     

基于多故障模型的并发测试生成方法

精简测试向量集是解决电路测试问题的一种行之有效的方法。针对故障电路,采用多故障模型方法可以简化有多个单故障的电路,且保持电路功能完整。论文在结构分析的基础上,利用多故障模型寻找故障集中的并发故障,建立并发关系图,并运用分团的思想对故障集中的并发故障进一步划分,以获得故障集的并发测试集。与传统的方法相比,并发测试生成将获得更加精简的测试向量集。     

Designing CMOS Circuits for Switch-Level Testability

Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level faults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. An inverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-on faults.     

固定型故障完全可测异步控制电路设计

本文基于直接映射技术和异步控制电路的故障自检测特性,提出了一种固定型故障完全可测的异步控制电路设计方法,并在此基础上对异步控制电路单固定型故障的测试策略进行了较为详细的阐述。结果表明本方法切实有效且额外的面积开销小。     

基于混沌搜索的数字电路多故障测试生成

针对数字电路中多故障测试生成较难的问题,本文提出了基于混沌搜索的数字电路多故障测试生成算法。该算法先把多故障转换成为单故障,再用神经网络的方法对单故障电路构造故障的约束网络,最后用混沌搜索方法求解故障约束网络能量函数的最小值点获得原电路中多故障的测试矢量。在一些国际标准电路上的实验结果表明了本算法的可行性。     

一种有效的EEPLA的测试算法

本文提出了一种硬件电路很少,故障覆盖率最高的ＥＥＰＬＡ的测试算法。同其他测试算法相比,该方法可以对每一个交叉点进行编程控制。所有单一的或多重的交叉点故障、线电位固定在“１”（“０”）、桥连故障都可以测试到,疽测试算法简单易行。     

Built-in test for folded programmable logic arrays

Implementing a function using a programmable logic array (PLA) can often be very expensive in terms of area. Folding rows and/or columns of a PLA usually leads to a reduction in area. In this paper the problem of fault detection in folded PLAs is considered. A new fault, the ‘cutpoint’ fault, is described and universal test sets for the detection of this fault are presented. Modifications to existing built-in universally testable design techniques for nonfolded PLAs are presented; the new designs are now applicable to folded PLAs.     

Multifrequency analysis of faults in analog circuits

Testability analysis of analog circuits in the presence of soft, large-deviation, and hard faults greatly facilitates production of testable systems. The authors analyze these faults by observing their symptoms at the circuit's output, an approach that uses the same test methodology to analyze all three fault types. Their algorithm indicates the set of adequate test frequencies and nodes that increase fault observability. They conclude by generating test vectors for observing and covering these faults     

IDDQ test and diagnosis of CMOS circuits

Designers must target realistic faults if they desire high-quality test and diagnosis of CMOS circuits. The authors propose a strategy for generating high-quality I_DDQ test patterns for bridging faults. They use a standard ATPG tool for stuck-at faults that adapts to target bridging faults via I_DDQ testing. The authors discuss I_DDQ test set diagnosis capability and specifically generated vectors that can improve diagnosability, and provide test and diagnosis results for benchmark circuits     

基于单元故障模型的树型加法器的测试

首先分析了树型加法器的原理，总结了其运算特性．其次在介绍单元故障模型的基础上分析了树型加法器的测试向量生成．分析结果表明，5n-1个测试向量可以实现树型加法器中所有单元故障的检测．这些测试向量具有很好的规则性，能够利用片上测试向量生成器实现，适合于应用内建自测试技术测试．基于此，作者提出了一种内建自测试的测试结构，测试时只需存储7个籽测试向量，其它测试向量可以在这7个籽测试向量的基础上通过循环移位实现．最后给出了实验分析结果．     

基于SAT的多目标故障测试向量动态压缩方法

针对传统的自动测试图形向量生成采用逐个求解单一故障模型导致生成测试向量数据量巨大的缺点, 提出一种基于布尔满足性(boolean satisfiability, SAT)的多目标故障测试向量动态压缩方法, 同时论证多目标故障测试生成问题为布尔满足性问题。该方法将具有鲁棒性的SAT算法嵌入经典的动态压缩流程中, 首先利用经典动态压缩算法求解最小测试向量检测大部分失效故障, 然后采用SAT求解器对未测出的多故障电路进行同一求解和附加约束求解方式, 最终得到故障覆盖率高的测试向量和同一测试最大故障列表。实验数据表明, 在相同电路模型情况下, 此方法求得的测试向量相比经典动态压缩减少高达70%。     

Using a periodic square wave test signal to detect crosstalk faults

Built-in self test (BIST) scheme simplifies the detection of crosstalk faults in deep-submicron VLSI circuits in the boundary scan environment. The scheme tests for crosstalk faults with a periodic square wave test signal under applied random patterns generated by a linear feedback shift register (LFSR), which is transconfigured from the embedded circuit's boundary scan cells. The scheme simplifies test generation and test application while obviating the fault occurrence timing issue. Experimental results show that coverage for the induced-glitch type of crosstalk fault for large benchmark circuits can easily exceed 90%.     

Analysis of testable PLA designs

A framework is presented for evaluating methods of testing programmable logic arrays (PLAs), and the attributes of 25 test design methodologies are tabulated. PLA testing problems are first examined, and several test-generation algorithms are briefly described. Techniques for designing testable designs are examined, namely, special coding, parity checking, signature analysis, divide and conquer, and fully testable PLAs. The attributes that make a good testable design are then discussed. They fall into four categories: (1) testability characteristics; (2) effect on original design; (3) requirements of the application environment; and (4) design costs, i.e. how difficult it is to implement the technique     

Self-checking circuits and decoding algorithms for binary hamming and BCH codes and Reed-Solomon codes over GF(2 m )

We consider problems of detecting errors in combinational circuits and algorithms for the decoding of linear codes. We show that a totally self-checking combinatorial circuit for the decoding of a binary Hamming [n, k] code can be constructed if and only if n = 2 ^r ? 1, r = n?k. We introduce the notion of a totally self-checking combinational circuit detecting error clusters of size at most µ; for shortened Hamming [n,k] codes, we construct totally self-checking decoding combinational circuits detecting error clusters of size at most µ, 2 ≤ µ < n?k. We describe single-error protected and self-checking algorithms: the extended Euclidean algorithm and decoding algorithms for binary BCH codes and Reed-Solomon codes over GF(2 ^m ).