形成倒装芯片焊点的铜接线柱焊凸(SBC)法

在倒装芯片应用中生长晶圆焊凸的工艺中对于间距较小(即小于150μm)、具有数个尺寸为150μm的焊凸,倒装前的焊锡涂敷好坏对产品的良率和可靠性起着重要作用。因为,如果涂敷的焊锡体积不均匀,就经不起涂敷过程中为确保涂敷在引线框上焊锡的完整和体积一致性而引入的强制视像系统检查,从而降低产出率。这就是一些组装工艺正设法减少或取消这些限制的原因。另一方面,采用直接熔化焊凸的方法来形成焊点是一种速度较快的工艺,但在保证回流处理后的离板高度方面有缺点,导致在温度和功率循环测试中的表现较差。介绍的采用铜接线柱焊凸(SolderBumponCopperStud;SBC)法解决了这些问题;对于那些需要倒装的组装工艺而言,这是可保障其制造性较佳的解决方案。介绍采用铜接线柱焊凸(SBC)工艺在附着在倒装芯片上的金属基片和焊凸之间形成焊点的新方法,利用铜接线柱焊凸技术再配合晶圆级的焊锡丝印工艺在半导体上预先形成焊凸。这是替代电镀焊凸工艺一种别具成本效益的方法。     

微米银焊点的超快激光图形化沉积及其在芯片连接中的应用探索

集成电路(IC)芯片封装中小尺寸、细节距焊点采用的传统锡基钎料在服役过程中存在桥接、电迁移、金属间化合物等问题,在大电流、大功率密度的应用中受到限制。采用脉冲激光沉积(PLD)技术,在覆铜陶瓷(DBC)基板上图形化沉积了多孔微米银焊点,用于替代传统的钎料凸点,并将其应用于Si芯片与DBC基板的连接。结果表明:采用不锈钢作为掩模,可沉积出500μm及300μm特征尺寸的疏松多孔银焊点阵列,银焊点呈圆台形貌;在250℃温度、2 MPa压力下热压烧结10 min, Si芯片与DBC基板连接良好,连接后的银焊点边缘的孔隙率为42%左右,银焊点中心区域的孔隙率为22%; 500μm和300μm特征尺寸的银焊点的连接接头的剪切强度分别为14 MPa和12 MPa;接头断裂主要发生在银焊点与芯片或DBC基板的连接界面处。     

采用热压焊工艺实现金凸点芯片的倒装焊接

金凸点芯片的倒装焊接是一种先进的封装技术.叙述了钉头金凸点硅芯片在高密度薄膜陶瓷基板上的热压倒装焊接工艺方法,通过设定焊接参数达到所期望的最大剪切力,分析研究互连焊点的电性能和焊接缺陷,实现了热压倒装焊工艺的优化.同时,还简要介绍了芯片钉头金凸点的制作工艺.     

金凸点的打球法制作与可靠性考核

本文采用打球法在芯片上制作金凸点，并将凸点倒装焊接在Ti/Ni/Au多层金属化的LTCC基板上。利用扫描电镜观察凸点形貌，X射线透射研究倒装互连状况，并通过接触电阻和剪切强度对凸点倒装焊的可靠性进行了考核。     

用于倒装芯片的金球凸点制作技术

倒装芯片中凸点用于实现芯片和基板的电路互连,芯片凸点的制作是倒装芯片技术的关键技术之一.对金球凸点制作进行了介绍.金球凸点直接粘附于芯片上,同时又可具有电路互连的作用,可以完成倒装芯片与基板的电气连接.金球凸点的优势是简单、灵活、便捷、低成本,最大特点是无需凸点下金属层(UBM),可对任意大小的单个芯片进行凸点制作,平整度可达到±4μm.     

铜焊盘与锡合金焊点界面物相分析及可靠性探讨

Sn60Pb40焊料与铜焊盘的焊接界面中金属间化合物Cu6Sn5的形成与长大以及在热循环过程中的组织粗化是影响焊点可靠性的重要因素。作者根据SMT工艺的实际情况，使用Au—Sn共晶焊料、Sn60Pb40焊料分别涂覆在铜合金基板表面，并分别在320℃、240℃下保温1min，冷却形成焊点，利用X射线研究分析了两种不同焊盘基材与Sn60Pb40钎料、Au—Sn共晶钎料的钎焊界面的物相。运用经典相变理论、低周疲劳失效的机理以及“柯肯达尔”效应，就优异焊点的形成、物相产生、温度循环后组织粗化与增加Ni阻挡层，对提高焊接接点的温度循环可靠性的作用进行了分析与探讨。     

一种新型FC和WLP的柔性凸点技术

FC(倒装片)和WLP(圆片级封装)均要在圆片上制作各类凸点,它们与基板焊接互连后,由于各材料间的热失配可能造成凸点——基板间互连失效,从而影响了器件的可靠性和使用寿命。解决这一问题的通常做法是对芯片凸点与基板间进行下填充。本文介绍的柔性凸点技术是在焊球下面增加一层具有弹性的柔性材料,当器件工作产生热失配时,由于柔性材料的自由伸缩,将大大减小以至消除各材料间的失配应力,使芯片凸点与基板下即使不加下填充,也能达到器件稳定、长期、可靠地工作的目的。     

浅谈CTE及其对FC—BGA焊点可靠性的影响

PCB对封装行业来说,最关键的莫过不同元器件和PCB之间的热膨胀系数（CTE）匹配性问题。其中FCRGA封装,通过倒装芯片实现芯片焊料凸点与FCBGA基板的直接连接,在FCBGA类产品中可实现较高的封装密度,获得更优良的电性能和热性能。但由于PCB与芯片之间cTE的不匹配,而导致FCBGA焊点的可靠性问题。本文就CTE影响FCBGA焊点可靠性展开讨论。     

使用再分布技术改善倒装芯片组装热疲劳可靠性

芯片上键合焊盘的设计,可以利用淀积型多芯片组件（MCM－D）的再分布技术,组排新的设计图形。这种新的焊盘布排,可以用作倒装芯片的组装。这些再分布的、倒装芯片结构的、热机械的可靠性,取决于焊点的粘塑性变形,以及BCB（苯丁烷丁烯聚合物）光敏胶再分布层中的应力。本将研究再分布层对焊接处可靠性的影响,以及减小再分布层中的应力,使其不超过极限应力值。考虑了三种不同的再分布层工艺,利用有限元仿真和根据Coffin-Manson的可靠性模型,对再分布的和标准的倒装芯片组件的热循环可靠性进行了比较。芯片上光敏再分布层BCB胶的存在,影响焊点的热疲劳。利用再分布芯片取得的最大的可靠性改善,是靠焊点从芯片周边移到内部,形成面阵列倒装芯片的结果。     

倒装焊陶瓷封装失效模式分析及失效机理研究

随着封装技术的发展,倒装焊技术得到广泛的应用,倒装焊的研究也越来越广泛深入。文章阐述了倒装焊封装的失效模式,主要有焊点疲劳失效、填充胶分层开裂失效、电迁移失效、腐蚀失效、机械应力失效等。并分析了陶瓷基板倒装焊温度循环试验后的失效模式,陶瓷倒装焊封装失效的机理主要是倒装芯片焊点与UBM界面金属间化合物应力开裂失效。根据失效机理分析,进行陶瓷倒装焊工艺优化改进,试验达到了JESD22-A104C标准规定的温度循环:-65℃～+150℃、500次循环、3只样品无失效的要求。     

Effect of substrate flexibility on solder joint reliability

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue lifetime significantly. The reliability of solder joint in flip chip assembly for both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Experimental results strongly showed that the thermal fatigue lifetime of solder joints in flip chip on flex assembly was much improved over that in flip chip on rigid substrate assembly. Debonding area of solder joints in flip chip on rigid board and flip chip on flex assemblies were investigated, and it was found that flex substrate could slow down solder joint crack propagation rate. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique. TMA results showed that flex substrate buckles or bends during temperature cycling and this phenomenon was discussed from the point of view of mechanics of the flip chip assembly during temperature cycling process. It was indicated that the thermal strain and stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Solder wetting in a wafer-level flip chip assembly

Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For real time monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the metallization pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated     

The influence of Sn–Cu–Ni(Au) and Sn–Au intermetallic compounds on the solder joint reliability of flip chips on low temperature co-fired ceramic substrates

The formation of intermetallic compounds in the solder joint of a flip chip or chip scale package depends on the under bump metallurgy (UBM), the substrate top surface metallisation, the solder alloy and the application conditions. To evaluate the influence of intermetallic compounds on the solder joint reliability, a detailed study on the influence of the UBM, the gold finish thickness of the substrate top surface metallisation, the solder alloy and the aging conditions has been conducted. Flip chips bumped with different solder alloys were reflow-mounted on low temperature co-fired ceramic substrates. The flip chip package was then aged at high temperature and a bump shear test followed to examine the shear strength of the solder joint at certain aging intervals. It was found that the type of UBM has a great impact on the solder joint reliability. With Ni(P)/Au as the UBM, well-documented gold embrittlement was observed when the gold concentration in the eutectic SnPb solder was about 3 wt%. When Al/Ni(V)/Cu was used as the UBM, the solder joint reliability was substantially improved. Copper dissolution from the UBM into the solder gives different intermetallic formations compared to Ni(P)/Au as UBM. The addition of a small amount of copper in the solder alloy changed the mechanical property of the intermetallic compound, which is attributed to the formation of Sn–Cu–Ni(Au) intermetallic compounds. This could be used in solving the problem of the AuSn₄ embrittlement. The formation and the influence of this Sn–Cu–Ni(Au) intermetallic phase are discussed. The gold concentration in the solder joint plays a role in the formation of intermetallic compounds and consequently the solder joint reliability, especially for the Sn–Ag–Cu soldered flip chip package.     

Improved thermal fatigue reliability for flip chip assemblies usingredistribution techniques

The bond pad design on a chip can be reconfigured to a new pad design using a redistribution layer, based on multichip module-deposited (MCM-D) technology. The new pad configuration can be used for flip chip mounting. The thermo-mechanical reliability of these redistributed flip chip structures is in particular determined by the visco-plastic deformations of the solder joints and by the stresses in the photosensitive BCB redistribution layers. In this paper, the influence of this redistribution layer on the solder joint reliability is investigated. Also the induced stresses in this redistribution layer may not exceed the ultimate stress level. Three different redistribution processes are considered. Finite element simulations and Coffin-Manson based reliability models are used to compare the thermal cycling reliability of redistributed and standard flip chip assemblies. The existence of a photosensitive BCB redistribution layer on the chip influences the thermal fatigue of solder joints. The largest reliability improvement using redistributed chips is achieved by moving the solder joints from the perimeter to the interior of the die resulting in an area array flip chip     

Effect of substrate flexibility on solder joint reliability. Part II: finite element modeling

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique and finite element modeling. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Finite element simulations were conducted to study the reliability of solder joints in flip chip on flex assembly (FCOF) and flip chip on rigid board assembly (FCOB) applying Anand model. Based on the finite element analysis results, the fatigue lives of solder joints were obtained by Darveaux’s crack initiation and growth model. The thermal strain/stress in solder joints of flip chip assemblies with different substrates were compared. The results of finite element analysis showed a good agreement with the experimental results. It was found that the thermal fatigue lifetime of FCOF solder joints was much longer than that of FCOB solder joints. The thermal strain/stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

Using active thermography for defects inspection of flip chip

With the development of electronics towards smaller, more compact, and increasingly complex, flip chip technology has been used extensively in microelectronic packaging, and disadvantages occur in traditional detection methods. It is indispensable to explore new methods for flip chip solder joint inspection. In this paper we investigate an approach for solder joint inspection based on the active thermography. The basic principle of the active thermography method is described, and the experimental investigation is carried out using the method. The test flip chip is heated by a non-contact heating source. The thermal distribution on two kinds of chips is captured by an infrared thermal imager. With median filter and segmentation processes, positions of the bumps are segmented. For chips with smaller bumps, principal component thermography is introduced to enhance the segmentation process. The analysis results demonstrate that missing bumps in flip chips can be discerned obviously, which proves the feasibility of the proposed method for defects inspection of flip chips.     

Effect of Gold Stud Bump Topology on Reliability of Flip Chip on Flex Interconnects

The flip chip technique using conductive adhesives have emerged as a good alternative to solder flip chip methods. Different approaches of the interconnection mechanism using conductive adhesives have been developed. In this paper, test chips with gold stud bumps are flip-chipped with conductive adhesives onto a flexible substrate. An experimental study to characterize the bonding process parameters is reported. Initial results from the environmental studies show that thermal shock test causes negligible failure. On the other hand, high humidity test causes considerable failure in flip chip on flex assemblies. Improvements in the reliability of the assembly are achieved by modifying the shape of the gold stud bumps.     

MECHATRONICS 2000. Seventh Mechatronics Forum InternationalConference and Mechatronics Education Workshop

The following topics are dealt with: flip chip solder joint quality inspection; direct chip attach packaging for microsystems; reliability analysis of no-underfill flip chip package; ASIC/memory integration by system-on-package; wafer-level and flip chip designs through solder prediction models and validation; reliability evaluation of under bump metallurgy in two solder systems; a method to improve the efficiency of the CMP process; thermal and reliability analysis of packaging systems     

High density of electrodeposited Sn/Ag bumps for flip chip connection

As peripheral pads in commercial chips have a pitch in the neighbourhood of 40-50 μm, a technique that could deposit solder paste directly in such pitch would be of great interest to reduce the overall cost of flip chip.This paper describes a new technique that can considerably reduce the final pitch. The main new feature of this process is that the bump pads can be built directly onto the peripheral ones. An electroplating process allows solder bump formation with a final pitch goal of 40-50 μm and after an accurate reflow process, eutectic Sn-3.5 wt%Ag solder bumps are obtained. In fact, the typical re-routing process can be eliminated and the process cost considerably reduced.