Characterization of AZ-2415 as a negative electron resist

The use of AZ-2415 as a negative electron resist is described. The effects of electron dose, optical dose, and development time on the resist line profiles are investigated. A low optical dose leads to wider and thicker developed negative lines, but with a lower contrast than lines exposed with a higher optical dose. An increase in development time results in a higher contrast which is accompanied by a significant increase in the electron dose required to maintain a fixed linewidth. A good overall process scheme would avoid both the low optical dose area and the shortest development times in favor of values of these parameters that offer greater linewidth control. Using a 0.5-µm initial film thickness, an electron dose of 80 to 120 µC/cm², an optical dose of 333 mJ/cm², and a 15-s development in 1:3.5 AZ-2401:H2O produce submicrometer resist patterns that provide excellent resistance to plasma etching.     

0.4-µm gate-length devices fabricated by contrast-enhanced lithography

This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 µm were fabricated with this process. Contrast-enhanced lithography (CEL) allows usable photoresist patterns to be fabricated at smaller dimensions than is possible with conventional resist. The simultaneous replication of mask dimensions for isolated lines at 0.35 µm and above was achieved in this work using a single exposure on an Optimetrix 10:1 DSW system. Contrast enhancement has been applied to the fabrication of n-channel MOS devices having gate lengths from 0.4 to 1.5 µm in steps of 0.1 µm. Long-channel devices were also fabricated. The transconductance of the 0.4-µm devices is 40 mS/mm at Vds= 5 V. Threshold voltages (Vds= 0) are nearly independent of gate length, ranging from 1.21 to 1.31 V over the 7.5- to 0.4-µm range in gate length. The effective mobility for long-channel devices is 430 cm²/V.s.     

Electron beam direct writing technology applied to 512 kbit ROM with 1 µm geometry

A 512 kbit read-only memory (ROM) to store Chinese ideographs has been fabricated using variable-shaped electron beam and dry-etching lithography. 1.0-µm minimum line width was used to delineate device area spacings smaller than those obtained with conventional design rules using photoimaging techniques. SiO2, Si3N4, and polysilicon etchings were accomplished by reactive sputter techniques with CF4+ H2and CCl3F gases using negative electron beam resist PGMA and positive resist AZ-2400. Al etching was carried out by plasma with CCl4gas using negative electron beam resist NER-1. The alignment marks detectability and their locating accuracy were improved by properly using the basis arithmetic operations, subtraction and summation, in backscatter signal processings. 6.6 mm × 8.9 mm chip-by-chip alignment yielded about 0.2-µm level-to-level registration accuracy. Memory cell size and chip size are 5.2 µm × 8.4 µm and 6.6 mm × 8.9 mm, respectively; access time and power dissipation are 400 ns and 800 mW, respectively.     

Reactive ion etching for VLSI

Reactive Ion Etching (RIE) is a dry etching technique that is used to etch 1-µm and submicrometer patterns into films of silicon and silicon compounds. RIE is suitable for VLSI applications because etching is anisotropic and proceeds via chemical reactions with the substrate. Anisotropic etching allows faithful reproduction of resist patterns into the films that make up a device, and chemical etching allows development of selective etching by manipulating the composition of the plasma. The RIE reactor is described and examples of its use to fabricate 1-µm MOSFET's are given. Concerns arising from the presence of a voltage between the substrates and the plasma, radiation damage of SiO2and contamination of silicon, are discussed.     

Dry etching technology for 1-µm VLSI fabrication

A dry etching technology for 1-µm VLSI has been developed. This technology led to successful fabrication of a 1-µm 256-kbit MOS RAM using electon-beam direct writing and molybdenum-polysilicon double-gate structure. Silicon nitride, silicon dioxide, phosphosilicate glass, polysilicon, single-crystal silicon, molybdenum, and aluminum are etched by parallel-plate RF diode reactors. Resist patterns are used as etching masks. The negative resist is CMS and the positive resist is FPM. Plasma polymerization is found to have significant effect on etching selectivity, undercutting, and residue. Directional etching profiles are realized and 1-µm patterns with less than 0.05-µm undercutting are obtained. High etching selectivities are achieved. Methods for preventing and removing contamination as well as damage are established. With these, dry etching proves to bring no adverse effects on device characteristics. Pattern-width fluctuations caused by negative-resist pattern foot are decreased to below 0.1 µm by a new foot trimming technique. Resist step coverage is also clarified.     

Electron-beam fabrication of submicrometer bipolar transistors for high-frequency low-current operation

A submicrometer device technology has been developed for the design and fabrication of bipolar transistors capable of high-frequency operation at low currents. Direct write electron-beam lithography is used with a single-level resist process that is compatible with high dose ion implants and dry etching, and is capable of producing feature sizes to at least the 0.5-µm level. A low temperature local oxidation process is used to minimize parasitic capacitances. Both process and device models are used in the design, which must consider the two-dimensional nature of the base-emitter region, since for these structures, the emitter junction depth is comparable in size to the emitter width. Data are presented and compared on 0.5-, 0.75-, and 1.0-µm devices.     

Variable-shaped electron-beam direct writing technology for 1-µm VLSI fabrication

A 1-µm 256K MOS RAM has been fabricated using a variable-shaped electron-beam (EB) direct writing technology. EB drawing data are prepared using a new program, PEBL, which includes a new algorithm for shot division. PEBL plays an important role in obtaining high EB system throughput and high quality patterns. A new proximity correction technique, DCA, has also been proposed. This technique is simple and very effective in fabricating 1-µm VLSI patterns. Negative resist CMS or positive resist FPM are used appropriately, according to process levels. In fabrication of a 1-µm 256K MOS RAM, ±0.2-µm overlay accuracy and ±0.1-µm linewidth accuracy were achieved.     

Optimization of the composition of a new MRS-type negative resist

Sensitizer concentration is optimized for a new negative photoresist, MRL (Micro Resist for Longer wavelengths) with the assistance of computer simulation. The resist, which has photosensitivity in the ordinary UV region, resembles a deep UV resist MRS in terms of light absorption characteristic. It is found that a photosensitizer concentration of 20 wt% (based on the resin) is suitable for a reduction projection exposure system that utilizes UV light at 365 nm. A steep profile resist image of 0.7-µm lines and 0.7-µm spaces in a 1.0-µm thick resist layer is obtained using the MRL of optimized composition and the exposure system.     

Alignment signals from resist-coated marks for direct wafer writing

Monte Carlo (MC) calculations based on a continuous-slowing-down approximation and experimental techniques are used to characterize the backscattered alignment signals from resist-covered Si tapered step marks. Effects of the coated thickness and the resist profile slope are separated by using MC simulation. A 1-µm resist coating on a 2-µm Si step reduces the maximum differenceDeltaSin the back-scattered signal for 20-keV electrons by a factor of 2 and about ⅓ of this reduction is due to the fact that the resist does not conformally follow the step. The rate of reduction inDeltaSwith resist coating was found to be faster for signals collected from low takeoff angles, however, the low takeoff angle signals are still preferred. For a 1-µm resist coating and 20-keV electrons, backscattered electrons with less than half the incident energy contain more information about the substrate but the use of energy analysis techniques would only improve the contrast slightly with a tradeoff in reduced signal-to-noise ratio. For best results alignment marks should a) be covered by a resist thickness less than 0.4 RB(RB= Bethe range) so that electrons will "see" the underlying material, and b) have a depth larger than ⅓ the resist thickness, so that the resist profiles will adequately reflect the underlying mark topography.     

MOS and bipolar VLSI technologies using electron-beam lithography

Key issues for micrometer and submicrometer MOS and bipolar device fabrication are discussed, including lithography, device and circuit scaling limitations, and process considerations. Lithographic requirements are presented in terms of an overall technology-machine, resist and pattern transfer methods-and an electron-beam alice writing technology is described which satisfies those needs. Viable micrometer and submicrometer MOS and bipolar process technologies are demonstrated by scaling complex LSI circuits to VLSI density using electron lithography. For the MOS case, scaling of static memories is discussed in detail, including fabrication of a 4K SRAM with 1.5-µm minimum feature sizes, 12-15-ns access times, and a chip size of only 6K mil². A discussion of bipolar device and process scaling issues is highlighted by the successful fabrication of a scaled 16-bit integrated injection logic (I²L) microprocessor with 1.25-µm minimum feature sizes and a clock frequency of 10 MHz with a chip current of only 250 mA.     

The use of submicrometer electron-beam lithography for fabricating 4-kbit CCD memory arrays

A 4-kbit CCD memory array has been fabricated using electron-beam lithography for the high-resolution patterns and projection lithography to define the low-resolution features. The basic CCD cell size is 3.2 µm × 4.2 µm consisting of a storage area 2.4 µm × 3.6 µm with a 0.8-µm barrier and a 0.6-µm channel stop. To make these small CCD's, as well as the associated short-channel MOSFET's, we modified the conventional MOS wafer processing. The new process for two-level polysilicon gates requires six electron-beam levels with a minimum resist feature of 0.3 µm. Alignment of the electron-beam patterns uses Ta benchmarks which we found to be compatible with MOS devices. Testing of the 4-kbit array and other shift resisters showed submicrometer channel-stops and barriers are feasible while maintaining low channel-to-channel crosstalk and charge-transfer efficiency greater than 0.9995. In addition, low capacitance output circuits defined by electron-beam lithography can detect the small number of charges in the high-resolution CCD's and amplify the signal sufficiently to recirculate the data.     

Resolution and linewidth tolerances in electron beam and optical projection lithography

In order to understand the practical limits of electron beam direct-write and optical projection lithography techniques in device fabrication with micrometer and submicrometer geometries, we have exercised two computer simulation programs to estimate resolution limits and linewidth control. Latent image contrast and developed resist thickness contrast were calculated as a function of line-array spatial frequency. The linewidth tolerances were calculated by varying exposure, development time, focusing, line/space Pattern, resist thickness, etc. These simulation results indicate that the lithographic performance of the two techniques using state-of-the-art exposure tools are comparable at 1-µm dimensions. Some relevant experimental data also are presented.     

Improved short-channel GaAs MESFET's by use of higher doping concentration

GaAs MESFET's with highly doped channels up to5 times 10^{18}cm^-3and with both micrometer and submicrometer gates were fabricated and evaluated. FET's with 1.2-µm gates show an extrinsic transconductance of more than 250 mS/mm, cutoff frequencies around 20 GHz, and a noise figure of 2 dB at 8 GHz with 9-dB associated gain. Breakdown voltage is higher than 6 V. FET's with 1.2- and 0.4-µm gates were simultaneously fabricated on the same wafer to investigate short-channel effects. The short-channel devices show a good saturation behavior and no shift in the threshold voltage compared to the long-channel devices thus demonstrating a pronounced alleviation of short-channel effects as experienced for1 times 10^{17}cm^-3doping levels. The influence of doping concentration on the performance of devices with micrometer and submicrometer gates upon doping concentration is investigated by detailed computer simulations. Good agreement between theoretical and experimental results is obtained. From these results improved technological approaches are pointed out.     

Submicrometer CMOS device fabrication using an X-ray stepper

CMOS devices with submicrometer minimum features have been fabricated using X-ray/photo hybrid lithography. The device fabrication process utilized thirteen lithography steps, including four X-ray lithography levels, such as local oxidation of silicon (LOCOS) [1], gate, contact, and wiring, that required the most critical dimension control and alignment accuracy. A step and repeat exposure system and a SiNxmembrane mask were used for the X-ray lithography process. The SiNxmembrane mask was improved in its flatness and effective contrast by employing a stress compensating structure and a secondary electron trapping film. As a result, CMOS devices with 0.4-µm effective channel length were fabricated using a single-layer resist process.     

A study of high-speed normally off and normally on Al0.5Ga0.5As heterojunction gate GaAs FET's (HJFET)

The dc, small-signal microwave, and large-signal switching performance of normally off and normally on Al0.5Ga0.5As gate heterojunction GaAs field-effect transistors (HJFET) with submicrometer gate lengths are reported. The structure of both types of devices comprises an n-type 10¹⁷-cm^-3Sn-doped active layer on a Cr-doped GaAs substrate, a p-type 10¹⁸-cm^-3Ge-doped Al0.5Ga0.5As gate layer and a p⁺-type 5 × 10¹⁸-cm^-3Ge-doped GaAs "contact and cap" layer on the top of the gate. The gate structure is obtained by selectively etching the p⁺-type GaAs and Al0.5Ga0.5As. Undercutting of the Al0.5Ga0.5As layer results in submicrometer gate lengths, and the resulting p⁺-GaAs overhang is used to self-align the source and the drain with respect to the gate. Normally off GaAs FET's with 0.5- to 0.7-µm long heterojunction gates exhibit maximum available power gains (MAG) of about 9 dB at 2 GHz. Large-signal pulse measurements indicate an intrinsic propagation delay of 40 ps with an arbitrarily chosen 100-Ω drain load resistance in a 50-Ω microstrip circuit. Normally on FET's with submicrometer gate lengths (∼0.6 µm) having a total gate periphery of 300 µm and a corresponding dc transconductance of 20-30 mmhos exhibit a MAG of 9.5 dB at 8 GHz. The internal propagation delay time measured under the same conditions as above is about 20 ps.     

Ballistic transport and properties of submicrometer Silicon MOSFET's from 300 to 4.2 K

The characteristics of submicrometer silicon MOSFET's have been measured from 300 to 4.2 K, and the mobility versus temperature and carrier velocity versus longitudinal field as a function of temperature have been plotted. Effective mobilities in 500-µm-square devices as high as 25 000 cm²/V . s at 4.2 K have been observed. Mobilities of this magnitude represent mean free path lengths that could lead to ballistic transport in submicrometer devices. Effective mobilities in 0.2-µm devices were only 800 cm²/V . s at 4.2 K due to high-field effects. The mobility versus effective channel length for 0.2-, 0.7-, and 1.7-µm devices operating at drain voltages of 0.1 V has been plotted, and it has been observed that the mobility is greatly reduced in short-channel devices. The mobility versus longitudinal field was studied, resulting in the observation that ballistic transport is inhibited by the high fields in devices operating at 0.1 V. Similar high-field effects should limit the effects of ballistic transport in high-mobility semiconductors such as submicrometer GaAs FET's Operating at nominal supply voltages.     

Two-layer resist structure for electron-beam fabrication of a submicrometer gate length GaAs device

A two-layer resist structure using EBR-9 and PMMA for fabricating a fine metal line with a mushroom-like cross-sectional profile is reported. The structure provides T-shaped resist cavities with undercut profiles using electron-beam exposure. With the optimum developing condition, the bottom opening is as small as 0.1 µm, and the top opening is wide enough not to require an additional exposure in order to obtain a mushroom-like metal lift-off pattern. A Monte Carlo calculation is carried out in order to analyze the profile of the two-layer resist structure, and it is shown that an undercut T-shaped resist profile with a 0.1-µm bottom opening can be obtained using a high-sensitivity resist on a low-sensitivity resist structure. A 0.15-µn mushroom-like lift-off metal profile has been fabricated on a 0.1-µm recessed GaAs substrate by the use of this resist structure.     

Electron-beam fabrication of submicrometer gates for a GaAs MESFET logic

A direct electron-beam lithography is applied to the fabrication of a submicrometer gate for an enhancement-mode GaAs MESFET logic. Exposure doses to produce submicrometer stripes in the positive PMMA resist on a GaAs wafer are investigated for different beam scans of a 0.1-µm-diameter spot. The resist adhesion against a GaAs etchant under the gate recessing is tested to make a fine control of an epitaxial layer thickness with good results. A propagation delay of 64 ps with an associated power consumption of 0.4 mW is obtained with a 0.5 × 20-µm-gate GaAs MESFET, which demonstrates the fastest speed among the enhancement-mode logics.     

Quantitative evaluation of proximity effect in raster-scan exposure system for electron-beam lithography

The proximity effect in a raster-scan for electron-beam lithography system was evaluated by Monte Carlo calculation and verified by experiments. It was revealed that the reduction in the beam diameter below the scanning pitch, which links into the shortening of drawing time, is more effective in decreasing the proximity effect than the reduction in the resist thickness. From the calculated results, it was found that the error in linewidth definition due to the proximity effect was less than 10 percent at a linewidth of 1.5 µm with scanning pitch of 0.5 µm, beam diameter of 0.2 µm, and PMMA resist of 1.0-µm thickness.     

Determination of wavelength and excitation voltage for X-ray lithography

The exposure time of an X-ray lithography system is minimized by the appropriate choice of X-ray wavelength and target excitation voltage, within the constraints of a specified resolution and contrast in the exposed resist pattern. The factors that must be considered in making this choice are the X-ray source brightness of various target materials, the continuum emission spectrum of the target, the wavelength-dependent transmission of the X-ray mask and the vacuum window, and the wavelength-dependent absorption in the resist. The relative exposure time, as a function of wavelength, is predicted for a system using a 25-µm-thick beryllium window and PMMA resist with three choices of mask substrate: 12.5- µm-thick Mylar, 4.0-µm-thick silicon, and 8.5-µm-thick beryllium. A new mask substrate, 0.2-µm-thick aluminum oxide, is presented and shown to be suitable for exposure in vacuum with a 2.5-µm-thick aluminum filter at 13.3-Å wavelength (copper target). X-ray emission spectra from an aluminum target were measured at electron energies of 4.5, 7.9, 10.4, 12.5, 15.5, 19.5, and 28.5 keV. These spectra showed that the continuum radiation contributes little to the degradation of contrast with a gold-on-silicon X-ray mask. Thus a 20-kV electron beam may be used for maximum X-ray production efficiency.