Optimization of mealy automaton logic using programmable logic arrays

Optimization of a two-level microprogrammed automaton is considered. The optimization method is based on equivalent transformation of the automaton, grouping the automaton states into equivalence classes with special encoding.Translated from Kibernetika i Sistemnyi Analiz, No. 5, pp. 180–184, September–October, 1991.     

Principles of logic optimization for a moore microprogrammed automaton

Conclusions  The existence of pseudoequivalent states permits minimizing the length of the direct structural table of the Moore automaton and thus reduces the number of terms in the system of automaton memory excitation functions. Automaton logic optimization requires unique identification of the classes of pseudoequivalent states. Method M₁ identifies the classesB _i ∈ π_ga without using additional variables and states. However, the application of this method does not always reduce the DST to the corresponding parameter of the equivalent Mealy automaton. Moreover, forR > R ₀ the number of feedback parameters in the Moore automaton is greater than in the equivalent Mealy automaton. Method M₂ attains the absolute minimum DST length and the absolute minimum number of feedback variables, which are equal to the corresponding parameters of the equivalent Mealy automaton. Moreover, state encoding can be applied that minimizes the number of terms in the microoperation system. However, M₂ requires the introduction of a special code converter and thus involves additional hardware costs. Translated from Kibernetika i Sistemnyi Analiz, No. 1, pp. 65–72, January–February, 1998.     

SYGRAF: implementing logic programs in a database style

It is shown how Horn logic programs can be implemented using database techniques, namely, mostly bottom-up in combination with certain top-down elements (as opposed to the top-down implementations of logic programs prevailing so far). The proposed method is sound and complete. It easily lends itself to a parallel implementation and is free of nonlogical features like backtracking. As an extension to the common approach to deductive databases, function symbols are allowed to appear in programs, and it is shown that much of database query optimization can be applied to optimize logic programs. An important advantage of present approach is its ability to evaluate successfully many programs that terminate under neither pure top-down nor bottom-up evaluation strategies     

一种1394总线分析逻辑电路的设计与实现

1394总线标准具有灵活、高速和可扩展的特性,为确保新一代航空1394总线系统功能、性能正确性,总线协议符合性及系统应用可靠性,对航空1394总线系统进行系统测试成为必要手段。提出了一种用于1394总线数据分析的逻辑电路,该逻辑电路内嵌于1394分析设备硬件中,可实现1394总线数据和状态的监控、分析和存储,再通过其主机接口读取分析结果。经过1394总线系统的联试、试验及试飞测试任务,充分表明该逻辑电路可有效监控分析1394总线,对于促进航空领域1394总线系统的研制具有重要意义。     

基于CPLD的内燃机车逻辑控制模块的设计

有触点电器控制的内燃机车在实际应用中存在着种种弊端,内燃机车逻辑控制模块采用SOC和现代电力电子技术实现了内燃机车逻辑控制的无触点化,简化了机车控制系统,提高了机车运行的稳定性和可靠性,这也是内燃机车逻辑控制系统的发展趋势.本文分析了内燃机车逻辑控制模块的设计方法,着重介绍了基于SOC技术的系统硬件设计,逻辑控制IP核及CAN网络通信的软件设计,并阐述了整个系统的抗干扰措施.     

基于CPLD的光电编码器快速运算电路设计

主要运用Quartus5．1软件开发平台,利用VHDL语言编程和仿真,基于Altera公司MAX11系列CPLD芯片EPM1270T144C5实现了硬件六十进制压缩BCD码加减运算功能。将设计的CPLD电路应用到光电编码器电路中,实现光电编码器的快速运算,提升了位置检测系统的动态性能指标。详细介绍了电路的原理、设计思路和软件设计,分析了目前设计中的不足之处,提出了部分改进建议。     

Fuzzy logic as a basis for reusing task-based specifications

In this paper, we propose an approach to reusing requirements specification, called task-based specifications in conceptual graphs (TBCG). In TBCG, task-based specification methodology is used to serve as the mechanism to structure the knowledge captured in conceptual models, and conceptual graphs are adopted as the formalism to express requirements specification. TBCG provides several mechanisms to facilitate the reuse of formal specifications: a contextual retrieval mechanism to support context-sensitive specifications retrieval and incremental context acquisition, a graph matching mechanism to compute the similarity between two graphs based on the semantic match and fuzzy logic, and a paraphraser to serve as an explanation mechanism for the retrieval specifications. ©1999 John Wiley & Sons, Inc.     

Description and Reasoning of VLSI circuit in temporal logic

This paper presents a method for describing and reasoning about the behavior of VLSI circuits within the framework of Extended Temporal Logic. For a reasoning method, an “ω-graph approach” is proposed which is useful in verifying the validity of a design. Not only verification but also other reasoning about circuit properties, such as unknown signal identification, can be treated in a unified way by this ω-graph approach. This approach has been studied as a basis of an expert system for the authors’ VLSI CAD system.     

基于CPLD的电子秤逻辑接口设计

借助EDA工具软件设计了一个逻辑控制部件,解决了CPU寻址空间不足、接口功能不全等问题。此基于CPLD的可重构硬件数字平台具有可移植性,使CPU对外接器件近似透明,在更换其他类型CPU后,仅做少量软件和硬件修改即可升级成为新系统。     

LOMACH — a MOS circuit mask checking logic simulator

Logic simulators were originally developed for logic diagram verification. Their use for mask verification is a complex task of logic diagram recognition based on the information gained from masks to be made. The simulator LOMACH is based on the idea that logic states do not propagate through the nodes of a logic diagram but rather through diffusion regions defined directly by the masks. This paper provides postulates governing the logic state wave propagation, and suggests an internal database and algorithms for checking topological correctness and logic function simulation.     

异步时序逻辑电路的分析与设计

异步时序逻辑电路状态的改变必须考虑外部输入信号以及对应存储器的时钟端或控制端有无信号作用,这是分析与设计的一个难点。针对这一难点进行了详细的讨论,通过系统框图给出了分析和设计的一般步骤;总结了分析和设计中对一般问题的解决方法以及应该注意的问题。通过举例验证了该方法的正确性、通用性和快速性。     

演化硬件技术中时序电路的遗传算法实现

本文在讨论了EHW的运行机制的基础上,提出了一种了适合“外进化”方式的可进化的闭环结构,即基于FPGA芯片和QUARTUSⅡ开发工具的EHW平台。详细讨论了如何利用遗传算法实现时序电路,目前演化硬件的研究主要还处于理论分析、演化算法优化、软件模拟的阶段,本文将演化硬件技术应用到时序数字电路的设计中,这对于演化硬件技术及时序数字电路设计来说都是成功的探索。     

基于CPLD的HDB3码编解码电路的设计

HDB3码是基带传输系统中经常采用的传输码型。本文阐述了HDB3码编解码电路的基本原理,在MAX+PLUSⅡ软件平台上,给出了利用复杂可编程逻辑器件设计的HDB3码编解码电路,并进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中,测试结果表明,达到了预期的设计要求。     

Rank of a finite automaton

The notion of rank of a finite automaton is considered. The Cerny—Pin conjecture about the length of terminal words in finite abstract automata is generalized to linear automata.Translated from Kibernetika i Sistemnyi Analiz, No. 3, pp. 3–10, May–June, 1992.     

Optimization of fuzzy logic inference architecture

A fuzzy logic controller architecture that is efficient in both performance and cost is proposed. Optimization of the fuzzy logic circuits is discussed. To speed up the inference process, the defuzzification operation is precomputed, and partial results are stored for runtime uses. Thus, larger memory is traded for better performance. The proposed architecture is less general than previous implementations, but offers better performance and cost     

A primary algorithm for the understanding of logic circuit diagrams

This paper describes a primary algorithm that inputs information of logic circuit diagrams by designers into a computer automatically executing a local area processing. The algorithm tracks signal lines that have thickness using a line sensor. A line sensor detects particular areas such as branches, crosses, L type junctions, logic symbol areas and so on. When the pending signal line is recognized as ending at the output-side of a logic symbol, its input-side is examined precisely and the kind (OR, AND or INVERTER), the numbers of input signal lines and so forth are recognized.     

数字电路基本逻辑运算的硬件语言描述与应用

将现代数字逻辑电路基本逻辑运算采用硬件描述语言描述。本文用Verilog HDL语言描述与运算、或运算和非运算,并给出了应用实例。将数字逻辑运算表示成硬件语言描述,具有格式统一、简洁的作用,便于阅读理解和修改。采用硬件语言描述方法更易于提高数字电路与系统设计能力,加强创新实践活动。     

Joint decomposition of Boolean functions on the basis of a solution of logic equations

It is proposed that the apparatus of logic equations be used to achieve an exact solution of the problem of joint decomposition of a system of Boolean functions with respect to a two-block partitioning of the set of arguments.     

Optimization of digital holographic setup by a fuzzy logic prediction system

In this study, the optimization of the digital holography setup is achieved by a using fuzzy logic prediction system. In fact, when this optimization process is experimentally performed, some parameters are changed in the setup. These parameters affect directly the obtained image quality after a reconstruction process, which is determined by normalized root mean square. The aim of this study is to achieve the optimization of digital holographic setup by using both experimental and fuzzy logic prediction systems. Furthermore, the required time during the experimental optimization can be lowered by using a numerical method like the fuzzy logic prediction system. Here, the experimental optimization results and the optimization results obtained by the fuzzy logic prediction system are compared. It is offered that the designed experimental system can be optimized by using an artificial intelligent tool. The applied fuzzy logic prediction model is used the first time for optimization of hologram recording setup. As a result, it is reached a conclusion that the optimization of digital holographic setup can be numerically performed by the fuzzy logic prediction system. Moreover, while digital holographic setup is experimentally designed, the required time for optimization is reduced, as well.