0.9 V rail-to-rail constant gm CMOS amplifier input stage

Presented is a 0.9 V rail-to-rail constant g_m CMOS amplifier input stage consisting of complementary differential pairs and a g_m control circuit. The g_m control circuit eliminates the g_m dead zone, which occurs in the conventional rail-to-rail amplifier with ultra-low supply voltages. The proposed amplifier input stage has a constant g_m that varies by ±2.3% for rail-to-rail input common-mode levels. To verify the proposed amplifier design, an experimental prototype operational amplifier is also implemented using 0.35 mm standard CMOS technology.     

Analysis of nonlinear behavior of power HBTs

To accurately understand the linear characteristics of a heterojunction bipolar transistor (HBT), we developed an analytical nonlinear HBT model using Volterra-series analysis. The model considers four nonlinear components: r_π, C_diff, C_depl, and g_m. It shows that nonlinearities of r _π and C_diff are almost completely canceled by g _m nonlinearity at all frequencies. The residual g_m nonlinearity is highly degenerated by input circuit impedances. Therefore, r_π, C_diff, C_depl, and g _m nonlinearities generate less harmonics than C_bc nonlinearity. If C_bc is linearized, g_m is the main nonlinear source of HBT, and C_depl becomes very important at a high frequency. The degeneration resistor R_E is more effective than R_B for reducing g_m nonlinearity. This analysis also shows the dependency of the third-order intermodulation (IM3) on the terminations of the source second harmonic impedances. The IM3 of HBT is significantly reduced by setting the second harmonic impedances of Z_S,_2ω2 = 0 and Z_S,_ω2-ω1 = 0     

Constant-gm rail-to-rail CMOS op-amp input stage withoverlapped transition regions

Conventional techniques to achieve a constant-g_m rail-to-rail complementary N-P differential input stage require complex additional circuitry. In addition, the frequency response and common-mode rejection ratio (CMRR) are degraded. An economical but efficient design technique to overcome these problems is proposed. The proposed technique strategically overlaps the transition regions of the tail currents for the n- and p-pairs to achieve constant overall transconductance. Experimental results demonstrate that g_m variation can be restricted to within ±4% with improved CMRR and frequency response     

A gm/ID based methodology for the design ofCMOS analog circuits and its application to the synthesis of asilicon-on-insulator micropower OTA

A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation between the ratio of the transconductance over DC drain current g_m/I_D and the normalized current I_D/(W/L). The g_m/I_D indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models. The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA)     

Optimization of active channel thickness of mm-wavelength GaAsMESFETs by using a nonlinear I-V model

To improve the performance of submicron GaAs MESFETs, an optimum value of active channel thickness, a is required. An algorithm has been developed to simulate the effects of a on the device characteristics. It has been observed that the ratio between output conductance and transconductance (g_d/g_m) increases with increasing values of α. The data suggest that this could be attributed to the fact that by increasing a, the magnitude of drain-to-source current, I _ds increases, and as a result there are more uncovered ionic charges in the space charge region toward the drain-side of the gate. The access charge density at the drain-side of the depletion induces opposite charges in the gate electrode. Consequently, it gives forward biasing to the Schottky barrier gate which increases with increasing values of I_ds. As a result, the modulation of channel current due to the applied gate potential becomes less effective and the ratio g _d/g_m increases as a function of α. The technique developed could be a very useful tool for the simulation of large scale integrated circuitry involving submicron GaAs MESFETs     

基于gm/Id参数的CMOS运算放大器设计重用方法

模拟电路的设计重用是提高模拟与混合信号集成电路设计效率的重要途径.本文提出了一种基于g_m/I_d参数的不同工艺之间同一结构电路的设计移植方法.方法的基本思想是保持移植前后电路中部分关键MOS管的g_m/I_d参数,从而使移植后电路的性能也基本保持不变.介绍了基于BSIM等模型的g_m/I_d匹配及移植电路参数确定方法.给出了一个Miller补偿两级运放及一个折叠共源共栅运放从0.35μm工艺到0.18μm、0.13μm、90nm工艺的移植仿真结果.与现有方法相比,本文方法可以更小的计算代价,得到性能基本相同、但功耗与面积缩减的电路.     

Automatic Scaling Procedures for Analog Design Reuse

In this paper, a methodology for analog design reuse is proposed. The basic idea is to keep the circuit topology unchanged while automatically modifying the MOSFETs aspect ratio in order to control the transistor transconductances g_m and output conductances g_DS. If g_m's and gDS's of each transistor are kept unchanged through the scaling procedure, we show that the overall frequency behavior of the scaled circuit remains very similar to the original one. The approach is very simple and it is suitable for the scaling of analog circuits. No input and output terminals have to be defined and it can be straightforwardly implemented in an automatic scaling tool. When this approach fails, more complex iterative numerical loops may be adopted. In order to validate and compare the scaling approaches, several linear and nonlinear circuits were scaled from a 0.25-mum, 2.5-V voltage supply to a 0.15-mum, 1.2-V voltage supply in standard CMOS technologies     

Physical model of drain conductance, gd, degradation ofNMOSFET's due to interface state generation by hot carrierinjection

Degradation of analog device parameters such as drain conductance, g_d, due to hot carrier injection has been modeled for NMOSFET's. In this modeling, mobility reduction caused by interface state generation by hot carrier injection and the gradual channel approximation were employed. It has been found that g_d degradation can be calculated from linear region transconductance, g_m, degradation which is usually monitored for hot carrier degradation of MOSFET's. The values of g_d degradation calculated from g_m degradation fit well to the measured values of g_d degradation The dependence of the g_d degradation lifetime on L_eff has been also studied, this model also provides an explanation of the dependence on L_eff. The model is then useful for lifetime predictions of analog circuits in which g_d degradation is usually more important than g_m degradation     

Recessed-gate AlGaAs-InGaAs-GaAs pseudomorphic HEMT withSi-planar-doped etch stop layer

An improved slot etch technique based on an Si planar doped layer has been applied to gate recessing in the fabrication of AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors (HEMTs). The devices exhibited comparable g_m with much better breakdown and leakage behaviour than conventional pseudomorphic HEMT devices     

Switching characteristics of an optically controlled GaAs-MESFET

The switching characteristics of an optically controlled Metal Semiconductor Field Effect Transistor (MESFET), popularly known as Optical Field Effect Transistor (OPFET), have been derived analytically. The limitations of the existing model have been overcome in the present model. Calculations are being carried out to examine the effect of illumination on the current-voltage characteristics, drain-to-source capacitance (C_dc), internal gate-to-source capacitance (C_gs), drain-to-source resistance (R_ds), the transconductance (g_m), the input RC time constant and the cutoff frequency (f_T) of a GaAs-MESFET. The variations of these parameters with gate length L_g and the doping concentration N_d have also been studied in dark and illuminated conditions. The results of numerical calculations show that there is an overall decrease in the input RC time constant of the device in the illuminated condition arising from the internal gate-to-source capacitance and the transconductance. The results obtained on the basis of the model show a close agreement with the reported experimental findings. The simple model presented here is fairly accurate and can be used as a basic tool for circuit simulation purposes     

Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation

In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time. Analog/RF figures of merit of SNWTs are studied, including transconductance efficiency g_m/I_d, intrinsic gain g_m/g_d, cutoff frequency f_t , and maximum oscillation frequency f_max. The results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog/RF applications. The impact of nanowire cross-sectional shape fluctuation that is caused by process variation is studied and found to be relatively severe, and the acceptable variation tolerance for RF integrated circuit design is given     

AlGaN/GaN HEMTs on a (001)-Oriented Silicon Substrate Based on 100-nm SiN Recessed Gate Technology for Microwave Power Amplification

AlGaN/GaN high-electron mobility transistors on (001)-oriented silicon substrates with a 0.1-mum gamma-shaped gate length are fabricated. The gate technology is based on a silicon nitride (SiN) thin film and uses a digital etching technique to perform the recess through the SiN mask. An output current density of 420 mA/mm and an extrinsic transconductance g_m of 228 mS/mm are measured on 300-mum gate-periphery devices. An extrinsic cutoff frequency f_t of 28 GHz and a maximum oscillation frequency f_max of 46 GHz are deduced from S-parameter measurements. At 2.15 GHz, an output power density of 1 W/mm that is associated to a power-added efficiency of 17% and a linear gain of 24 dB are achieved at V_DS = 30 V and V_GS = -1.2 V.     

Velocity saturation in the extrinsic device: a fundamental limit inHFET's

We have carried out an experimental study revealing that velocity saturation (υ_sat) occurring in both the extrinsic source and drain sets a fundamental limit on maximum drain current and useful gate swing in HFET's. Using AlGaAs/n⁺-InGaAs HFET's as a vehicle, we find that first g_m and eventually f_T decline at high currents in two stages. Initially, the approach of υ_sat in the extrinsic device causes the small-signal source and drain resistances (r_s and r_d) to rise dramatically, primarily degrading g_m. As the current increases further, the large-signal source and drain resistances (R_s and R_d) grow significantly as well, pushing the intrinsic HFET toward the linear regime. Combined with the rapid rise of r_s and r_d, the accompanying increase in gate-drain capacitance forces f_T to decline through a strongly enhanced Miller effect. We associate this two-fold mechanism with a new regime of HFET operation, which we call the parasitic-resistance blow-up regime     

Selective gate recess etching of GaInAs/AlInAs based HEMTs using aCH4/H2 plasma without subsequent annealing

A methane hydrogen plasma has been used to define gate recesses through a polymer mask selectively on GaInAs/InAlAs based HEMT devices. No subsequent annealing was necessary and the devices exhibited comparable g_m and i_dss values with much better uniformity than conventional wet etched devices     

Features and mechanisms of the saturating hot-carrier degradationin LDD NMOSFETs

Propagation of defects from the sub-spacer region to the gate-overlapped LDD region in NMOSFETs is modeled using measurements and 2-D device simulation. It is argued that the saturation of degradation is caused by the saturating nature of this degradation length, as opposed to decreasing lateral electric field maxima (E_m) or increasing barrier height (φ_it) to defect creation. Two stage hot-carrier degradation was observed in our LDD NMOSFETs. The early mode (1000-3000 s) of the degradation is characterized by a sharp rate of degradation of the linear transconductance (g_m), and a reduction in the substrate current (I_B). In order to locate and quantify defects produced in this early mode degradation phase, we use the results of a combination of the floating gate technique and simultaneous measurements of the reverse (source and drain interchanged) saturation g_m's. These results help us build a 2-D simulation framework involving trapped negative charges in the oxide in the drain-side gate-edge region, partly under the gate and partly in the spacer region. We then use 2-D simulation and other measurements such as linear and saturation current degradation, I_B degradation, and charge pumping to confirm the location of the defects and help estimate their quantity. Simulation results also help us build an analytical model for defect propagation from the early mode to the late mode. The analytical model is seen to explain many features of the saturating nature of hot-carrier degradation     

Low-frequency noise properties of dynamic-threshold (DT) MOSFET's

This paper shows that MOSFET operated in dynamic-threshold (DT) mode (V_body=V_gate) is more suitable for low-noise RF/analog applications than those operated in conventional mode (V_body=V_source). Detailed low-frequency noise properties of these two modes of device operation were compared for 0.31-μm gate MOSFET's, in which NMOS's are surface-channel devices (S.C.) and PMOS's are buried-channel (B.C.) devices. Experimental data show that when the devices are biased at same transconductance, the low-frequency noise in DT mode is 30 times lower (at g_m=2.2×10^-3 S) than that in the conventional mode for the B.C. devices and ten times (at g_m=2.0×10 ^-3 S) lower for the S.C. devices     

Subthreshold Performance of Dual-Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications

Analog circuits based on the subthreshold operation of CMOS devices are very attractive for ultralow power, high gain, and moderate frequency applications. In this paper, the analog performance of 100 nm dual-material gate (DMG) CMOS devices in the subthreshold regime of operation is reported for the first time. The analog performance parameters, namely drain-current (I_d), transconductance (g_m), transconductance generation factor (g_m/I_d), early voltage (V_A), output resistance (R_o) and intrinsic gain for the DMG n-MOS devices, and and for the DMG p-MOS devices are systematically investigated with the help of extensive device simulations. The effects of different capacitances on the unity-gain frequency are also studied. The DMG CMOS devices are found to have significantly better performance as compared to their single-material gate (SMG) counterpart. More than 70% improvement in the voltage gain is observed for the CMOS amplifiers when dual-material gates, instead of single-material gates, are used in both the n- and p-channel devices.     

Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly C_gb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (I_dsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (g_m) degradation and, eventually, cutoff frequency (f_T) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. f_T is largely affected by local stress change, i.e., g_m degradation at minimal gate poly (GP) pitch and gate-to-active spacing, f_T is dominated by increased parasitic capacitance (C_gb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in f_T has been observed through layout optimization for C_gb reduction by increasing the transistor active-to-SC spacing.     

An AlGaAs/InGaAs pseudomorphic HEMT modulator driver IC with lowpower dissipation for 10-Gb/s optical transmission systems

An optical modulator driver integrated circuit (IC) has been developed for 10-Gb/s optical communication systems. To achieve both high-frequency (HF) operation and low power dissipation, 0.2-μm T-shaped gate AlGaAs/InGaAs pseudomorphic high electron-mobility transistors (HEMTs) have been employed for their large transconductance g_m of 610 mS/mm and high cutoff frequency f_T of 67.5 GHz. In addition, optimizing input logic swing, switching transistor size in the output driver, and using cascode-current mirror circuits with small output conductance enable power dissipation as low as 1 W to be achieved at a 10-Gb/s nonreturn-to-zero (NRZ) signal output with 3 V_p._p. This is the lowest value ever reported for power dissipation. As an additional function, the output-voltage swing can be controlled in the range from 2 to 3.3 V_p._p. by the current mirror circuit for the purpose of adjusting the optical-output-signal duty factor through an optical modulator     

A tunable pulse-shaping filter for use in a nuclear spectrometersystem

A pulse-shaping filter for use in a nuclear spectrometer system is described. The filter is designed using tunable g_m blocks in order to allow for an adjustable peaking time. Fully differential structures are employed to achieve sufficient pulse height linearity