Extended baseline architecture for nonblocking photonic switching

A new switch architecture called extended baseline networks (EBN) is proposed for nonblocking photonic switching. This switch is a space-division multistage network using 2×2 optical switch elements which may be directional couplers fabricated on titanium diffused lithium niobate (Ti:LiNbO₃) substrates. A recursive definition for the proposed architecture is presented. Some properties including the number of switch elements required, blocking characteristics, number of crossovers, system attenuation, and signal-to-noise ratio (SNR) are derived and analyzed. Most of the characteristics are shown to be better than those of other well-known networks fabricated on single Ti:LiNbO₃ substrates     

An improved systolic architecture for 2-D digital filters

An improved systolic architecture for two-dimensional infinite-impulse response (IIR) and finite-impulse-response (FIR) digital filters is presented. Comparisons with recently published work are made. When compared with the architecture of M.A. Sid-Ahmed (1989), a substantial reduction in the number of delay elements is observed. This reduction is of the order of 10² for a 2-D IIR filter and equals N+1 for an Nth-order 2-D FIR filter. The clock period has been made independent of the order of the filter. The speed-up factor is the maximum achievable and is independent of the filter order. Comparison with the work of S. Sunder et al. (1990) shows an improvement in the latency of the systolic array, which has been reduced from 1 to 0. A reduction of N+1 delay elements has been achieved for the FIR filter. An error analysis for the architecture is made     

A Low-Cost Serial Decoder Architecture for Low-Density Parity-Check Convolutional Codes

We propose a low-cost serial decoder architecture for low-density parity-check convolutional codes (LDPC-CCs). It has been shown that LDPC-CCs can achieve comparable performance to LDPC block codes with constraint length much less than the block length. The proposed serial decoder architecture for LDPC-CCs uses a single decoding processor. Terminated data frames are sent through the processor iteratively until correctly decoded or a maximum number of iterations is reached. This architecture saves memory consumption and uses a very small number of logic elements, making it especially suitable for strong LDPC-CCs with large code memory. The proposed architecture is realized for a (2048,3,6) regular LDPC-CC on an Altera Stratix FPGA. With a maximum of 100 iterations, the design achieves up to 9-Mb/s throughput using only a very small portion of the field-programmable gate array resources.      

Traffic Shaping for Resource-Efficient In-Vehicle Communication

In-vehicle communication has become complex and costly due to the growing number of automotive network systems applied for different data types. In this work, our previously proposed in-vehicle network architecture that is based on Internet Protocol (IP) and full-duplex switched Ethernet (IP/Ethernet) is further investigated for real-time audio and video streaming. Quality-of-service (QoS) and resource usage are analyzed for selected IP/Ethernet-based network topologies. Traffic shaping is used to reduce the required network resources and consequently the cost. A novel traffic shaping algorithm is presented that outperforms other traffic shapers in terms of resource usage when applied to variable bit rate video sources in the proposed double star topology. In addition, a new architecture design is introduced for traffic shaper implementation in switches which operates on a per stream basis. Analytical and simulation results confirm that the proposed network architecture with traffic shaping is well-adapted for in-vehicle communication.      

COD: alternative architectures for high speed packet switching

Architectures for packet switches are approaching the limit of electronic switching speed. This raises the question of how best to utilize advances in photonic technology to enable higher speeds. The authors introduce cascaded optical delay line (COD) architectures. The COD architectures utilize an extremely simple distributed electronic control algorithm to configure the states of 2×2 photonic switches and use optical fiber delay lines to temporarily buffer packets if necessary. The simplicity of the architectures may also make them suitable for “lightweight” all-electronic implementations. For optical implementations, the number of 2×2 photonic switches used is a significant factor determining cost. The authors present a “baseline” architecture for a 2×2 buffered packet switch that is work conserving and has the first-in, first-out (FIFO) property. If the arrival processes are independent and without memory, the maximum utilization factor is ρ, and the maximum acceptable packet loss probability is ϵ, then the required number of 2×2 photonic switches is O(log(ϵ)/log(γ)), where γ=ρ²/(ρ²+4-4ρ). If one modifies the baseline architecture by changing the delay line lengths then the system is no longer work conserving and loses the FIFO property, but the required number of 2×2 photonic switches is reduced to O(log[log(ϵ)/log(γ)]). The required number of 2×2 photonic switches is essentially insensitive to the distribution of packet arrivals, but long delay lines are required for bursty traffic     

A new architecture and a new metric for lightwave networks

The notion of a logically routed network was developed to overcome the bottlenecks encountered during the design of a large purely optical network. In the last few years, researchers have proposed the use of torus. Perfect shuffle, hypercube, de Bruijn graph, Kautz graph, and Cayley graph as an overlay structure on top of a purely optical network. All these networks have regular structures. Although regular structures have many virtues, it is often difficult in a realistic setting to meet these stringent structural requirements. In this paper, we propose generalized multimesh (GM), a semiregular structure, as an alternate to the proposed architectures. In terms of simplicity of interconnection and routing, this architecture is comparable to the torus network. However, the new architecture exhibits significantly superior topological properties to the torus. For example, whereas a two-dimensional (2-D) torus with N nodes has a diameter of Θ(N^0.5), a generalized multimesh network with the same number of nodes and links has a diameter of Θ(N^0.25). In this paper, we also introduce a new metric, flow number, that can be used to evaluate topologies for optical networks. For optical networks, a topology with a smaller flow number is preferable, as it is an indicator of the number of wavelengths necessary for full connectivity. We show that the flow numbers of a 2-D torus, a multimesh, and a de Bruijn network, are Θ(N^1.5), Θ(N^1.25), and Θ(N log N), respectively, where N is the number of nodes in the network. The advantage of the generalized multimesh over the de Bruijn network lies in the bet that, unlike the de Bruijn network, this network can be constructed for any number of nodes and is incrementally expandable     

A system for systolic modules for the MUSIC algorithm

The authors believe that special-purpose architectures for digital signal processing (DSP) real-time applications will use closely coupled processing elements as array processor modules to implement the various portions of the new algorithms, and several such modules will cooperate in a pipelined manner to implement complete algorithms. Such an architecture, based upon systolic modules, for the MUSIC algorithm is presented. The architecture is suitable for VLSI implementation. The throughput of the pipelined approach is O(N), whereas the sequential approach is O(N³)     

Model for autonomous agents in machine‐to‐machine navigation networks

Machine‐to‐machine (M2M) is an evolving architecture and tends to provide enormous services through the swarm presence of the networked devices. Localization is one of those services. Previous localization techniques require complex computation that is not suitable and affordable in such architecture. Moreover, integrating intelligent multiagents on these ubiquitous devices makes the network more independent and reactive requiring for a less complex localization model. This paper reviews the present localization techniques and discusses their infeasibility for M2M communication while proposing a mathematical model that is derived from Anderson model for the distributed structure of machine‐type‐communication network involving autonomous agents. This paper has made an attempt to use the property of Anderson model that structures the distributed objects. This paper also classifies autonomous agents according to their functionalities in a navigational network. Recently, Anderson model have been customized for implication of optical communication; in this paper, the proposed mathematical model involves intelligent agents for localization that aim to reduce complexity of positioning computations for nodes having restricted computational resources and battery life, which are the main characteristics of M2M communication.     

Architectural analysis of multiple fiber ring networks employingoptical paths

Analyzes the performance of various types of multiple fiber ring networks employing optical paths (OP's). The multiple fiber ring network architecture is suitable for achieving failure resilient networks that have extremely large bandwidth but are still upgradable against future increases in traffic. This architecture will overcome the limitation of conventional WDM rings in terms of network expansion capabilities, the number of nodes within the ring, and the number of OP's accommodated in the network. The generic node architecture suitable for multiple fiber ring networks is presented and functionality requirements are identified. The OP accommodation design algorithms that minimize the required node system scale are proposed. Based on the generic node architecture and proposed OP accommodation design algorithms, we evaluated the performance of several types of multiple fiber rings in terms of the required node system scale for rings under various conditions. The effect of the ring architecture (uni-/bidirectional rings), optical path schemes (wavelength path/virtual wavelength path), and different node connectivity patterns are demonstrated for the first time. The obtained results elucidate the criteria for selecting the most suitable multiple fiber ring architecture     

An area-efficient topology for VLSI implementation of Viterbidecoders and other shuffle-exchange type structures

A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required for interconnection. The processing elements are implemented in pairs that are connected to form a ring. In this way three-quarters of the interconnections are between neighbors. The ring structure is laid out in two columns and the interconnection of nonneighbors is routed in the channel between the columns. The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2-μm CMOS process using MOSIS-like simplified design rules. The chip operates at speeds up to 19 MHz under worst-case conditions (V_DD=4.75 V and T_A=70°C). The core of the chip (excluding pad cells) is 7.8×5.1 mm² and contains approximately 50000 transistors. The interconnection network occupies 32% of the area     

Neural scheduling algorithms for time-multiplex switches

In an N×N time-multiplex switch, transmission conflict arises when two or more input adaptors transmit packets to the same output adaptor simultaneously. To resolve transmission conflict, we propose two neural-based scheduling algorithms which use a large number of simple processing elements to perform scheduling in parallel. The first algorithm uses N² hysteresis McCulloch-Pitts (1943) neurons to determine conflict-free transmission schedules with maximum throughput. The second algorithm resolves transmission conflict among the first M packets in each input queue. It determines suboptimal transmission schedules using only NM neurons (M2=250000 to NM=5000     

Design and Implementation of a Field Programmable CRC Circuit Architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s.      

A New Architecture for Nonblocking Optical Switching Networks

With the current technology, all-optical networks require nonblocking switch architectures for building optical cross-connects. The crossbar switch has been widely used for building an optical cross-connect due to its simple routing algorithm and short path setup time. It is known that the crossbar suffers from huge signal loss and crosstalk. The Clos network uses a crossbar as building block and reduces switch complexity, but it does not significantly reduce signal loss and crosstalk. Although the Spanke's network eliminates the crosstalk problem, it increases the number of switching elements required considerably (to 2N ² - 2N). In this paper, we propose a new architecture for building nonblocking optical switching networks that has much lower signal loss and crosstalk than the crossbar without increasing switch complexity. Using this architecture we can build non-squared nonblocking networks that can be used as building block for the Clos network. The resulting Clos network will then have not only lower signal loss and crosstalk but also a lower switch complexity.     

Architecture design for ATM statistical multiplexers

Both high-speed packet switches and statistical multiplexers are critical elements in the ATM (asynchronous transfer mode) network. Many switch architectures have been proposed and some of them have been built, but relatively fewer statistical multiplexer architectures have been investigated to date. It has been considered that multiplexers are a special kind of switches which can be implemented with similar approaches. The main function of a statistical multiplexer, however, is to concentrate traffic from a number of input ports to a comparatively smaller number of output ports; ‘switching’ in the sense that a cell must be delivered to a specific output port is often not required. This implies that the channel grouping design principle, in which more than one path is available for each virtual circuit connection, can be applied in the multiplexer. We show that this technique reduces the required buffer memory and increases the system performance significantly. The performances of three general approaches for implementing an ATM statistical multiplexer are studied through simulations with various bursty traffic assumptions. Based on the best performing approach (sharing output channels and buffers), we propose two architecture designs to implement a scalable statistical multiplexer that is modularly decomposed into many smaller multiplexers by using a novel grouping network.     

A General Neural Network Model for Estimating Telecommunications Network Reliability

This paper puts forth a new encoding method for using neural network models to estimate the reliability of telecommunications networks with identical link reliabilities. Neural estimation is computationally speedy, and can be used during network design optimization by an iterative algorithm such as tabu search, or simulated annealing. Two significant drawbacks of previous approaches to using neural networks to model system reliability are the long vector length of the inputs required to represent the network link architecture, and the specificity of the neural network model to a certain system size. Our encoding method overcomes both of these drawbacks with a compact, general set of inputs that adequately describe the likely network reliability. We computationally demonstrate both the precision of the neural network estimate of reliability, and the ability of the neural network model to generalize to a variety of network sizes, including application to three actual large scale communications networks.      

A vision for residential broadband services: ATM-to-the-home

The arrival of asynchronous transfer mode (ATM) networks has enabled a wide range of new interactive multimedia applications for the residential market. The article presents a vision for supporting universal residential broadband services based on an ATM-to-the-home (ATTH) network architecture. This network architecture applies to the various residential access network (RAN) architectures being deployed today, such as hybrid fiber/coax (HFC), fiber-to-the-curb (FTTC), fiber-to-the-home (FTTH), and asymmetric digital subscriber loop (ADSL) technologies. The article addresses today's residential networks and applications, to understand why a switched broadband residential network is required to support residential broadband services. After exploring residential broadband application requirements, a new class of service is proposed to support a very important class of residential broadband applications that has been not addressed. Then, the technical and strategic motivations for using the ATTH architecture are discussed in detail. A universal model for residential broadband network architecture based on ATTH is described, which is shown to apply to various RAN architectures. Finally, it discusses the signaling requirements of residential broadband services and explain why the ATM multiconnection per-call model is much more efficient than the digital stored media command and control (DSM-CC) session control protocol approach for the ATTH architecture     

A 0.8nV/√Hz CMOS preamplifier for IC-magneto-resistive readelements

The first CMOS preamplifier IC for magnetoresistive (MR) read elements for use in state-of-the-art tape drives is presented. The circuit's noise performance of 0.8 nV/√Hz includes noise contributions from both the amplifier and the integrated current source needed to bias the MR elements. It will be shown that a single-ended input architecture is highly attractive for MR preamps because it offers advantages such as lowest noise levels and substantially reduced power and area consumption. Also, a current-mode amplifier (CMA) has been developed to enhance the preamp's bandwidth, large-signal capability and PSRR. The quad preamp has been implemented in a 1.2 μm CMOS process and measures 4.5×4.24 mm²     

Neural net nonlinear prediction for speech data

A new, nonlinear, neural network based predictor has been devised fro the encoding of speech data. It may be used in the design of a differential pulse code modulation (DPCM) coder for speech. A hybrid neural network architecture has been employed which combines the perceptron and backpropagation paradigms, thus called the PB-hybrid (PBH). Only two neurons are needed in the backpropagation section, keeping the required overhead modest. This predictor is designed by supervised training, based on a typical sequence of digitised values of samples in a speech frame. Simulation experiments have been carried out using 15 ms frames of 16 kHz speech data. The results obtained for the prediction gain show a 3 dB advantage of the PBH network over the linear predictor.<>     

Reduced banyan-type multiplane rearrangeable switching networks

The new concept of the multiplane rearrangeable switching network is presented. The new switching network's architecture is based on the well-known baseline network (the log₂(N, 0, 1) switching network). This new architecture can easily be obtained from the baseline network by the removal of some switching elements. It is therefore called the reduced baseline switching network and is denoted by log^r ₂((N, 0, 1). The new multiplane rearrangeable reduced baseline switching network requires fewer switching elements and crosspoints than the multiplane switching network which is based on the plain baseline network.     

A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS

We have developed an H.264/MPEG-4 dual video codec IP for mobile applications such as digital still cameras (DSCs), digital video cameras (DVCs), and mobile phones. The codec is capable of encoding and decoding HD-sized moving pictures (1280 pixels by 720 lines at 30 fps) in real-time at an operating frequency of 144 MHz, and SD-sized pictures at 54 MHz. We have implemented our original architecture based on a macroblock-level pipeline method and encoding algorithms suitable for the architecture in the codec, which enable low power of 64 mW for HD encoding with high picture quality equivalent to that of the H.264 reference encoder “JM (Joint Model)”.