A CMOS 5-V analog front end for 9600-bit/s facsimile modems

A CMOS 9600-b/s facsimile-modem analog front end was designed with the consideration that it be capable of being fabricated on the same chip with digital signal processing circuits. To achieve the dynamic range required in the high-speed QAM (quadrature amplitude modulation) modem environment with a single 5-V power supply, a fully differential architecture is used. The die area is 23 kmil/SUP 2/ and the power consumption is only 35 mW. The experimental results show that 76-dB dynamic range is achieved from the fully differential bandpass filter. The zero crossing detector in the MF-1 detection block can normally operate with -50-dBm input signal.     

A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS

A single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 /spl mu/W under 1-V supply voltage and the chip core size is 0.18 mm/sup 2/.     

基于BLF时钟的RFID低功耗数字基带设计

提出了一种符合ISO/IEC 18000-6C协议中关于时序规定的射频识别(RFID)无源标签芯片低功耗数字基带处理器的设计.基于采用模拟前端反向散射链路频率(BLF)时钟的方案,将BLF的二倍频设置为基带中的全局时钟,构建BLF和基带数据处理速率之间的联系;同时在设计中采用门控时钟和行波计数器代替传统计数器等低功耗策略.芯片经TSMC 0.18 μmCMOS混合信号工艺流片,实测结果表明,采用该设计的标签最远识别距离为7 m,数字基带动态功耗明显降低,且更加符合RFID协议的要求.     

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.     

A high-efficiency CMOS +22-dBm linear power amplifier

Modern wireless communication systems require power amplifiers with high efficiency and high linearity. CMOS is the technology of choice for complete systems on a chip due to its lower costs and high integration levels. However, it has always been difficult to integrate high-efficiency power amplifiers in CMOS. In this paper, we present a new class of operation (parallel A&B) for power amplifiers that improves both their dynamic range and power efficiency. A prototype design of the new amplifier was fabricated in a 0.18-/spl mu/m CMOS technology. Measurement results show a PAE that is over 44% and the measured output power is +22 dBm. In comparison to a normal class A amplifier, this new design increases the 1-dB compression point (P1dB) by over 3 dB and reduces dc power consumption by over 50% within the linear operating range.     

A Low-Power Wide-Dynamic-Range Analog VLSI Cochlea

Low-power wide-dynamic-range systems are extremely hard to build. The biological cochlea is one of the most awesome examples of such a system: It can sense sounds over 12 orders of magnitude in intensity, with an estimated power dissipation of only a few tens of microwatts. In this paper, we describe an analog electronic cochlea that processes sounds over 6 orders of magnitude in intensity, and that dissipates 0.5 mW. This 117-stage, 100 Hz to 10 KHz cochlea has the widest dynamic range of any artificial cochlea built to date. The wide dynamic range is attained through the use of a wide-linear-range transconductance amplifier, of a low-noise filter topology, of dynamic gain control (AGC) at each cochlear stage, and of an architecture that we refer to as overlapping cochlear cascades. The operation of the cochlea is made robust through the use of automatic offset-compensation circuitry. A BiCMOS circuit approach helps us to attain nearly scale-invariant behavior and good matching at all frequencies. The synthesis and analysis of our artificial cochlea yields insight into why the human cochlea uses an active traveling-wave mechanism to sense sounds, instead of using bandpass filters. The low power, wide dynamic range, and biological realism make our cochlea well suited as a front end for cochlear implants.     

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

This paper presents a full-CMOS transmitter and receiver for 2.0-GHz wide-band code division multiple access with direct conversion mixers and a DC-offset cancellation scheme. The direct conversion scheme combined with a multiphase sampling fractional-N prescaler alleviates the problems of the direct conversion transmitter and receiver. Digital gain control is merged into the baseband filters and variable-gain amplifiers to optimize the linearity of the system, reduce the noise, and improve the sensitivity. Variable-gain amplifiers with DC-offset cancellation loop eliminate the DC-offset in each stage. The chip implemented in 0.35-/spl mu/m CMOS technology shows the experimental results of 6 dBm maximum output power with 38-dB adjacent channel power rejection ratio at 1.92 MHz, 50-dB dynamic range, and 363-mW power consumption in the transmitter. The receiver shows -115.4 dBm sensitivity, a 4.0-dB noise figure, and a dynamic range of 80-dB with 396-mW power consumption.     

A micropower dry-electrode ECG preamplifier

This paper describes the development of a very low-power preamplifier intended for use in pasteless-electrode recording of the human electrocardiogram. The expected input signal range is 100 microV-10 mV from a lead-II electrode configuration. The amplifier provides a gain of 43 dB in a 3-dB bandwidth of 0.05 Hz-2 kHz with a defined high input impedance of 75 M omega. It uses a driven common electrode to enhance rejection of common-mode interfering signals, including low-frequency motion artifact, achieving a common-mode rejection ratio (CMRR) of better than 80 dB over its entire bandwidth. The gain and phase characteristics meet the recommendations of the American Heart Association, ensuring low distortion of the output ECG signal and making it suitable for clinical monitoring. The amplifier has a power consumption of 30 microW operating from a 3.3-V battery and is intended for use in small, lightweight, portable electrocardiographic equipment and heart-rate monitoring instrumentation.     

A 110-MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function

This paper describes a CMOS programmable gain amplifier (PGA) that maintains a 3-dB bandwidth greater than 110 MHz and can provide an 84-dB gain control range with 1-dB step resolution. The PGA can also be operated in a low-power mode with 3-dB bandwidth greater than 71 MHz. Integrated with this PGA is a CMOS successive logarithmic detecting amplifier with a /spl plusmn/0.7-dB logarithmic accuracy over an 80-dB dynamic range. It achieves -83-dBm sensitivity and consumes 13 mA from a single 3-V supply in the normal power mode. The chip area, including pads, occupies 1.5/spl times/1.5 mm/sup 2/.     

Hearing with bionic ears [cochlear implant devices]

According to speech perception-rate data continuous interleaved sampling (CIS) and spectral maxima sound processor (SMSP) techniques are, and probably will be, the best speech processing strategies for multichannel electrode cochlear implant devices. From packaging and power-consumption viewpoints, today's speech processing systems are very big and are, therefore, worn on the body and consume large electric power. Next-generation cochlear implant devices would be more compact, low-power products that would be worn behind or in the ear. It is clear that mixed-signal, high-density, and low-power design techniques are required to satisfy compactness, as well as low-power consumption features to realize intelligent speech sensation for the implantees. The especially critical design consideration of power supply lifetime and efficiency might be increased by using new promising technologies like microelectromechanical systems (MEMS)     

A 77 GHz mHEMT MMIC Chip Set for Automotive Radar Systems

A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 µm gate‐length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4‐inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2 mm × 2 mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1 mm × 2 mm. The frequency doubler achieved an output power of –6 dBm at 76.5 GHz with a conversion gain of ?16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2 mm × 1.2 mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W‐band.     

Micropower circuits for bidirectional wireless telemetry in neural recording applications

State-of-the art neural recording systems require electronics allowing for transcutaneous, bidirectional data transfer. As these circuits will be implanted near the brain, they must be small and low power. We have developed micropower integrated circuits for recovering clock and data signals over a transcutaneous power link. The data recovery circuit produces a digital data signal from an ac power waveform that has been amplitude modulated. We have also developed an FM transmitter with the lowest power dissipation reported for biosignal telemetry. The FM transmitter consists of a low-noise biopotential amplifier and a voltage controlled oscillator used to transmit amplified neural signals at a frequency near 433 MHz. All circuits were fabricated in a standard 0.5-microm CMOS VLSI process. The resulting chip is powered through a wireless inductive link. The power consumption of the clock and data recovery circuits is measured to be 129 microW; the power consumption of the transmitter is measured to be 465 microW when using an external surface mount inductor. Using a parasitic antenna less than 2 mm long, a received power level was measured to be -59.73 dBm at a distance of one meter.     

A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-/spl mu/m CMOS

We have developed a complete single-chip GPS receiver using 0.18-/spl mu/m CMOS to meet several important requirements, such as small size, low power, low cost, and high sensitivity for mobile GPS applications. This is the first case in which a radio has been successfully combined with a baseband processor, such as SoC, in a GPS receiver. The GPS chip, with a total size of 6.3 mm /spl times/ 6.3 mm, contains a 2.3 mm /spl times/ 2.0 mm radio part, including RF front end, phase-locked loops, IF functions, and 500 K gates of baseband logic, including mask ROM, SRAM, and dual port SRAM . It is fabricated using 0.18-/spl mu/m CMOS technology with a MIM capacitor and operates from a 1.6-2.0-V power supply. Experimental results show a very low power consumption of, typically, 57 mW for a fully functional chip including baseband, and a high sensitivity of -152dBm. Through countermeasures against substrate coupling noise from the digital part, the high sensitivity was successfully achieved without any external low-noise amplifier.     

A "divide and conquer" technique for implementing wide dynamic range continuous-time filters

This paper presents a technique for implementing analog filters with wide dynamic range and low power dissipation and chip area. The desired dynamic range of the filter is divided into subranges, each covered by a different filtering path optimized specifically for this subrange. This results in small admittance levels for the individual filtering paths and correspondingly small power dissipation and chip area. The system provides undisturbed output during range switching, contrary to conventional automatic gain control (AGC)/filter arrangements that generate disturbances every time the gain of the AGC changes. We also report on a low-noise highly linear CMOS transconductor useful for high-frequency applications. A chip implementing the ideas of this paper was fabricated in a 0.25-/spl mu/m digital CMOS process. The intended application of the filter is channel selection in an 802.11a/Hiperlan2 Wireless Ethernet receiver. The chip dissipates 9 mA, occupies an area of 0.7 mm/sup 2/, and maintains a signal/(noise + IM3 distortion) ratio of at least 33 dB over a 48-dB signal range, with good blocker immunity. This performance represents at least an order of magnitude improvement over existing channel selection filters, even those that do not achieve disturbance-free operation.     

A 1.8-V ΔΣ modulator interface for an electretmicrophone with on-chip reference

The design of a delta-sigma (ΔΣ) analog-to-digital converter (ADC) for direct voltage readout of an electret microphone is presented. The ADC is integrated on the same chip with a bandgap voltage reference and is designed to be packaged together with an electret microphone. Having a power consumption of 1.7 mW from a supply voltage of 1.8 V, the circuit is well suited for use in mobile applications. The single-loop, single-bit, fourth-order ΔΣ ADC operates at 64 times oversampling for a signal bandwidth of 11 kHz. The measured dynamic range is 80 dB and the peak signal-to-(noise+distortion) ratio is 62 dB. The harmonic distortion is minimized by using an integrator with an instrumentation amplifier-like input which directly integrates the 125-mV peak single-ended voltage generated by the microphone. A combined continuous-time/switched-capacitor design is used to minimize power consumption     

一种基于射频电子标签的超低电压低功耗基带处理器

设计了一款应用于超高频段射频识别系统中电子标签的超低电压低功耗基带处理器.该基带处理器兼容协议,并满足无源标签的超低功耗要求.在设计上有针对性地提出了一种适合于门控时钟电源管理机制的体系结构,以及简单有效的随机数发生机制和分布式译码电路;并灵活运用了流水线结构、降低逻辑深度等低功耗技术.实现了解码/编码、CRC校验、指令解析、防碰撞机制和权限认证,以及对EEPROM的读写操作等功能.芯片采用Chartered 0.35μm 1P3M CMOS标准工艺实现,正常工作的最低电压仅为1.5V,平均电流2.1μA,功耗3.15μW,面积1.1mm×0.8mm.     

Low‐Noise MEMS Microphone Readout Integrated Circuit Using Positive Feedback Signal Amplification

A low‐noise readout integrated circuit (ROIC) for a microelectromechanical systems (MEMS) microphone is presented in this paper. A positive feedback signal amplification technique is applied at the front‐end of the ROIC to minimize the effect of the output buffer noise. A feedback scheme in the source follower prevents degradation of the noise performance caused by both the noise of the input reference current and the noise of the power supply. A voltage booster adopts noise filters to cut out the noise of the sensor bias voltage. The prototype ROIC achieves an input referred noise (A‐weighted) of ?114.2 dBV over an audio bandwidth of 20 Hz to 20 kHz with a 136 μA current consumption. The chip is occupied with an active area of 0.35 mm² and a chip area of 0.54 mm².     

一种带植入式数字信号处理器的新型人工耳蜗系统

提出了一种带植入式数字信号处理器的人工耳蜗系统. 该系统只需在无线通道中传输低码率的语音信号,不存在数据码率受限的问题,有利于人工耳蜗未来的发展. 通过优化语音处理算法和数字信号处理器硬件设计,植入式的处理器可以在3MHz的时钟频率下执行连续相间采样（CIS）算法,功耗仅为1.91mW. 根据理论分析得到的无线能量传输效率（40%) ,可以推算出由于处理器植入所增加的功耗是2.87mW,与现有的商用人工耳蜗系统整机功耗（几十毫瓦）相比微乎其微. 由于处理器的植入,新系统可以很容易扩展成全植入式人工耳蜗系统.     

一种带植入式数字信号处理器的新型人工耳蜗系统

提出了一种带植入式数字信号处理器的人工耳蜗系统.该系统只需在无线通道中传输低码率的语音信号,不存在数据码率受限的问题,有利于人工耳蜗未来的发展.通过优化语音处理算法和数字信号处理器硬件设计,植入式的处理器可以在3MHz的时钟频率下执行连续相间采样(CIS)算法,功耗仅为1.91mW.根据理论分析得到的无线能量传输效率(40%),可以推算出由于处理器植入所增加的功耗是2.87mW,与现有的商用人工耳蜗系统整机功耗(几十毫瓦)相比微乎其微.由于处理器的植入,新系统可以很容易扩展成全植入式人工耳蜗系统.     

基于AD9928A的CCD摄像机的AFE设计

选用ADI公司的AD9928A芯片进行CCD图像传感器的AFE模拟前端设计,包含对AFE模拟前端硬件设计以及驱动时序的研究.主要应用于安防道路智能分析,具有图像分辨率高、噪声小,帧率高、色彩真实鲜亮、超高动态范围等优点,适合基于CCD摄像机的智能分析和图像识别系统.