Numerical methods for transient solutions of machine repair problems

This paper reviews and compares two types of numerical methods of computing transient probabilities of finite Markovian queues (particularly the machine repair problem). A brief review of each method is followed by numerical examples of small and moderate size machine repair problems. The results demonstrate the feasibility of applying numerical techniques for obtaining transient solutions to Markovian queueing problems.     

Plausible clocks: constant size logical clocks for distributed systems

Summary. In a Distributed System with N sites, the precise detection of causal relationships between events can only be done with vector clocks of size N. This gives rise to scalability and efficiency problems for logical clocks that can be used to order events accurately. In this paper we propose a class of logical clocks called plausible clocks that can be implemented with a number of components not affected by the size of the system and yet they provide good ordering accuracy. We develop rules to combine plausible clocks to produce more accurate clocks. Several examples of plausible clocks and their combination are presented. Using a simulation model, we evaluate the performance of these clocks. We also present examples of applications where constant size clocks can be used. Received: January 1997 / Accepted: January 1999     

多交叉通道模型中瞬时故障的后向恢复

在多交叉通道余度系统中,最大限度恢复个别通道出现的输出错误,是表决结果正确性的前提,也是余度系统中的基本问题。在一个指令周期中,多交叉通道针对任务在时间分配上存在一定冗余,对当前表决面之前时间的冗余进行汇总,并假设之后阶段不出现瞬时故障,进行后期冗余时间的估计;累计这两部分冗余,构造一个较大的时间窗口,利用该窗口,在故障时增加回卷深度,实现瞬时故障的最大恢复。基于上述思想,提出了多通道交叉余度模型中的动态时间序列,针对该序列,进行时间回卷深度分析,由此设计了支持后向恢复的算法和具有后向恢复能力的故障监测逻辑。理论分析和实验表明,提出的方法对于提高多通道系统的故障恢复率、减少失步次数等方面十分有效:与静态回卷相比,4通道和6通道下恢复成功率分别提高了47.49%和72.35%,失步次数分别下降了58%和85%,进而较大幅度促进了系统可靠性的提高,尤其是表决面数目较大时效果更为明显。     

Resettable vector clocks

Vector clocks (VC) are an inherent component of a rich class of distributed applications. In this paper, we first consider the problem of realistic implementation—more specifically, bounded-space and fault-tolerant—of applications that use vector clocks (VC). To this end, we generalize the notion of VC to resettable vector clocks (RVC), and provide a realistic implementation of RVC. Further, we identify an interface contract under which our RVC implementation can be substituted for VC in client applications, without affecting the client's correctness. This interface contract is designed for phase-based applications that provide certain communication guarantees. Based on such substitution and the use of the interface contract, we show how to transform the client so that it is itself realistically implemented. We illustrate our method in the context of Ricart–Agrawala's mutual exclusion program and Garg–Chase's predicate detection program.     

Decision-level fusion based on wavelet decomposition for induction motor fault diagnosis using transient current signal

In this paper, we propose and implement a decision-level fusion model by combining the information of multi-level wavelet decomposition for fault diagnosis of induction motor using transient stator current signal. Firstly, the start-up transient current signals are collected from different faulty motors. Then signal preprocessing is conducted containing smoothing and subtracting to reduce the influence of line frequency in transient current signals. Next, we employ discrete wavelet transform technique to decompose the preprocessed signals into different frequency ranges of products, and then features are extracted from decomposed detail components. Finally, two decision-level fusion strategies, Bayesian belief fusion and multi-agent fusion, are employed. That is, fault features are classified using several classifiers and generated decisions are fused using a specific fusion algorithm. The proposed approach is evaluated by an experiment of fault diagnosis for induction motors. Experiment results show that excellent diagnosis performance can be obtained.     

基于混沌神经网络的故障暂态量选线方法研究

为了有效提取故障暂态信息,研究选取适当的小波包基函数。针对电力系统故障暂态量的特点,为了有效克服非故障暂态信号的干扰,研究选取了容错性和联想记忆功能很强的混沌神经网络实现故障选线,并采用改进的遗传算法对混沌神经网络的权值和参数同时进行训练,加快其收敛速度。根据目标模式与神经元的输出状态构造了数值型选线判据。通过实验算例验证了基于暂态量选线判据的有效性和适用性。     

基于混沌神经网络的故障暂态量选线方法研究

为了有效提取故障暂态信息,研究选取适当的小波包基函数.针对电力系统故障暂态量的特点,为了有效克服非故障暂态信号的干扰,研究选取了容错性和联想记忆功能很强的混沌神经网络实现故障选线,并采用改进的遗传算法对混沌神经网络的权值和参数同时进行训练,加快其收敛速度.根据目标模式与神经元的输出状态构造了数值型选线判据.通过实验算例验证了基于暂态量选线判据的有效性和适用性.     

Simulation inferences for an availability system with general repair distribution and imperfect fault coverage

We study the statistical inferences of an availability system with imperfect coverage. The system consists of two active components and one warm standby. The time-to-failure and time-to-repair of the components are assumed to follow an exponential and a general distribution respectively. The coverage factors for an active-component failure and for a standby-component failure are assumed to be the same. We construct a consistent and asymptotically normal estimator of availability for such repairable system. Based on this estimator, interval estimation and testing hypothesis are performed. To implement the simulation inference for the system availability, we adopt two repair-time distributions, namely, lognormal and Weibull and three types of Weibull distributions characterized by their shape parameters are considered. Finally, all simulation results are displayed in appropriate tables and curves for highlighting the performance of the statistical inference procedures.     

星载FPGA混合时钟域设计

设计了以XC2V3000为核心处理芯片的星载FPGA系统的涵盖高速、中速、低速和甚低速的混合时钟域,对混合时钟域可靠性设计中的关键问题,如资源降额、时序冗余、布局布线等,做了深入研究,提出了基于全局时钟网络、时钟鉴相、FIFO缓冲的多时钟同步设计解决方案,并在实际工程中验证了方案的可行性和可靠性。     

Evaluation of transient errors in GPGPUs for safety critical applications: An effective simulation-based fault injection environment

General Purpose Graphics Processing Units (GPGPUs) are increasingly adopted thanks to their high computational capabilities. GPGPUs are preferable to CPUs for a large range of computationally intensive applications, not necessarily related to computer graphics. Within the high performance computing context, GPGPUs must require a large amount of resources and have plenty execution units. GPGPUs are becoming attractive for safety-critical applications where the phenomenon of transient errors is a major concern. In this paper we propose a novel transient error fault injection simulation methodology for the accurate simulation of GPGPUs applications during the occurrence of transient errors. The developed environment allows to inject transient errors within all the memory area of GPGPUs and into not user-accessible resources such as in streaming processors combinational logic and sequential elements. The capability of the fault injection simulation platform has been evaluated testing three benchmark applications including mitigation approaches such as Duplication With Comparison, Triple Modular Redundancy and Algorithm Based Fault Tolerance. The amount of computational costs and time measured is minimal thus enabling the usage of the developed approach for effective transient errors evaluation.     

Saving power by synthesizing gated clocks for sequential circuits

Portable devices demand low power consumption to prolong battery life. Gating the clock is one strategy for saving power. The authors' technique identifies self-loops in an FSM and uses the function described by the self-loops to gate the clock. Applying these techniques to standard benchmarks achieved an average 25% less power dissipation at a cost of only 5% more area     

带时间约束的LTL性质的模型检测的实现

针对当前的模型检测工具不能对时间自动机直接检测带时间约束的线性时序逻辑性质的问题,对带时间约束的线性时序逻辑性质的模型检测进行了研究。带时间约束的线性时序逻辑公式转Büchi自动机后,性质自动机的迁移边上含有了时间约束,在对性质自动机和模型自动机的复合进行空性检测时,通过使用不同方法对如何获取性质自动机迁移边上的时间约束进行了研究,实现了对带时间约束的线性时序逻辑性质的检测,扩展了工具CATV的检测范围,方便了用户的使用。     

A leader election algorithm for dynamic networks with causal clocks

An algorithm for electing a leader in an asynchronous network with dynamically changing communication topology is presented. The algorithm ensures that, no matter what pattern of topology changes occurs, if topology changes cease, then eventually every connected component contains a unique leader. The algorithm combines ideas from the Temporally Ordered Routing Algorithm for mobile ad hoc networks (Park and Corson in Proceedings of the 16th IEEE Conference on Computer Communications (INFOCOM), pp. 1405–1413 (1997) with a wave algorithm (Tel in Introduction to distributed algorithms, 2nd edn. Cambridge University Press, Cambridge, MA, 2000), all within the framework of a height-based mechanism for reversing the logical direction of communication topology links (Gafni and Bertsekas in IEEE Trans Commun C–29(1), 11–18 1981). Moreover, a generic representation of time is used, which can be implemented using totally-ordered values that preserve the causality of events, such as logical clocks and perfect clocks. A correctness proof for the algorithm is provided, and it is ensured that in certain well-behaved situations, a new leader is not elected unnecessarily, that is, the algorithm satisfies a stability condition.     

Clock trees: logical clocks for programs with nested parallelism

A vector clock is a valuable tool for maintaining run time concurrency information in parallel programs. A novel method is presented for modifying vector clocks to make them suitable for programs with nested fork join parallelism (having a variable number of tasks). The resulting kind of clock is called a clock tree, due to its tree structure. The clock tree method compares favorably with other timestamping methods for variable parallelism: task identifier reuse and task recycling. The worst case space requirements of clock trees equals the best case for the latter two methods, and the average size of a clock tree is much smaller than the size of a vector with task recycling. Furthermore, the algorithm for maintaining clock trees does not require a shared data structure and thus avoids the serialization bottleneck that task recycling suffers from     

Automated design space exploration of multi-cycle transient fault detectable datapath based on multi-objective user constraints for application specific computing

A novel automated design space exploration (DSE) approach of multi-cycle transient fault detectable datapath based on multi-objective user constraints (power and delay) for application specific computing is presented in this paper. To the best of the authors’ knowledge, this is the first work in the literature to solve this problem. The presented approach, driven by bacterial foraging optimization (BFO) algorithm provides easy flexibility to change direction in the design space through tumble/swim actions if a search path is found ineffective. The approach is highly capable of reaching true Pareto optimal curve indicated by the closeness of our non-dominated solutions to the true Pareto front and their uniform distribution over the Pareto curve (implying diversity). The contributions of this paper are as follows: (a) novel exploration approach for generating a high quality fault detectable structure based on user provided requirements of power-delay, which is capable of transient error detection in the datapath; (b) novel fault detectable algorithm for handling single and multi-cycle transient faults.The results of the proposed approach indicated an average improvement in Quality of Results (QoR) of >9% and reduction in hardware usage of >23% compared to recent approaches that are closer in solving a similar objective.     

Computing with biological switches and clocks

The complex dynamics of biological systems is primarily driven by molecular interactions that underpin the regulatory networks of cells. These networks typically contain positive and negative feedback loops, which are responsible for switch-like and oscillatory dynamics, respectively. Many computing systems rely on switches and clocks as computational modules. While the combination of such modules in biological systems leads to a variety of dynamical behaviours, it is also driving development of new computing algorithms. Here we present a historical perspective on computation by biological systems, with a focus on switches and clocks, and discuss parallels between biology and computing. We also outline our vision for the future of biological computing.     

小电流接地故障暂态选线技术在炼化企业电网的应用

炼化企业配电网与地方配电网存在一定差异,本文介绍了一种利用故障暂态信息的适用于炼化企业的小电流接地故障选线原理和装置,提出了基于瞬时性故障信息的线路绝缘监测思路,分析统计其在现场的运行情况。现场运行结果表明,该技术原理先进,选线成功率高,能够发现并纠正零序二次回路极性反接。线路绝缘监测,能更准确地用来估计线路的绝缘状态,从而减少停电时间和预防试验对电缆的损坏。     

一种用于铷原子钟的低相位噪声压控振荡器

基于相干布局囚禁(CPT)现象研制的原子钟与传统原子钟相比,能够提供更高的时间精度,且有利于原子钟向微型化、低功耗方向发展。在不同种类的CPT原子钟中,铷原子钟应用最为广泛,而其性能的优劣很大一部分取决于自身内部的用于提供微波信号源的压控振荡器(VCO)。基于此,利用高品质因数的同轴谐振器和Clapp振荡电路,首先根据负阻分析法使电路快速起振,并结合虚拟地技术对电路参数进行优化,完成了一个小体积、低相位噪声的3.035 GHz压控振荡器的设计。其相位噪声为-60.49 d Bc/Hz@300 Hz、-73.08 d Bc/Hz@1 k Hz和-97.48 d Bc/Hz@10 k Hz,压控调节灵敏度为12 MHz/V,输出信号的功率为-1.13 d Bm,满足铷原子钟的应用需求。     

Principal Component Analysis of the start-up transient and Hidden Markov Modeling for broken rotor bar fault diagnosis in asynchronous machines

This article presents a novel computational method for the diagnosis of broken rotor bars in three phase asynchronous machines. The proposed method is based on Principal Component Analysis (PCA) and is applied to the stator’s three phase start-up current. The fault detection is easier in the start-up transient because of the increased current in the rotor circuit, which amplifies the effects of the fault in the stator’s current independently of the motor’s load. In the proposed fault detection methodology, PCA is initially utilized to extract a characteristic component, which reflects the rotor asymmetry caused by the broken bars. This component can be subsequently processed using Hidden Markov Models (HMMs). Two schemes, a multiclass and a one-class approach are proposed. The efficiency of the novel proposed schemes is evaluated by multiple experimental test cases. The results obtained indicate that the suggested approaches based on the combination of PCA and HMMs, can be successfully utilized not only for identifying the presence of a broken bar but also for estimating the severity (number of broken bars) of the fault.     

异步时钟域的亚稳态问题和同步器

相较纯粹的单一时钟的同步电路设计,设计人员更多遇到的是多时钟域的异步电路设计.因此,异步电路设计在数字电路设计中的重要性不言而喻.本文主要就异步设计中涉及到的亚稳态问题,作简要介绍,并提出常用的解决办法--即同步器的使用.