共查询到16条相似文献,搜索用时 62 毫秒
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分析研究了在电力系统测控中应用数字信号处理器的优势,并且设计了以DSP处理器TMS320F2812为核心的电网谐波检测分析系统.通过多路同步采集将电网电量数据输入系统,在处理器中完成数据倒序处理和快速傅立叶变换等相关的运算处理工作,可以得到各次谐波含量. 相似文献
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小波变换与傅立叶变换相结合的信号实例分析 总被引:1,自引:0,他引:1
文章采用离散小波变换与快速傅立叶变换相结合的方法,先对原始信号进行小波分解,再对各子带信号做快速傅立叶变换,从而得到各子带上时间信号的频谱。计算机仿真的实例分析表明,该方法将小波变换和傅立叶变换的优点结合了起来。 相似文献
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Real-valued Fast Fourier Transform (FFT) plays an important role in today’s digital world because of the fact that most of the signals contain real values. The FFT computation of real signals using conventional techniques requires more hardware space with high power consumption, which is the most important task for a researcher while designing VLSI architectures. This can be eradicated by clearly analysing the symmetric property of the real-valued signals. In this paper, we have adopted the symmetric property and designed an efficient pipelined architecture for 16-point DIF FFT. The pipeline scheme reduce the processing time at the cost of some registers and in order to contribute efficiently for power reduction we have modified the complex multiplier with reduced internal real multipliers which are in turn replaced by an modified canonic signed digit multiplier (CSDM) with resource-sharing technique. The complete module is synthesised and simulated using Xilinx ISE 14.1 with the target device is Virtex-5 xc5vlx110T. The experimental results verify that our implemented design is more efficient in terms of speed, area and power when comparing with similar works. 相似文献
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设计和实现超高速快速傅里叶变换器(FFT)在雷达与未来无线通信等系统中具有重要意义。该文提出首个全并行架构的FFT处理器,其避免了复杂的路由寻址以及数据访问冲突等问题,基于较大基进行分解降低运算复杂度。由于旋转因子已知和固定,大量的乘法转化为了定系数乘法。同时由于采用了串行的计算单元,在达到全并行结构的高速度同时硬件复杂度相对较低;所有的硬件计算单元处于满载的条件,其硬件效率能达到100%。根据实际的实现结果,所提出的512点FFT处理器结构能够达到5.97倍速度面积比的提升,同时硬件开销仅占用了Xilinx V7-980t FPGA 30%的查找表资源与9%的寄存器资源。 相似文献
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针对视觉跟踪中目标表观变化、局部遮挡、背景干扰等问题,该文提出一种基于快速傅里叶变换的局部分块视觉跟踪算法。通过建立目标分块核岭回归模型并构建循环结构矩阵进行分块穷搜索来提高跟踪精度,利用快速傅里叶变换将时域运算变换到频域运算提高跟踪效率。首先,在包含目标的初始跟踪区域建立目标分块核岭回归模型;然后,提出通过构造循环结构矩阵进行分块穷搜索,并构建目标分块在相邻帧位置关系模型;最后,利用位置关系模型精确估计目标位置并进行分块模型更新。实验结果表明,该文算法不仅对目标表观变化、局部遮挡以及背景干扰等问题的适应能力有所增强,而且跟踪实时性较好。 相似文献
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Fast Fourier transform (FFT) plays an important role in the orthogonal frequency division multiplexing (OFDM) communication
systems. In this paper, we propose an area-efficient design of variable-length FFT processor which can perform various FFT
lengths of 512/1,024/2,048/4,096/8,192 points used in OFDM-based communication systems, such as digital audio broadcasting
(DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). To reduce computational
complexity and chip area, we develop a new variable-length FFT architecture by devising a mixed-radix algorithm that consist
of radix-2, radix-22 and radix-2/4/8 algorithms and optimizing the realization by substructure sharing. Based on this architecture, an area-efficient
design of variable-length FFT processor is presented. By synthesized using the UMC 0.18 μm process, the area of the processor
is 2.9 mm2 and the 8,192-point FFT can be performed correctly up to 50 MHz with power consumption 823 mW under a 1.8 V supply voltage.
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Shuenn-Shyang WangEmail: |
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提出了一套快速傅里叶变换深能级瞬态谱(FFT-DLTS)测试系统,分析了该系统的硬件构成和软件流程,并给出了一个实例分析。最后,将FFT-DLTS与常规DLTS作了对比。 相似文献