Design and performance of 0.1-μm CMOS devices usinglow-impurity-channel transistors (LICT's)

0.1-μm CMOS devices using low-impurity-channel transistors (LICTs) with dual-polysilicon gates have been fabricated by nondoped epitaxial growth technology, high-pressure oxidation of field oxide, and electron-beam lithography. These devices, with gate lengths of 0.135 μm, achieved normal transistor operation at both 300 and 77 K using 1.5-V supply voltage. Maximum transconductances are 203 mS/mm for nMOS transistors and 124 mS/mm for pMOS transistors at 300 K. Low-impurity channels grown on highly doped wells provide low threshold voltages of about 0.35 V for nMOS transistors and about -0.15 V for pMOS transistors at 77 K, and preserve good turn-offs with subthreshold swings of 25 mV/decade at 77 K. LICTs suppress short-channel effects more effectively, compared with conventional devices with nearly uniform dopings     

Short-channel-effect free 0.18 μm MOSFET bytemperature-dimension combination scaling theory: design and experiment

We have fabricated 77 K deep-submicron MOSFETs on the basis of the temperature-dimension combination scaling theory (CST). The 77 K MOSFETs with 1-V supply voltage are designed from a 300 K MOSFET with 4-V supply voltage. The fabricated 77 K 0.18 μm device has exhibited fully scaled characteristics. The subthreshold swing (S) and the threshold voltage (V_th) of the 77 K device are found to be 1/4≈77 K/300 K of those of the 300 K device. Furthermore, S and V_th are achieved to be 27 mV/dec and 0.21 V without short-channel effect degradation     

0.18-μm fully-depleted silicon-on-insulator MOSFET's

High-performance 0.18-μm gate-length fully depleted silicon-on-insulator (FD-SOI) MOSFET's were fabricated using 4-nm gate oxide, 35-nm thick channel, and 80-nm or 150-nm buried oxide layer. An elevated source/drain structure was used to provide extra silicon during silicide formation, resulting in low source/drain series resistance. Nominal device drive currents of 560 μA/μm and 340 μA/μm were achieved for n-channel and p-channel devices, respectively, at a supply voltage of 1.8 V. Improved short-channel performance and reduced self-heating were observed for devices with thinner buried oxide layers     

DIBL in short-channel NMOS devices at 77 K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 μm is improved for the range of L<0.6 μm and L>1.2 μm, but is worse for L between 0.6 and 1.2 μm. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and V_TH as required for room-temperature operation are briefly discussed     

Experimental high performance sub-0.1 μm channel nMOSFET's

Very high performance sub-0.1 μm channel nMOSFET's are fabricated with 35 Å gate oxide and shallow source-drain extensions. An 8.8-ps/stage delay at V_dd=1.5 V is recorded from a 0.08 μm channel nMOS ring oscillator at 85 K. The room temperature delay is 11.3 ps/stage. These are the fastest switching speeds reported to date for any silicon devices at these temperatures. Cutoff frequencies (f_T) of a 0.08 μm channel device are 93 GHz at 300 K, and 119 GHz at 85 K, respectively. Record saturation transconductances, 740 mS/mm at 300 K and 1040 mS/mm at 85 K, are obtained from a 0.05 μm channel device. Good subthreshold characteristics are achieved for 0.09 μm channel devices with a source-drain halo process     

A low-resistance self-aligned T-shaped gate for high-performancesub-0.1-μm CMOS

This paper describes the high performance of T-shaped-gate CMOS devices with effective channel lengths in the sub-0.1-μm region. These devices were fabricated by using selective W growth, which allows low-resistance gates smaller than 0.1 μm to be made without requiring fine lithography alignment. We used counter-doping to scale down the threshold voltage while still maintaining acceptable short-channel effects. This approach allowed us to make ring oscillators with a gate-delay time as short as 21 ps at 2 V with a gate length of 0.15 μm. Furthermore, we experimentally show that the high circuit speed of a sub-0.1-μm gate length CMOS device is mainly due to the PMOS device performance, especially in terms of its drivability     

Sub-40 nm SOI V-groove n-MOSFETs

We present output and transfer characteristics of single-gated, 36 nm, 46 nm and 56 nm channel length SOI MOSFETs with a V-groove design. For the shortest devices we find transconductances as high as 900 μS/μm and drive currents of 490 μA/μm at V_gs - V _th=0.6 V. The V-groove approach combines the advantages of a controlled, extremely abrupt doping profile between the highly doped source/drain and the undoped channel region with an excellent suppression of short-channel effects. In addition, our V-groove design has the potential of synthesizing devices in the 10 nm range     

Double ion implanted V-MOS technology

An n-channel double ion implanted (or diffused] lateral V-MOS structure (D-V-MOS) for LSI digital application is presented. The effective channel is formed by the vertical difference in an n-type and a p-type impurity profile on a high resistive p-type substrate through a V-groove technique. Thus the threshold voltage and effective channel length of the D-V-MOS can be directly and accurately controlled by ion implantation. Very short-channel length (0.1 to 0.2 /spl mu/m) MOS devices with good electrical characteristics can thus be realized. A simple fabrication process with 5 masking steps for an n-channel self-isolated self-aligned enhancement/depletion (E/D) D-V-MOST device is presented. The fabrication procedures are described. Special features associated with the V structure are discussed. The short-channel effect is treated. It is found that the substrate sensitivity due to source-substrate biasing for a short-channel D-V-MOS is reduced significantly, even with a 1000-/spl Aring/ gate oxide thickness.     

Design and characterization of superlattice infrared photodetectoroperating at low bias voltage

In this paper, we investigate the performance and characterization of a 15-period superlattice embedded between two thick AlGaAs barriers. The structure can operate at low bias voltage with less power consumption for 8-10 μm long-wavelength infrared detection. In our design, one barrier is used to reduce the dark current and the other one is designed to enhance the collection efficiency of photoelectrons at the collector contact. The fabricated detector can be operated at a bias voltage lower than 0.1 V and exhibits a pronounced photovoltaic response. The spectral response shows voltage dependence around 0 V. At high bias voltage (>25 mV) the spectral lineshape is independent of bias and is around 8-10 μm with peak wavelength at 9.3 μm. At lower bias voltage the response is shifted toward shorter wavelength range. The peak responsivity was found to be 12 mA/W at λ_p =8.7 μm and zero bias and 85 mA/W at λ_p=9.3 μm and 0.1 V. Background limitation can be achieved up to 65 K with bias voltage less than 0.1 V. The measured noise power spectral density of the dark current at 77 K shows the characteristics of full shot noise rather than generation-recombination noise. The peak detectivity is determined to be D^*=3.5×10⁹ cm√(Hz)/W at 77 K and 0.1 V. In comparison with a conventional 30-period QWIP, our detector has the advantages of better performance at low bias voltages with lower power consumption and a tunable feature of spectral range     

High-performance devices for a 0.15-μm CMOS technology

Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 μm and minimum channel length below 0.1 μm. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 μm, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF₂ implant were used. Maximum high V _DS threshold rolloff was 250 mV at effective channel length of 0.06 μm. For the minimum channel length of 0.1 μm, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively     

A room temperature 0.1 μm CMOS on SOI

An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 μm) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 Å effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C_L=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained     

Study of the operation speed of half-micron design rule CMOS ringoscillators

The operation speed of a 73-stage CMOS ring oscillator with 0.5 μm channel lengths has been investigated. By employing a capacitance-reduced structure, gate delays of 47.4 ps and 49.3 ps with and without substrate bias at room temperature, and of 43.0 ps at 77 K, respectively, have been experimentally obtained at a supply voltage of 5 V. From the evaluation of parasitic capacitances, the speed which is achievable by the proper scaling of the device parameters at a half-micron design rule is estimated to be approximately 30 ps     

A novel 0.1 μm MOSFET structure with inverted sidewall andrecessed channel

To solve the problems of trade-off between the short channel effect and the performance enhancement of sub-quartermicrometer MOSFETs, we have developed a recessed channel MOSFET structure called ISRC (Inverted-Sidewall Recessed-Channel). The oxide thickness is 4 nm and the effective channel length is 0.1 μm, which is the smallest Si-MOSFET ever reported in the recessed channel structures. The maximum saturation transconductance at V_D=2 V is 446 mS/mm for the 0.1 μm n-channel device. The threshold voltage roll-off is kept within 64 mV when the gate length varies from 1.4 μm to 0.1 μm and good subthreshold characteristics are achieved for 0.1 μm channel device     

Submicrometer-channel CMOS for low-temperature operation

A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n⁺-poly gate for n-channel and p⁺-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.     

Multiple Sb ion implantation for deep-submicron pMOS channel doping

We propose a channel doping technology for pMOSFET's in which Sb is multiply ion implanted to produce a uniform doping profile in the region deeper than the minimum projected range of the multiple ion implantation. We derive a threshold voltage model and show how to realize this uniform doping profile, which is verified with experimental data. We study the short-channel effect of this device using a two-dimensional (2-D) device simulator, and show that this transistor can readily operate with a gate length of down to 0.1 μm     

Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V     

Design of 10-nm-scale recessed asymmetric Schottky barrier MOSFETs

We have proposed and simulated a new 10-nm and sub-10 nm n-MOSFET that has a recessed channel and asymmetric source/drain Schottky Contacts (RASC MOSFETs). The recessed channel can effectively suppress short-channel effects, and the asymmetric source/drain contacts in which a higher Schottky barrier at the source contact can yield smaller off-state current while a lower Schottky barrier at the drain can yield larger on-state current. The simulated results show that the device can exhibit an on/off ratio as high as 10⁶ and an on-state current of 393 μA/μm with a supply voltage of 1.0 V. Furthermore, the parameters of RASC MOSFETs are rather insensitive to size variations. These characteristics make the 10-nm or even sub-10 nm transistors potentially suitable for logic and memory applications     

Electrical characteristics of a DSA MOS transistor with a fine structure

Fabrication technologies and electrical characteristics of a diffusion self-aligned MOS transistor (DSA MOST) or a double-diffused MOS transistor (DMOST) are discussed in comparison with a conventional short-channel MOS transistor as a fundamental device for a VLSI. The symmetrical DSA MOS LSI with enhancement depletion configurations requires six photolithographic steps and the number of the steps is the same as that of an NMOS LSI with small physical dimensions. The only difference is the step orders of the enhancement channel doping in these devices. The lowering effects of the threshold voltage and the source drain breakdown voltage are smaller in the DSA MOST than in the conventional MOS transistor. The drain current IDof the symmetrical DSA MOS transistor is, respectively, 1.13 (in the nonsaturation region) and 1.33 (in the saturation region) times larger than that of the conventional short-channel NMOS transistor at the effective gate voltage of 3.0 V. The improvement of the short-channel effect, the current voltage characteristics, and the power-delay product are obtained by the scaling of the DSA MOS transistor.     

The inversion layer of subhalf-micrometer n- and p-channel MOSFET'sin the temperature range 208-403 K

Minority carrier mobility has been extracted from I-V measurements on N- and PMOS-transistors entirely processed by means of X-ray lithography with effective channel lengths down to 0.35 μm. The measurements have been performed within the temperature range 208-403 K (-65°C to +130°C). The accuracy of the mobility determination has been investigated, especially with regard to the determination of the effective channel length and the series resistance. The results indicate a significant mobility reduction for short-channel NMOS devices at temperatures below 300 K. A slight increase of the threshold-voltage is observed in the short-channel region. Both effects can be required by an inhomogeneous lateral doping profile within the channel due to standard submicron technology; this has been confirmed by two-dimensional device simulation     

Ultrafast operation of Vth-adjustedp+-n+ double-gate SOI MOSFET's

To optimize the V_th of double-gate SOI MOSFET's, we fabricated devices with p⁺ poly-Si for the front-gate electrode and n⁺ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V_th of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 μm long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects