High-speed integrated circuits using i-AlGaAs/n-GaAs doped-channel hetero-MISFET's (DMT's)

High-speed ring oscillators and divide-by-two circuits have been fabricated by using i-AlGaAs/n-GaAs doped-channel hetero-MISFET's (DMT's) and saturated resistors in direct-coupled FET logic (DCFL) circuit architecture for the first time. The maximum operating frequency is 3.72 GHz for dual-clocked master-slave flip-flop frequency dividers based on eight NOR gates, which consist of 0.8-µm gate enhancement-mode DMT's with 370-mS/mm maximum transconductance. A 25-stage ring oscillator shows 24-     

Scanning electron mirror microscopy and scanning electron microscopy of integrated circuits

The recently developed scanning electron mirror microscope (SEMM) is compared with other types of electron microscopes, such as the electron mirror microscope (EMM) and the scanning electron microscope (SEM), for examining integrated circuits. Potential advantages of the SEMM include high resolution, elimination of electron bombardment damage, and high sensitivity of voltage gradients, magnetic fields, and topography. Preliminary observations of integrated, circuits obtained with the feasibility SEMM at various specimen potentials are discussed.     

Frequency-selective integrated circuits using phase-lock techniques

A system-oriented approach to the design of inductorless tuned integrated circuits is described. This design method uses the phase-locked loop (PLL) techniques to obtain the desired tuning and interference-rejection characteristics. The PLL approach does not require tight control of component tolerances, and offers a higher selectivity and frequency capability than the corresponding active-RC synthesis methods. In this paper, basic design parameters for phase-locked integrated circuits are given, and two separate design examples are described. First is a high- frequency (1 to 25 MHz) FM amplifier/detector, which forms a monolithic replacement for the IF strip and the detector sections of a conventional FM receiver or TV sound system. The second is an integrated FM multiplex receiver for multi-channel telemetry applications, which has the selectivity of a 6-pole bandpass filter and can be tuned by means of an external resistor or capacitor from a fraction of a cycle to over 300 kHz.     

太赫兹探测器读出电路的单电子晶体管制备

射频单电子晶体管具有高电荷灵敏度和高读出速率的特点,可用于超导太赫兹单光子探测器产生的微弱电荷信号的读出。采用绝缘体上硅(SOI)材料制备的硅基单电子晶体管具有结构可控、工艺可重复的优点。但是,目前单电子晶体管的成品率约为30%,难以满足探测器阵列化的需求。为进一步提高单电子晶体管成品率,首先采用电子束零宽度线曝光工艺精确设定单电子晶体管的图形,其次对感应耦合等离子体刻蚀工艺中的气氛比例进行优化,实现电子束曝光图形的良好转移。最后通过降低氧化温度进一步保持了图形转移的准确度。单电子晶体管的隧穿势垒宽度得到了良好的控制,使成品率提高到90%,增强了单电子晶体管作为阵列化超导太赫兹单光子探测器读出电路的可行性。     

Recent progress in optoelectric integrated circuits (OEIC's)

Recent developments in both GaAs- and InP-based opto-electronic circuits (OEIC's) which incorporate both optoelectronic and electronic devices on the same semiconductor substrates will be discussed. Several key technologies required for optoelectronic integration and the present status of the technology are explained by reviewing some of OEIC transmitters and receivers that have been realized up to now. Possibilities of application of OEIC's and further technological challenges to enhance the advantages of OEIC's are discussed.     

Depth profiling of integrated circuits with thermal wave electron microscopy

Nondestructive depth profiling of integrated circuits is performed with thermal wave electron microscopy at 640 kHz modulation frequency.     

Digital optical networks using photonic integrated circuits (PICs) address the challenges of reconfigurable optical networks

To reduce costs and simplify operations, carriers are deploying flexible optical networks that can be easily reconfigured and managed remotely. This article provides an overview of typical all-optical reconfigurable optical add/drop multiplexer (ROADM) systems and their associated network issues. We describe a novel digital optical network architecture based on digital ROADM systems, which use photonic integrated circuits (PICs) to overcome many of these issues. Digital ROADM systems use monolithic PICs to integrate over 60 discrete optical components, including lasers, modulators and detectors, into a single pair of optical components, allowing cost-effective optical-electrical-optical conversion at every node. This also allows key functions such as service reconfiguration, add/drop and protection to be implemented in the digital domain, and enables de-coupling of service provisioning from optical link engineering, termed bandwidth virtualization. Finally, key deployment, reliability and operational metrics for PIC-based digital ROADM systems are presented.     

Low-noise high electron mobility transistors for monolithic microwave integrated circuits

High electron mobility transistors (HEMT's) for monolithic microwave integrated circuits have been fabricated that have demonstrated excellent performance. External transconductance of 300 mS/mm is observed and noise figures of 1 and 1.8 dB with associated gains of 16.1 and 11.3 dB at 8 and 18 GHz, respectively, have been measured. These are comparable to the best reported noise figures for either HEMT's or MESFET's and are the highest associated gains reported for such low-noise figures. Analysis of these devices indicates that further improvements in these results is possible through optimization of HEMT layers and fabrication technology to reduce gate-source parasitic resistance.     

Analogue MOS current-mode circuits for three-dimensional integrated smart image sensor

An image processing technique using analogue MOS current-mode circuits is presented. This approach is of interest in smart image sensors based on three-dimensional (or multi-layered) VLSI structures. High-performance smart image sensors with high resolution can be realised because the number of transistors required for image processing in each pixel is greatly reduced.<>     

Transmission electron microscopy of cross sections of large scale integrated circuits

Accurate cross-sectional views of large scale integrated circuits are useful for failure analysis and process evaluation. We have successfully prepared thin sections of finished devices cut perpendicular to the plane of the chip and examined them using transmission electron microscopy. We describe the sectioning procedure and show some cross-sectional views from memory cells of a CMOS RAM with poly-Si gates and tungsten second metal. Examples include micrographs of sections through 1) an IGFET showing the gate edges and the poly-Si grain size distribution, 2) metal to Si, and metal to poly-Si contacts, and 3) poly-Si runners. Each circuit element examined was uniquely identified by mapping the cross section through adjacent memory cells and noting the sequence of elements intersected. This demonstrated ability to examine cross sections of finished devices, consisting of multilayers of materials with different densities, hardness, etc., should prove useful whenever detailed device geometries, crystalline structures, etc., need to be examined in a manner which is relatively free of experimental artifacts.     

亮度自适应增强的图像投影系统设计

为了让投影系统在恒定照明功率下提升投影亮度,设计了基于FPGA的光源亮度自适应调节的图像投影显示系统。硬件系统以FPGA+MCU结构为核心处理单元,4片速率为677 MHz的DDR2为高速缓存器,32位800 MHz LVDS为高速数字微镜DMD(Digital Micro Mirror Device)通信接口。系统的核心算法IEB(Intelligence to Enhance Brightness)可自适应地提升图像亮度,真实地还原图像细节,以及产生PWM(Pulse Width Modulation)脉冲实时控制光源发射功率。运用并行运算降低算法执行时间,优化算法结构,增加时序余量。实验结果表明,恒定照明功率下投影平均亮度增加2倍,细节可得到真实还原,基于FPGA的IEB算法执行速度较PC提高10倍,系统工作稳定可靠。     

High-quality image resizing using oblique projection operators

The standard interpolation approach to image resizing is to fit the original picture with a continuous model and resample the function at the desired rate. However, one can obtain more accurate results if one applies a filter prior to sampling, a fact well known from sampling theory. The optimal solution corresponds to an orthogonal projection onto the underlying continuous signal space. Unfortunately, the optimal projection prefilter is difficult to implement when sine or high order spline functions are used. We propose to resize the image using an oblique rather than an orthogonal projection operator in order to make use of faster, simpler, and more general algorithms. We show that we can achieve almost the same result as with the orthogonal projection provided that we use the same approximation space. The main advantage is that it becomes perfectly feasible to use higher order models (e.g. splines of degree n=/>3). We develop the theoretical background and present a simple and practical implementation procedure using B-splines. Our experiments show that the proposed algorithm consistently outperforms the standard interpolation methods and that it provides essentially the same performance as the optimal procedure (least squares solution) with considerably fewer computations. The method works for arbitrary scaling factors and is applicable to both image enlargement and reduction.     

Metallization for integrated circuits using a lift-off technique

A special lift-off technique for realizing small metal interconnection geometries for integrated circuits is described. 0.6-/spl mu/m gaps between metal conductors can be obtained even at 0.8-/spl mu/m metal layer thickness. The slopes of the conductors are tapered. Etching problems inherent in alloy films or sandwiched layers such as Al/Si or Al/Cu/Si are avoided by the technique proposed. SEM micrographs of Al/Si conductor patterns are presented.     

High-voltage DMOS integrated circuits using floating-gate protection technique

An efficient low power protection scheme for thin gate oxide of high voltage (HV) DMOS transistor is presented. To prevent gate-oxide breakdown and protect HV transistor, the voltage controlling its gate must be within 5 V from the HV supply. Thus signals from the low voltage domain must be level shifted to control the gate of this transistor. Usually this level shifting involves complex circuits that reduce the speed besides requiring of large power and area. In this paper, a simple and efficient protection technique for gate-oxide breakdown is achieved by connecting a capacitor divider structure to the floating-gate node of HV transistor to increase its effective gate oxide thickness. Several HV circuits, including: positive and negative HV doublers and level-up shifters suitable for ultrasound sensing systems are built successfully around the proposed technique. These circuits were implemented with 0.8 μm CMOS/DMOS HV DALSA process. Simulation and experimental results prove the good functionality of the designed HV circuits using the proposed protection technique for voltages up to 200 V.     

An integrated micro cooling system for electronic circuits

A fully FR4-compatible integrated cooling system has been developed. Cooling channels have been etched into a thick copper layer to form microchannels. The structure is reinforced by two prepreg layers toward the component and solder side. Several cooling channels can be independently run. The heat dissipation capability of the system is 20 W per channel (and heat source). Typical coolants are water or methoxynonafluorobutane. For an outlet to inlet temperature difference of 25°C and a power dissipation of 30 W, a (water) flow rate of 20 ml/min is required. Pressure losses are below 300 mbar (for water)     

Pseudomorphic high electron mobility transistor monolithic microwave integrated circuits reliability study

Accelerated high temperature RF life testing was used to investigate the reliability of two-stage GaAs monolithic microwave integrated circuit (MMIC) power amplifiers based on 0.25 μm pseudomorphic high electron mobility transistor technology. Life testing was performed at elevated baseplate temperatures with MMICs operating at typical d.c. bias conditions and large signal RF drive levels of two dB compression. The resulting failure distribution was log normal and the estimated median life time extrapolated to a channel temperature of 140°C was 2.3×10⁶ h with an activation energy of 1.1 eV.     

Design of RF integrated circuits using SiGe bipolar technology

We report on design aspects and the implementation of radio-frequency integrated circuits using TEMIC's SiGe technology. The differences between the device parameters of silicon bipolar junction transistor and silicon germanium heterojunction bipolar transistor technology and their influence on IC design are discussed. Design and measurement results of RFICs, including low noise amplifier, power amplifier, and single-pole, double-throw antenna switch for application in a 1.9 GHz digital enhanced cordless telecommunications RF front end are presented     

Multiple layers of CMOS integrated circuits using recrystallizedsilicon film

This letter presents a method to fabricate high performance three-dimensional (3-D) integrated circuits based on the conventional CMOS SOI technology. The first layer of transistors is fabricated on SOI and the second layer is fabricated on large-grain polysilicon-on-insulator (LPSOI), using oxide as the interlayer dielectric. The LPSOI film is formed by the recrystallization of amorphous silicon through metal induced lateral crystallization (MILC). The grain size obtained by the LPSOI process is much larger than the transistors and the transistor performance is similar to those fabricated on the SOI layer. Three-dimensional (3-D) CMOS inverters have been demonstrated with p-channel devices stacking over the n-channel ones     

Diagnosing reliability of integrated circuits using noises and the ESD effect

Procedures for screening batches of CMOS and bipolar integrated circuits (ICs) are considered using low-frequency noises and electrostatic discharge (ESD) effects.     

Design and implementation of quaternary NMOS integrated circuits for pipelined image processing

A pattern-matching procedure for performing four-valued image processing based on cellular logic operation is proposed, allowing two different templates to be processed simultaneously in a pipelined manner. Based on these double pattern-matching cells, a compact NMOS image-processing chip has been implemented. It is demonstrated that the compactness comes from reduced interconnections in the double pattern-matching cells using a quaternary multiplexer or T gates, realized with pass transistors and multiple ion implants.