Inverter-based 1 V analog front-end amplifiers in 90 nm CMOS for medical ultrasound imaging

In this paper, we present the design and experimental evaluation of 1 V analog front-end amplifiers designed in 90 nm CMOS technology for capacitive micro-machined ultrasound transducers (CMUTs) for medical ultrasound imaging systems. We propose two front-end amplifier topologies based on an inverter-based cascode amplifier; the first is a continuous time amplifier and the second is a charge sampling amplifier (CSA). The proposed front-end amplifiers are designed to amplify the signals from CMUTs in the frequency bandwidth from 15 to 45 MHz with a centre frequency of 30 MHz. From the measurements, the continuous time single-ended transimpedance amplifier achieves a voltage gain of 19 dB, an output noise power spectral density of 0.042 (μV)/SQRT(Hz) at a centre-frequency of 30 MHz, and a total harmonic distortion of −23 dB at 450 mV p–p output voltage at 30 MHz input signal frequency. It draws only 598 μA per amplifier from a 1 V power supply. Its area measured only about 32 μm × 32 μm per amplifier. On the other hand, a sampling based front-end amplifier [CSA] achieves a transfer gain of 17.4 dB at an input signal frequency of 30 MHz and an upper 3 dB cut-off frequency of 46 MHz at a sampling clock frequency of 100 MHz. It consumes 586 μA per amplifier from a 1 V power supply and achieves a signal-to-noise (SNR) ratio of 45.7 dB with a peak-to-peak output signal amplitude of 500 mV at a sampling frequency of 100 MHz. It occupies an area of 1470.2 μm² (which is equivalent to 38 μm × 38 μm), which also includes the area of the switches for the CSA that will be used for the single CMUT element.     

A fully on-chip LDO voltage regulator with 37 dB PSRR at 1 MHz for remotely powered biomedical implants

This article presents a fully on-chip low-power LDO voltage regulator dedicated to remotely powered wireless cortical implants. This regulator is stable over the full range of alternating load current and provides fast load regulation achieved by applying a time-domain design methodology. Moreover, a new compensation technique is proposed and implemented to improve PSRR beyond the performance levels which can be obtained using the standard cascode compensation technique. Measurement results show that the regulator has a load regulation of 0.175 V/A, a line regulation of 0.024%, and a PSRR of 37 dB at 1 MHz power carrier frequency. The output of the regulator settles within 10-bit accuracy of the nominal voltage (1.8 V) within 1.6 μs, at full load transition. The total ground current including the bandgap reference circuit is 28 μA and the active chip area measures 290 μm × 360 μm in a 0.18 μm CMOS technology.     

A 1.3 ppm/°C BiCMOS bandgap voltage reference using piecewise-exponential compensation technique

A high-order curvature-compensated BiCMOS bandgap voltage reference using piecewise-exponential compensation technique is presented in this paper. The circuit utilizes a variable gain current mirror to realize exponential compensation as well as a common emitter amplifier with local feedback to achieve a second correction. Implemented in 0.5-μm BCD process, the proposed voltage reference consumes a supply current of 17.5 μA at 2.5 V. A temperature coefficient(TC) of 1.3 ppm/°C, PSRR of more than 76 dB at low frequencies and a line regulation of 160 ppm/V from 2.5 to 5 V are easily achieved, which make it applied widely in portable equipments.     

A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Post-layout Monte Carlo analysis and characterization as function of temperature, process, and mismatch variations of a rail-to-rail full clock fully programmable differential rectifier and sample-and-hold amplifier (RSHA) for biomedical applications are presented in this paper. The RSHA is based on a class AB fully differential two-stage operational amplifier. It uses the Miller compensation capacitor to hold the output and a duplicate of the output stage to ensure proper offset cancellation and common-mode control. The circuit is designed and implemented using a 0.35 μm CMOS technology. Results show that the total harmonic distortion, for an almost rail-to-rail input swing at 10 kHz and at 100 kS/s is equivalent to more than 9 bits in worst case. The dc output offset is below 140 μV and the error introduced by the rectification with respect to the non rectified signal is less than −100 dB. The power consumption is 3 mW with ±1.25 V supplies. The RSHA provides an output valid for more than 85% of the clock cycle.     

Winner-Take-All Class AB Input Stage

A novel technique to implement class AB differential amplifier input stages is proposed. It is based on the use of Winner-Take-All circuits for achieving dynamic current boosting, and is well suited for low-voltage operation. Experimental measurements of an OTA using this technique, fabricated in a 0.5-μm CMOS technology, show a slew rate of 92 V/μs for an 80-pF load and 120 μW of static power consumption.     

A 122 TΩ Hz transimpedance bandwidth product BiCMOS optical sensor front-end with a 54.7 dB voltage-controlled photo-sensitivity range

An optical sensor front-end with integrated PIN photodiode in 0.6 μm BiCMOS technology intended for universal optical storage operation is presented. It is based on a mixed current conveyor and voltage amplifiers topology avoiding stability problems. The transimpedance is continuously variable and directly proportional to a voltage-controlled resistance. Another voltage-controlled resistor within a variable-gain voltage amplifier increases the photo-sensitivity range. A fixed-gain voltage amplifier and a current biasing of the current conveyor enable frequency bandwidth enhancement leading to a large transimpedance bandwidth product. A linearity error smaller than 2.8%, a photo-sensitivity range of 541 (54.7 dB) with the largest photo-sensitivity of 2468 mV/μW, an offset voltage <13.7 mV, a frequency bandwidth up to 277 MHz, a slew rate up to 377 V/μs, a transimpedance bandwidth product up to 122 TΩ Hz, and a maximum power consumption of <4.3 mW are achieved.     

A multistage amplifier technique with embedded frequencycompensation

A new multistage operational amplifier topology requires only N-2 embedded compensation networks for N gain stages. The compensation circuits do not load the output stage, and noninverting gain stages are not required as in previous multistage approaches. Consequently, high gain, wide bandwidth, fast slewing, and excellent power efficiency are achieved. A low-power resistance-capacitance compensation technique assures stability and fast settling over process, voltage, and temperature variations. Implemented in a 0.6-μm n-well CMOS process, a single ended three-stage prototype dissipates 6.9 mW at 3.0 V with 102 dB gain, 47 MHz bandwidth, and 69 V/μs average slew rate with 40 pF load     

0.8 V bulk-driven operational amplifier

A low-voltage bulk-driven CMOS operational amplifier is proposed in this paper. The inherent small transconductance of the bulk-driven devices is enlarged using a positive feedback, improving also the noise performance. The amplifier is designed using standard 0.18 μm n-well CMOS process. Although the amplifier is optimized for 0.8 V supply voltage, it is also capable to operate under supply voltage of 0.7 V. The amplifier consumes 130 μΑ, performing 56 dB open-loop gain, 154 nV/√Hz input-referred spot noise at 100 kHz, 80 dB CMRR at 100 kHz and IIP3 equal to −4.7 dBV.     

A 0.5 V bulk-input OTA with improved common-mode feedback for low-frequency filtering applications

This paper presents the design of a two-stage pseudo-differential operational transconductance amplifier (OTA) and its application in low-frequency continuous time filters. The OTA was designed in a 0.18 μm, 0.45 V V _T CMOS process. An improved bulk-mode common-mode feedback (CMFB) circuit has been designed which does not load the OTA compared to prior art. A self cascode load structure and partial positive feedback provide higher gain. The bulk terminals of all transistors have been biased to lower their threshold voltages (V_T) and maximize signal swing. The OTA operates at a supply voltage of 0.5 V and consumes only 28 μW of power. Rail-to-rail input is made possible by using the transistor’s bulk terminal as the input. For a load of 20 pF the OTA has a measured DC gain of 63 dB and a gain-bandwidth product of 570 kHz. To demonstrate the use of the OTA in practical circuits, three active RC filters were designed: a 10 kHz Butterworth filter, a 10 kHz Bessel filter, and a 2.5 kHz Tschebycheff filter.     

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 µA. A final benchmark comparison considering all relevant performance metrics is presented.     

A CMOS low-distortion fully differential power amplifier withdouble nested Miller compensation

A four-stage fully differential power amplifier using a double-nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and stability conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and total harmonic distortion (THD) is -83 dB for a -V_p-p differential output signal at 10 kHz and a load of 50 Ω. With an 8 Ω load and for a 10-kHz, 4-V _p-p output signal, THD is -68 dB. The chip area is 0.625 mm ² in a 1.5-μm single-poly, double-metal, n-well CMOS technology     

A 0.5-V 90-dB SNDR 102 dB-SFDR audio-band continuous-time delta–sigma modulator

A 0.5-V high performance continuous-time one-bit delta–sigma modulator is reported for audio applications. High performance under this ultra-low supply is achieved by a feed-forward modulator architecture for reduced integrator swing, a special switched-capacitor-resistor feedback for less sensitivity to jitter noise, and a fast-settling fully differential amplifier. The synthesized modulator also has a high thermal-noise-limited SNR of 91 dB over a 20 kHz bandwidth. The 0.5-V fully-differential gate-input amplifier employs an adaptive common-mode feedback frequency compensation circuit, which leads to a robust modulator performance against process, supply voltage and temperature variations. Fabricated in a standard 0.13 μm CMOS process, the modulator achieves a spurious-free dynamic range (SFDR) of 101.9 dB and a signal-to-noise plus distortion ratio (SNDR) of 90 dB (A-weighted) over a 20-kHz signal bandwidth, with the latter being very close to the thermal noise limit. The modulator operates over a supply range from 0.4 to 0.75 V and a temperature range from −20 to 90°C.     

A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation

A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-/spl mu/m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V//spl mu/s average slew rate while only dissipating 330 /spl mu/W at 1.5 V, when driving a 25-k/spl Omega///120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.     

A monolithic isolation amplifier in silicon-on-insulator CMOS: Testing and applications

In this paper, the design and test results of a 4-channel digital isolation amplifier are presented, along with results of a prototype power converter circuit using the amplifier for voltage feedback regulation. The amplifier uses a capacitive coupling technique to transfer digital signals from input to output while preserving galvanic isolation between the two. The isolation amplifier was fabricated in a 0.5 μm Silicon-on-Sapphire (SOS) technology and uses the isolation properties of the SOS substrate to achieve more than 800 V isolation between input and output grounds. Each of the four channels can operate in excess of 100 Mbps using a differential transmission scheme to reject ground bounce transients up to 1 V/μs. The input circuit can be powered from an on-chip charge-pump to permit single supply operation. The device can be used in a wide variety of applications that require passing signals across an isolation barrier: power supplies, remote sensing, and medical and industrial applications.     

Rail-to-rail BiCMOS operational amplifier using input signal adapters with floating outputs

An operational amplifier with rail-to-rail input and output voltage range in 0.6 μm BiCMOS technology is presented. Two simple input signal adapters with floating outputs serving as pre-stages are introduced. They are followed by a differential amplifier. The adapters translate the input signals into a floating level within the operating region of the differential amplifier, enabling rail-to-rail operation. An inverter-based simple rail-to-rail class AB output stage has been used. With a single supply of 1.5 V, the proposed rail-to-rail operational amplifier achieves 72 dB DC open-loop gain, 2.54 MHz unity-gain frequency, 62° phase margin, 2.5 V/μs slew rate, and 147 μW power consumption.     

2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

This paper reports an optical preamplifier intended for low-cost fiber-optic receivers. The preamplifier is based on a resistive shunt-feedback topology, is power-optimized and employs two different frequency compensation techniques, phantom zeros and shunt-peaking. The circuit is designed in a 1.8 V 0.18 μm CMOS technology. Experimental results report a transresistance of 58 dBΩ and a bandwidth of 1.5 GHz, respectively. Eye diagrams obtained at 2.5 Gb/s show a total jitter of 18 ps and a bit error rate (BER) of 10⁻¹² when the input current amplitude (I_in) is equal to or higher than 8.5 μA. Higher bit rates up to 3 Gb/s also have been tested achieving a BER of 10⁻¹² when I_in ≥9.5 μA. The power consumption and die active area are 23.7 mW and 0.017 mm², respectively.     

Multistage amplifier topologies with nested Gm-Ccompensation

This paper presents a multistage amplifier for low-voltage applications (<2 V). The amplifier consists of simple (noncascode) low gain stages and is stabilized using a nested transconductance-capacitance compensation (NGCC) scheme. The resulting topology is similar to the well known nested Miller compensation (NMC) multistage amplifier, except that the proposed topology contains extra G _m feedforward stages which are used to enhance the amplifier performance. The NGCC simplifies the transfer function of the proposed multistage amplifier which, in turn, simplifies its stability conditions. A comparison between the NGCC and NMC shows that the NGCC has wider bandwidth and is easier to stabilize. A four-stage NGCC amplifier has been fabricated using a 2-μm CMOS process and is tested using a ±1.0 V power supply. A dc gain of 100 dB has been measured. A gain bandwidth product of 1 MHz with 58° of phase margin and power of 1.4 mW can be achieved. The op amp occupies an active area of 0.22 mm². Step response shows that the op amp is stable     

A 50‐mA 1‐nF Low‐Voltage Low‐Dropout Voltage Regulator for SoC Applications

In this paper, we present a low‐voltage low‐dropout voltage regulator (LDO) for a system‐on‐chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1‐nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop‐out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.     

High efficiency,high switching speed,AlGaAs/GaAs P-HEMT DC–DC converter for integrated power amplifier modules

This paper presents a high efficiency, high switching frequency DC–DC buck converter in AlGaAs/GaAs technology, targeting integrated power amplifier modules for wireless communications. The switch mode, inductor load DC–DC converter adopts an interleaved structure with negatively coupled inductors. Analysis of the effect of negative coupling on the steady state and transient response of the converter is given. The coupling factor is selected to achieve a maximum power efficiency under a given duty cycle with a minimum penalty on the current ripple performance. The DC–DC converter is implemented in 0.5 μm GaAs p-HEMT process and occupies 2 × 2.1 mm² without the output network. An 8.7 nH filter inductor is implemented in 65 μm thick top copper metal layer, and flip chip bonded to the DC–DC converter board. The integrated inductor achieves a quality factor of 26 at 150 MHz. The proposed converter converts 4.5 V input to 3.3 V output for 1 A load current under 150 MHz switching frequency with a measured power efficiency of 84%, which is one of the highest efficiencies reported to date for similar current/voltage ratings.     

Design of a 1-V High-Frequency Bipolar Operational Amplifier

This paper presents the design of a low-voltage high-frequency operational amplifier implemented in bipolar technology. The minimum power supply voltage for this amplifier can be as low as 0.9 V, so it is suitable for portable equipment applications. The design emphasis is on the high frequency response. A pole-zero cancellation compensation technique and a special low-voltage design gives a simulated cutoff frequency of about 175 MHz with a 50° phase margin at a power supply voltage of ±0.5 V with a 10 k load resistance; the low-frequency voltage gain is 110 dB. The common-mode input range includes, and can exceed, the negative supply voltage by about 400 mV. A complimentary class-B type output stage enables the output voltage to reach both supply rails within about 100 mV without significant signal distortion. This amplifier dissipates 875 W.