Electrical and reliability characterization of metal-gate/HfO2/Ge FET’s with Si passivation

Field-effect transistors with metal gate and HfO₂ gate dielectric on silicon-passivated germanium substrate are studied. Capacitance-Voltage characteristics show lower gate capacitance at negative gate voltages, irrespective of the device channel polarity. Possible mechanisms for this asymmetry are discussed. Reliability of the metal/high-k gate stack on sub-micron p-channel transistors is evaluated. Time-dependent dielectric breakdown analysis indicates comparable gate-stack quality on germanium and silicon substrates.     

Effects of hot-carrier trapping in n- and p-channel MOSFET's

Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFET's down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFET's. A hot-electron gate current is present not only in n-channel MOSFET's, but also in p-channel MOSFET's where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFET's, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.     

A new self-consistent modeling approach to investigating MOSFETdegradation

A modeling tool is presented that allows a complete analysis of a DC stress experiment without assuming the location and amount of trapped oxide charges and interface states. To describe the buildup of oxide damage, a semiempirical rate equation approach is outlined. A completely self-consistent calculation is presented of the time dependence of the DC stress experiment. This calculation monitors the amount and location of charges built up in the 2-D oxide region during the stress line. The model includes competing trap mechanisms such as the formation of interface states and fixed oxide traps. This permits consideration of n- and p-channel MOSFETs with the same model. The calculations are compared to DC stress measurements on n- and p-channel devices with gate lengths of 0.65 μm that are typical for 16-Mb DRAMs     

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

Threshold voltage, field effect mobility, and gate-to-channelcapacitance in polysilicon TFTs

Based on experimental and theoretical studies of n- and p-channel polysilicon thin film transistors with gate W/L ratios from 0.3 to 3.3, we have demonstrated that the threshold voltage extracted from gate to channel capacitance data results in field effect mobility parameters which are independent of device geometry. The parameters extracted using this V_t allow us to reproduce the I-V characteristics of the n- and p channel TFTs over wide ranges of bias voltages and gate sizes. The C_gc-V_GS characteristics of polysilicon TFTs are strongly affected by the trapping and de-trapping of carriers. As a result, the measured C_gc characteristic is a function of measurement frequency and gate length. However, we demonstrate that to the first order, the frequency dispersion of the C_gc curve can be related to the effective carrier transit time determined using the V_GS dependent field effect mobility     

IGFET circuit performance-n-channel versus p-channel

The n-channel insulated-gate field-effect transistor offers a factor of 2 to 3.4 mobility advantage (depending on crystal orientation and substrate doping level) over p-channel devices. In addition, several advantages result from the fact that the work function difference between an aluminum gate and the silicon substrate is about -0.8 volt for a p substrate compared with about zero for an n substrate. In particular, this results in a low threshold voltage that allows the use of a substrate bias to adjust the threshold voltage over a useful design range resulting in an added flexibility in choice of thresholds and substrate doping, a reduction in the effect of source-substrate bias on device threshold, decreased junction capacitance, and larger parasitic thick-oxide thresholds for a given insulator thickness. The speed, power, and density advantages of the n-channel device are illustrated for logic and memory circuits using representative n- and p-channel device designs.     

Gate-self-aligned p-channel germanium MISFETs

The authors have fabricated the first gate-self-aligned germanium MISFETs and have obtained record transconductance for germanium FETs. The devices fabricated are p-channel, inversion-mode germanium MISFETs. A germanium-oxynitride gate dielectric is used and aluminum gates, serve as the mask for self-aligned source and drain implants. A maximum room-temperature transconductance of 104 mS/mm was measured for a 0.6-μm gate length. A hole inversion channel mobility of 640 cm² /V-s was calculated using transconductance and capacitance data from long-channel devices. This large hole channel mobility suggests that germanium may be an attractive candidate for CMOS technology     

Switch the n-type to ambipolar transfer characteristics by illumination in n-type pentacene-based organic field-effect transistors

This work investigates the suppression of n-channel and the switch of transfer characteristics (from n-type to ambipolar) by illumination in n-type pentacene-based organic field-effect transistors (OFETs). The illumination outcomes differently on the output characteristics of OFETs, which markedly decreases the magnitude of drain current (n-channel) and shifts the turn-on voltage to a higher positive bias in the n-type regime, but induces the formation of p-channel in the p-type regime. We attribute that the trapped negative charges in the device as induced by illumination electrostatically shield the effective electrical field applied to the gate with source/drain electrodes and modulate the device performance. The result of quasi-static capacitance–voltage measurement agrees well with the modulations of the transfer characteristics for n-type OFETs by illumination. In addition, the de-trapping of charges recovers the n-type only output characteristics of pentacene-based OFETs. This study highlights the unique photo responses of n-type pentacene-based OFETs to the development of phototransistors of distinct output characteristics operated in n- and p-type regime.     

Parasitic MOSFET degradation induced by Fowler-Nordheim injection

Degradation induced by Fowler-Nordheim (F-N) electron injection is observed in a parasitic MOS transistor associated with a MOS transistor's edge region. A bump appears in the subthreshold region of both an n-channel transistor after positive gate biased F-N injection and a p-channel transistor after negative gate biased F-N injection. It is found that the effective gate-oxide thickness of a parasitic transistor is 30 nm. As thinner gate oxide is used, the amount of the charge injected into the gate oxide may increase due to increased electric fields     

La2O3 gate dielectrics for AlGaN/GaN HEMT

The annealing temperature dependent electrical characteristics of La₂O₃ gate dielectrics for W gated AlGaN/GaN high electron mobility transistors (HEMTs) have been characterized. The threshold voltage (V_th) has been found to shift to positive direction with higher temperature annealing, exceeding those of Schottky HEMTs, presumably attributed to the presence of negative fixed charges at the interface between La₂O₃ and AlGaN layers. At a high temperature annealing over 500 °C, a high dielectric constant (k-value) of 27 has been achieved with poly-crystallization of the La₂O₃ film, which is useful to limit the reduction in gate capacitance. A high k-value for La₂O₃ gate dielectrics and the presence of negative charges at the interface are attractive for AlGaN/GaN HEMTs with low gate leakage and normally-off operation.     

GaAs FET device and circuit simulation in SPICE

We have developed a GaAs FET model suitable for SPICE Circuit simulations. The dc equations are accurate to about 1 percent of the maximum drain current. A simple but accurate interpolation formula for drain current as a function of gate-to-source voltage connects the square-law behavior just above pinchoff and the square-root law for larger values of the drain current. The ac equations, with charge-storage elements, describe the variation of the gate-to-source and gate-to-drain capacitances as the drain-to-source voltage approaches zero and when this voltage becomes negative. Under normal operating conditions the gate-to-source capacitance is much larger than the gate-to-drain capacitance. At zero drain-to-source voltage both capacitances are about equal. For negative drain-to-source voltages the original source acts like a drain and vice versa. Consequently the normally large gate-to-source capacitance becomes small and acts like a gate-to-drain capacitance. In order to model these effect it is necessary to realize that, contrary to conventional SPICE usage, there are no separate gate-to-source and gate-to-drain charges, but that there is only one gate Charge which is a function of gate-to-source and gate-to-drain voltages. The present treatment Of these capacitances permits simulations-in which the drain-to-source voltage reverses polarity, as occurs in pass-gate circuits.     

Novel self-limiting high-speed program scheme of p-channel DINORflash memory with n-channel select transistors

This paper describes a novel self-limiting high-speed program scheme of the p-channel DINOR (D_I_vided bit line N_O_R_) flash memory utilizing n-channel select transistors. This scheme makes it possible to maintain the high programming throughput of the p-channel DINOR even for future lower-voltage operation. Using this scheme, programming stops automatically at the desired threshold voltage state without any conventional verify operations. Moreover, the only structural change from the conventional p-channel DINOR is the change of the impurity type of the select transistors, and the only operational change is the addition of a very short negative voltage pulse of 0.1 μs to each programming gate pulse. This shortness of the additional pulse hardly degrades the programming speed at all. This novel scheme is expected to become a key technology for the realization of future, high-performance, lower-supply-voltage p-channel DINOR flash memories     

TOM3 capacitance model: linking large- and small-signal MESFETmodels in SPICE

Improved accuracy in the modeled gate capacitance of GaAs metal-semiconductor field-effect transistors (MESFET's) is obtained in SPICE using conservation of charge in an implanted layer. The gate junction creates a natural partition between mobile and fixed channel charges. Relating the gate charge to the channel current creates gate capacitances dependent upon the channel current derivatives linking the small-signal model to the large-signal equations. Results are illustrated using a depletion-mode MESFET     

Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-$kappa$ Gate Dielectrics

In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO₂ and HfSiO_x, high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher I_on/I_off current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V_th), relative to conventional deposited-SiO₂, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiO_x, as the gate dielectric had ca. 1.73 times the mobility (mu_FE) relative to that of the deposited-SiO₂ TFTs; in contrast, the HfO₂ TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO₂ TFTs. The immunity of the HfSiO_x, TFTs was better than that of the HfO₂ TFTs-in terms of their V_th shift, SS degradation, mu_FE degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiO_x, rather than HfO₂, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.     

Comparison between the effects of positive noncatastrophic HBM ESDstress in n-channel and p-channel power MOSFETs

The effect of noncatastrophic positive human body model (HBM) electrostatic discharge (ESD) stress on n-channel power MOSFETs is radically different from that on p-channel MOSFETs. In n-channel transistors, the stress causes negative shifts of the current-voltage characteristics indicative of positive charge trapping in the gate oxide. In p-channel transistors, the stress increases the drain-to-source leakage current, probably due to localized avalanche electron injection from the p-doped drain     

Adiabatic differential voltage switch logic

To diminish the trapped charges in internal nodes of the complex logic adiabatic gate, adiabatic differential voltage switch logic (ADVSL) using capacitance coupling technique is presented. An adiabatic system, based on a relatively small number of complex ADVSL gates, reduces not only dissipation loss, but also the gate count greatly.     

Hole and electron current transport inmetal-oxide-nitride-oxide-silicon memory structures

The carrier transport properties in metal-oxide (top oxide) nitride-oxide (tunnel oxide) silicon (MONOS) memory structures have been investigated in steady-state conditions under negative gate bias voltage. Carriers were separated into holes and electrons utilizing an induced junction of the p-channel MONOS transistors. Two-carrier transport is confirmed in the structure at negative gate polarity. It is found that the relatively thick top oxide acts as a potential barrier to the holes injected from the Si into the thin nitride. It is also found that a portion of the electrons injected from the gate at negative gate polarity recombine with the holes injected from the Si even in such a thin nitride and/or at the top-oxide/nitride interface     

Negative bias temperature instability: What do we understand?

We present a brief overview of negative bias temperature instability (NBTI) commonly observed for in p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) when stressed with negative gate voltages at elevated temperatures and discuss the results of such stress on device and circuit performance and review interface traps and oxide charges, their origin, present understanding, and changes due to NBTI. Next we discuss some of the models that have been proposed for both NBTI degradation and recovery and p- versus n-MOSFETs. We also address the time and energy dependence effects of NBTI and crystal orientation. Finally we mention some aspect of circuit degradation. The general conclusion is that although we understand much about NBTI, several aspects are poorly understood. This may be due to a lack of a basic understanding or due to varying experimental data that are likely the result of sample preparation and measurement conditions.     

积累模式p沟道SOI基围栅Fin-FET驱动电流的研究

通过比较,研究了积累模式p沟道围栅Fin-FET的驱动电流。积累模式p沟道围栅Fin-FET的驱动电流比具有同样结构的反型模式p沟道Fin-FET的驱动电流大15% ~ 26%,这是因为前者存在体输运,但随着栅极偏压的增大体输运电流的比重逐渐减小。积累模式p沟道围栅Fin-FET的驱动电流比积累模式p沟道平面FET的驱动电流大50%,这起因于前者有效输运表面的展宽和体积累。其中有效输运表面展宽源于围栅结构感应的多表面输运,而体积累（即Fin截面中任何位置的多子浓度超过了掺杂浓度）源于围栅结构不同方向上电场的耦合。另外,对于积累模式p沟道围栅Fin-FET,由于不同输运方向和输运表面迁移率的差别,沟道沿<110>方向比沿<100>方向有较大的驱动电流,这在较大的栅极偏压使表面输运电流在总电流中占主导时变得更为明显。