The C-V-f and G/ω-V-f characteristics of Al/SiO2/p-Si (MIS) structures

The frequency dependence of capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of the Al/SiO₂/p-Si metal-insulator-semiconductor (MIS) structures has been investigated taking into account the effect of the series resistance (R_s) and interface states (N_ss) at room temperature. The C-V and G/ω-V measurements have been carried out in the frequency range of 1 kHz to 1 MHz. The frequency dispersion in capacitance and conductance can be interpreted only in terms of interface states and series resistance. The N_ss can follow the ac signal and yield an excess capacitance especially at low frequencies. In low frequencies, the values of measured C and G/ω decrease in depletion and accumulation regions with increasing frequencies due to a continuous density distribution of interface states. The C-V plots exhibit anomalous peaks due to the N_ss and R_s effect. It has been experimentally determined that the peak positions in the C-V plot shift towards lower voltages and the peak value of the capacitance decreases with increasing frequency. The effect of series resistance on the capacitance is found appreciable at higher frequencies due to the interface state capacitance decreasing with increasing frequency. In addition, the high-frequency capacitance (C_m) and conductance (G_m/ω) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance. Experimental results show that the locations of N_ss and R_s have a significant effect on electrical characteristics of MIS structures.     

Analysis of interface states and series resistance of MIS Schottky diodes using the current-voltage (I-V) characteristics

The purpose of this paper is to analyze interface states in Al/SiO₂/p-Si (MIS) Schottky diodes and determine the effect of SiO₂ surface preparation on the interface state energy distribution. The current-voltage (I-V) characteristics of MIS Schottky diodes were measured at room temperature. From the I-V characteristics of the MIS Schottky diode, ideality factor (n) and barrier height (Φ_B) values of 1.537 and 0.763 eV, respectively, were obtained from a forward bias I-V plot. In addition, the density of interface states (N_ss) as a function of (E_ss-E_v) was extracted from the forward bias I-V measurements by taking into account both the bias dependence of the effective barrier height (Φ_e), n and R_s for the MIS Schottky diode. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. In addition, the values of series resistance (R_s) were determined using Cheung’s method. The I-V characteristics confirmed that the distribution of N_ss, R_s and interfacial insulator layer are important parameters that influence the electrical characteristics of MIS Schottky diodes.     

On the energy distribution of interface states and their relaxation time and capture cross section profiles in Al/SiO2/p-Si (MIS) Schottky diodes

The energy distribution profile of the interface states (N_ss) and their relaxation time (τ) and capture cross section (σ_p) of metal-insulator-semiconductor (Al/SiO₂/p-Si) Schottky diodes have been investigated by using the high-low frequency capacitance and conductance methods. The capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of these devices were investigated by considering series resistance (R_s) effects in a wide frequency range (5 kHz-1 MHz.). It is shown that the capacitance of the Al/SiO₂/p-Si Schottky diode decreases with increasing frequency. The increase in capacitance especially at low frequencies results form the presence of interface states at Si/SiO₂ interface. The energy distributions of the interface states and their relaxation time have been determined in the energy range of (0.362-E_v)-(0.512-E_v) eV by taking into account the surface potential as a function of applied bias obtained from the measurable C-V curve (500 Hz) at the lowest frequency. The values of the interface state density (N_ss) ranges from 2.34 × 10¹² to 2.91 ×  10¹² eV⁻¹/cm², and the relaxation time (τ) ranges from 1.05 × 10⁻⁶ to 1.58 × 10⁻⁴ s, showing an exponential rise with bias from the top of the valance band towards the mid-gap.     

On the temperature dependence of series resistance and interface states in Al/SiO2/p-Si (MIS) Schottky diodes

The capacitance-voltage-temperature (C-V-T) and conductance-voltage-temperature (G/w-V-T) characteristics of metal-semiconductor (Al/p-Si) Schottky diodes with thermal growth interfacial layer were investigated by considering series resistance effect in the wide temperature range (80-400 K). It is found that in the presence of series resistance, the forward bias C-V plots exhibit a peak, and experimentally shows that the peak positions shift towards higher positive voltages with increasing temperature, and the peak value of the capacitance has a maximum at 80 K. The C-V and (G/w-V) characteristics confirm that the N_ss and R_s of the diode are important parameters that strongly influence the electric parameters in (Al/SiO₂/p-Si) MIS Schottky diodes. The crossing of the G/w-V curves appears as an abnormality when seen with respect to the conventional behaviour of the ideal MS or MIS Schottky diode. It is thought that the presence of a series resistance keeps this intersection hidden and unobservable in homogeneous Schottky diodes, but it appears in the case of inhomogeneous Schottky diode. In addition, the high frequency (C_m) and conductance (G_m/w) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance.     

On the profile of frequency dependent series resistance and surface states in Au/Bi4Ti3O12/SiO2/n-Si(MFIS) structures

The frequency dependent capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of the metal-ferroelectric-insulator-semiconductor (Au/Bi₄Ti₃O₁₂/SiO₂/n-Si) structures (MFIS) were investigated by considering series resistance (R_s) and surface state effects in the frequency range of 1 kHz-5 MHz. The experimental C-V-f and G/ω-V-f characteristics of MFIS structures show fairly large frequency dispersion especially at low frequencies due to R_s and N_ss. In addition, the high frequency capacitance (C_m) and conductance (G_m/ω) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real capacitance of MFIS structures. The R_s-V plots exhibit anomalous peaks between inversion and depletion regions at each frequency and peak positions shift towards positive bias with increasing frequency. The C⁻²-V plot gives a straight line in wide voltage region, indicating that interface states and inversion layer charge cannot follow the ac signal in the depletion region, but especially in the strong inversion and accumulation region. Also, it has been shown that the surface state density decreases exponentially with increasing frequency. The C-V-f and G/w-V-f characteristics confirm that the interface state density (N_ss) and series resistance (R_s) of the MFIS structures are important parameters that strongly influence the electrical properties of MFIS structures.     

On the profile of temperature dependent series resistance in Al/Si3N4/p-Si (MIS) Schottky diodes

The temperature dependence of capacitance-voltage (C-V) and conductance-voltage (G/w-V) characteristics of metal-insulator-semiconductor (Al/Si₃N₄/p-Si) Schottky barrier diodes (SBDs) was investigated by considering series resistance effect in the temperature range of 80-300 K. It is found that in the presence of series resistance, the forward bias C-V plots exhibit a peak, and experimentally show that the peak positions with a maximum at 260 K shift toward lower voltages with increasing temperature. The C-V and (G/w-V) characteristics confirm that the interface state density (N_ss) and series resistance (R_s) of the diode are important parameters that strongly influence the electric parameters of MIS structures. The crossing of the G/w-V curves appears as an abnormality compared to the conventional behavior of ideal Schottky diode. It is thought that the presence of series resistance keeps this intersection hidden and unobservable in homogeneous Schottky diodes, but it appears in the case of inhomogeneous Schottky diode. In addition, the high frequency (C_m) and conductance (G_m/w) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance.     

碲化镉肖特基势垒的温度依赖关系

本文通过对Au/n-CdTe肖特基二极管I-V-T测量得出:在室温附近,势垒高度随温度升高而线性增加,增加速率约为 9 ×10~(-4)eV/K.这一结果与 Hattori 等对InP的研究结果一致,     

The interface states analysis of the MIS structure as a function of frequency

The energy distribution of interface states (N_ss) and their relaxation time (τ) were of the fabricated the Al/SiO₂/p-Si (MIS) structures were calculated using the forward bias current-voltage (I-V), capacitance-frequency (C-f) and conductance-frequency (G-f) measurements. Typical ln[I/(1 − exp(−qV/kT)] versus V characteristics of MIS structure under forward bias show one linear region. From this region, the slope and the intercept of this plot on the current axis allow to determine the ideality factor (n), the barrier height (Φ_b) and the saturation current (I_S) evaluated to 1.32, 0.77 eV and 3.05 × 10⁻⁹ A, respectively. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer at metal-semiconductor interface, the interface states and barrier inhomogeneity of the device. The energy distribution of interface states (N_ss) and their relaxation time (τ) have been determined in the energy range from (0.37 − E_v) to (0.57 − E_v) eV. It has been seen that the N_ss has almost an exponential rise with bias from the mid gap toward the top of valance band. In contrary to the N_ss, the relaxation time (τ) shows a slow exponential rise with bias from the top of the E_v towards the mid gap energy of semiconductor. The values of N_ss and τ change from 6.91 × 10¹³ to 9.92 × 10¹³ eV⁻¹ cm⁻² and 6.31 × 10⁻⁴ to 0.63 × 10⁻⁴ s, respectively.     

On the profile of frequency dependent series resistance and dielectric constant in MIS structure

In this study, the frequency dependent of the forward and reverse bias capacitance-voltage (C-V) and conductance-voltage (G/ω - V) measurements of Al/SiO₂/p-Si (MIS) structures are carried out in frequency range of 10 kHz-10 MHz. The frequency dependence of series resistance (R_s), density of surface states (N_ss), dielectric constant (ε′), dielectric loss (ε″), dielectric loss tangent (tan δ) and the ac electrical conductivity (σ_dc) are studied for these structure at room temperature. Experimental results show that both electrical and dielectric parameters were strongly frequency and voltage dependent. The ε′ and ε″ are found to decrease with increasing frequency while σ_ac is increased. Also, both the effects of surface states N_ss and R_s on C-V and G/ω - V characteristics are investigated. It has been seen that the measured C and G decrease with increasing frequency due to a continuous distribution of N_ss in frequency range of 10 kHz-1 MHz. The effect of R_s on the C and G are found noticeable at high frequencies. Therefore, the high frequencies C and G values measured under both reverse and forward bias were corrected for the effect of series resistance R_s to obtain real MIS capacitance C_c and conductance G_c using the Nicollian and Goetzberger technique. The distribution profile of R_s-V gives a peak in the depletion region at low frequencies and disappears with increasing frequencies.     

Temperature and frequency dependent electrical and dielectric properties of Al/SiO2/p-Si (MOS) structure

The electrical and dielectric properties of Al/SiO₂/p-Si (MOS) structures were studied in the frequency range 10 kHz-10 MHz and in the temperature range 295-400 K. The interfacial oxide layer thickness of 320 Å between metal and semiconductor was calculated from the measurement of the oxide capacitance in the strong accumulation region. The frequency and temperature dependence of dielectric constant (ε′), dielectric loss (ε″), dielectric loss tangent (tan δ) and the ac electrical conductivity (σ_ac) are studied for Al/SiO₂/p-Si (MOS) structure. The electrical and dielectric properties of MOS structure were calculated from C-V and G-V measurements. Experimental results show that the ε′ and ε″ are found to decrease with increasing frequency while σ_ac is increased, and ε′, ε″, tan δ and σ_ac increase with increasing temperature. The values of ε′, ε″ and tan δ at 100 kHz were found to be 2.76, 0.17 and 0.06, respectively. The interfacial polarization can be more easily occurred at low frequencies, and the number of interface state density between Si/SiO₂ interface, consequently, contributes to the improvement of dielectric properties of Al/SiO₂/p-Si (MOS) structure. Also, the effects of interface state density (N_ss) and series resistance (R_s) of the sample on C-V characteristics are investigated. It was found that both capacitance C and conductance G were quite sensitive to temperature and frequency at relatively high temperatures and low frequencies, and the N_ss and R_s decreased with increasing temperature. This is behavior attributed to the thermal restructuring and reordering of the interface. The C-V and G/ω-V characteristics confirmed that the N_ss, R_s and thickness of insulator layer (δ) are important parameters that strongly influence both the electrical and dielectric parameters and conductivity in MOS structures.     

Investigation of Ta2O5/SiO2/4H-SiC MIS capacitors

Tantalum pentoxide (Ta₂O₅) deposited by pulsed DC magnetron sputtering technique as the gate dielectric for 4H-SiC based metal-insulator-semiconductor (MIS) structure has been investigated. A rectifying current-voltage characteristic was observed, with the injection of current occurred when a positive DC bias was applied to the gate electrode with respect to the n type 4H-SiC substrate. This undesirable behavior is attributed to the relatively small band gap of Ta₂O₅ of around 4.3 eV, resulting in a small band offset between the 4H-SiC and Ta₂O₅. To overcome this problem, a thin thermal silicon oxide layer was introduced between Ta₂O₅ and 4H-SiC. This has substantially reduced the leakage current through the MIS structure. Further improvement was obtained by annealing the Ta₂O₅ at 900 °C in oxygen. The annealing has also reduced the effective charge in the dielectric film, as deduced from high frequency C-V measurements of the Ta₂O₅/SiO₂/4H-SiC capacitors.     

Current transport mechanisms and deep level transient spectroscopy of Au/n-Si Schottky barrier diodes

The temperature-dependent electrical characteristics of the Au/n-Si Schottky diodes have been studied in the temperature range of 40-300 K. Current density-voltage (J-V) characteristics of these diodes have been analyzed on the basis of thermionic emission theory with Gaussian distribution model of barrier height. The basic diode parameters such as rectification ratio, ideality factor and barrier height were extracted. Under a reverse bias, the conduction process at low voltage is determined by Schottky emission over a potential barrier but at higher voltage the Poole Frenkel effect is observed. The capacitance-voltage (C-V) features of the Au/n-Si Schottky diodes were characterized in the high frequency of 1 MHz. The barrier heights values obtained from the J-V and C-V characteristics have been compared. It has been seen that the barrier height value obtained from the C-V measurements is higher than that obtained from the J-V measurements at various temperatures. Possible explanations for this discrepancy are presented. Deep level transient spectroscopy (DLTS) has been used to investigate deep levels in Au/n-Si. Three electron trap centers, having different emission rates and activation energies, have been observed. It is argued that the origin of these defects is of intrinsic nature. A correlation between C-V and DLTS measurements is investigated.     

Frequency and gate voltage effects on the dielectric properties of Au/SiO2/n-Si structures

To determine the dielectric constant (ε′), dielectric loss (ε″), loss tangent (tan δ), the ac electrical conductivity (σ_ac) and the electric modulus of Au/SiO₂/n-Si structure, the measurement admittance technique was used. Experimental results show that the values of ε′, ε″, tan δ, σ_ac and the electric modulus show fairly large frequency and gate bias dispersion especially at low frequencies due to the interface charges and polarization. An increase in the values of the ε′ and ε″ were observed with both a decrease in frequency and an increase in frequency. The σ_ac is found to increase with both increasing frequency and voltage. In addition, the experimental dielectrical data have been analyzed considering electric modulus formalism. It can be concluded that the interface charges and interfacial polarization have strong influence on the dielectric properties of metal-insulator-semiconductor (MIS) structures especially at low frequencies and both in depletion and accumulation regions.     

AC response analysis of C-V curves and quantitative analysis of conductance curves in Al2O3/InP interfaces

The ac signal response of majority carriers has been systematically investigated for Al₂O₃/InP metal-insulator-semiconductor (MIS) interfaces using C-V and the conductance methods. It was revealed by the conductance curve fitting that both slow trap and interface trap responses contribute to a conductance curve at the Al₂O₃/InP interfaces in the depletion bias condition, and that the contribution of slow trap response and large surface potential fluctuation make it difficult to obtain a clear conductance peak. It was found that the conductance curves in high frequency region can be represented by the surface potential fluctuation model. This means that the analysis through the conductance curve fitting is effective in characterizing III-V MIS interfaces.     

Calculation from the current-voltage and capacitance-voltage measurements of characteristics parameters of Cd/CdS/n-Si/Au-Sb structure with CdS interface layer grown on n-Si substrate by SILAR method

The CdS thin film has been directly formed on n-type Si substrate to form an interfacial layer between cadmium (Cd) and n-type Si with Successive Ionic Layer Adsorption and Reaction (SILAR) method. An Au-Sb electrode has been used as an ohmic contact. The Cd/CdS/n-Si/Au-Sb structure has demonstrated clearly rectifying behaviour by the current-voltage (I-V) curves studied at room temperature. The characteristics parameters such as barrier height, ideality factor and series resistance of Cd/CdS/n-Si/Au-Sb structure have been calculated from the forward bias I-V and reverse bias C⁻²-V characteristics. The diode ideality factor and the barrier height have been calculated as n = 2.06 and Φ_b = 0.92 eV by applying a thermionic emission theory, respectively. The diode shows non-ideal I-V behaviour with an ideality factor greater than unity that can be ascribed to the interfacial layer, the interface states and the series resistance. At high current densities in the forward direction, the series resistance (R_s) effect has been observed. The values of R_s obtained from dV/d(lnI)-I and H(I)-I plots are near to each others (R_s = 182.24 Ω and R_s = 186.04 Ω, respectively). This case shows the consistency of the Cheung′s approach. In the same way, the barrier height calculated from C⁻² -V characteristics varied from 0.698 to 0.743 eV. Furthermore, the density distribution of interface states (N_ss) of the device has been obtained from the forward bias I-V characteristics. It has been seen that, the N_ss has almost an exponential rise with bias from the mid gap toward the bottom of conduction band.     

在SiO2中掺A1对Au／纳米（SiO2／Si／SiO2）／p—Si结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米（SiO2/Si/SiO2）/p-Si结构和纳米（SiO2:A1/Si/SiO2:A1)/p-Si结构,用磁控溅射制备纳米SiO2:A1时所用的SiO2/A1复合靶中的A1的面积百分比为1%。上述两种结构中Si层厚度均为1-3nm,间隔为0.2nm。为了对比研究,还制备了Si层厚度为零的样品。这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸A1作欧姆接触后,都在正向偏置下观察到电致发光（EL）。在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同。但掺A1结构的发光强度普遍比不掺A1结构强。另外,这两种结构的EL具体振荡特性有明显不同,对这两种结构的电致发光的物理机制和SiO2中掺A1的作用进行了分析和讨论。     

The source of negative capacitance and anomalous peak in the forward bias capacitance-voltage in Cr/p-si Schottky barrier diodes (SBDs)

The frequency and voltage dependence of capacitance–voltage (C–V) and conductance-voltage (G/ω−V) characteristics of the Cr/p-Si metal semiconductor (MS) Schottky barrier diodes (SBDs) were investigated in the frequency and applied bias voltage ranges of 10 kHz to 5 MHz and (−4 V)−(+4 V), respectively, at room temperature. The effects of series resistance (R_s) and density distribution of interface states (N_ss), both on C–V and G/ω−V characteristics were examined in detail. It was found that capacitance and conductance, both, are strong functions of frequency and applied bias voltage. In addition, both a strong negative capacitance (NC) and an anomalous peak behavior were observed in the forward bias C–V plots for each frequency. Contrary to the behavior of capacitance, conductance increased with the increasing applied bias voltage and there happened a rapid increase in conductance in the accumulation region for each frequency. The extra-large NC in SBD is a result of the existence of R_s, N_ss and interfacial layer (native or deposited). In addition, to explain the NC behavior in the forward bias region, we drew the C–I and G/ω−I plots for various frequencies at the same bias voltage. The values of C decrease with increasing frequency at forward bias voltages and this decrease in the NC corresponds to an increase in conductance. The values of N_ss were obtained using a Hill–Coleman method for each frequency and it exhibited a peak behavior at about 30 kHz. The voltage dependent profile of R_s was also obtained using a Nicollian and Brews methods.     

Effects of PCBM concentration on the electrical properties of the Au/P3HT:PCBM/n-Si (MPS) Schottky barrier diodes

In this study, the gold/poly(3-hexylthiophene):[6,6]-phenyl C61 butyric acid methyl ester/n-type silicon (Au/P3HT:PCBM/n-Si) metal–polymer–semiconductor (MPS) Schottky barrier diodes (SBDs) were investigated in terms of the effects of PCBM concentration on the electrical parameters. The forward and reverse bias current–voltage (I–V) characteristics of the Au/P3HT:PCBM/n-Si MPS SBDs fabricated by using the different P3HT:PCBM mass ratios were studied in the dark, at room temperature. The main electrical parameters, such as ideality factor (n), barrier height (Φ_B0), series resistance (R_s), shunt resistance (R_sh), and density of interface states (N_ss) were determined from I–V characteristics for the different P3HT:PCBM mass ratios (2:1, 6:1 and 10:1) used diodes. The values of n, R_s, Φ_B0, and N_ss were reduced, while the carrier mobility and current were increased, by increasing the PCBM concentration in the P3HT:PCBM organic blend layer. The ideal values of electrical parameters were obtained for 2:1 P3HT:PCBM mass ratio used diode. This shows that the electrical properties of MPS diodes strongly depend on the PCBM concentration of the P3HT:PCBM organic layer. Moreover, increasing the PCBM concentration in P3HT:PCBM organic blend layer improves the quality of the Au/P3HT:PCBM/n-Si (MPS) SBDs which enables the fabrication of high-quality electronic and optoelectronic devices.     

Analysis of interface states and series resistance of Ag/SiO2/n-Si MIS Schottky diode using current-voltage and impedance spectroscopy methods

The electrical characteristics and interface state density properties of Ag/SiO₂/n-Si metal-insulator-semiconductor diode have been analyzed by current-voltage and impedance spectroscopy techniques. The electronic parameters such as barrier height, ideality factor and average series resistance were determined and were found to be 0.62 eV, 1.91 and 975.8 Ω, respectively. The calculated ideality factor shows that Ag/SiO₂/n-Si structure obeys a metal-interfacial layer-semiconductor configuration rather than ideal Schottky barrier diode. The interface state density of the diode is of order of ∼10¹¹ eV⁻¹ cm⁻². The dielectrical relaxation mechanism of the diode is analyzed by Cole-Cole plots, indicating the presence of single relaxation mechanism. It is evaluated that the interfacial oxide layer modifies electrical parameters such as interface state density, series resistance and barrier height of Ag/SiO₂/n-Si diode.