Investigation of Ta2O5/SiO2/4H-SiC MIS capacitors

Tantalum pentoxide (Ta₂O₅) deposited by pulsed DC magnetron sputtering technique as the gate dielectric for 4H-SiC based metal-insulator-semiconductor (MIS) structure has been investigated. A rectifying current-voltage characteristic was observed, with the injection of current occurred when a positive DC bias was applied to the gate electrode with respect to the n type 4H-SiC substrate. This undesirable behavior is attributed to the relatively small band gap of Ta₂O₅ of around 4.3 eV, resulting in a small band offset between the 4H-SiC and Ta₂O₅. To overcome this problem, a thin thermal silicon oxide layer was introduced between Ta₂O₅ and 4H-SiC. This has substantially reduced the leakage current through the MIS structure. Further improvement was obtained by annealing the Ta₂O₅ at 900 °C in oxygen. The annealing has also reduced the effective charge in the dielectric film, as deduced from high frequency C-V measurements of the Ta₂O₅/SiO₂/4H-SiC capacitors.     

Defect-engineering in SiC by ion implantation and electron irradiation

Three examples are given, which show that ion implantation and electron irradiation can drastically modify the electrical properties of SiC and SiC-based MOS capacitors. (1) It is demonstrated that sulphur ions (S⁺) implanted into 6H-SiC act as double donors with ground states ranging from 310 to 635 meV below the conduction bandedge. (2) Co-implantation of nitrogen (N⁺) - and silicon (Si⁺) - ions into 4H-SiC leads to a strong deactivation of N donors. Additional experiments with electron (e⁻)-irradiated 4H-SiC samples (E(e⁻) = 200 keV) support the idea that this deactivation is due to the formation of an electrically neutral (N_x-V_C, y)-complex. (3) Implantation of a surface-near Gaussian profile into n-type 4H-SiC followed by a standard oxidation process leads to a strong reduction of the density of interface traps D_it close to the conduction bandedge in n-type 4H-SiC/SiO₂ MOS capacitors.     

Thermodynamic study, compositional and electrical characterization of LPCVD SiO2 films grown from TEOS/N2O mixtures

The theoretical phase diagram describing the growth of SiO₂ films from TEOS and N₂O mixtures within the temperature range 500–1100°C and pressure 0.3 Torr has been obtained, minimizing the total Gibbs energy of the chemical system involved in the deposition. It was found that at temperatures up to 900°C and N₂O/TEOS molar ratios up to approximately 7, the SiO₂ films deposited contained carbon impurities. For higher N₂O/TEOS molar ratios the obtained films are carbon free. SiO₂ films were grown from TEOS/N₂O mixtures in a conventional horizontal low pressure chemical vapor deposition reactor at temperatures of 710°C and 820°C and at a pressure of 0.3 Torr. These films were analyzed using X-ray photoelectron spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy and C–V measurements taken on metal–insulator–semiconductor structures formed with the deposited films as insulators. It was found that the films contain carbon impurities the concentration of which decreases with the increase of N₂O/TEOS molar ratio, in agreement with the results of the thermodynamic study. Carbon atoms were 90% bonded to other carbon atoms and only 10% to oxygen. It was found that the films are substoichiometric in oxygen with O/Si atomic ratios ranging between 1.95 and 1.80. The films were found to be positively charged, the charge increasing with N₂O flow and decreasing with deposition temperature.     

Stack engineering of TANOS charge-trap flash memory cell using high-κ ZrO2 grown by ALD as charge trapping layer

ZrO₂ with a κ value of 30 grown by atomic layer deposition has been integrated as charge trapping layer alternative to Si₃N₄ in TANOS-like memory capacitors, with Al₂O₃ as blocking oxide, SiO₂ as tunnel oxide and TaN metal gate. The fabricated device featuring 24 nm ZrO₂ exhibits efficient program and erase operations under Fowler-Nordheim tunneling when compared to a Si₃N₄ based reference device with similar EOT and fabricated under the same process conditions. The effect of stack thermal budget (900-1030 °C range) on memory performance and reliability is investigated and correlated with physical analyses. Finally, scaling ZrO₂ down to 14 nm allows program and erase at lower voltages, even if the trapping efficiency and retention of these device need further improvements for the integration of ZrO₂ in next generation charge trapping nonvolatile memories.     

High spatial and energy resolution characterization of lateral inhomogeneous Schottky barriers by conductive atomic force microscopy

We present a novel approach based on conductive atomic force microscope (c-AFM) for nano-scale mapping in laterally inhomogeneous metal-semiconductors Schottky contacts. For ultra-thin (1-5 nm) metal films with resistivity exceeding by about two orders of magnitude the bulk value, the current localization under the tip (10-20 nm diameter) occurs. By spectroscopic analysis of the current-voltage characteristics for different tip positions, the 2D Schottky barrier height (SBH) distribution is obtained with ∼0.1 eV energy resolution. The method was applied to explain the experimentally observed SBH lowering in macroscopic Au/4H-SiC diodes, in the presence of a not uniform SiO₂ layer at the SiC/Au interface. Nano-scale mapping on the oxide free Au/4H-SiC contact demonstrates a SBH distribution peaked at 1.8 eV and with tails from 1.6 eV to 2.1 eV. When ∼2 nm not uniform SiO₂ layer is intentionally grown on SiC before contact formation, the Au/SiO₂/4H-SiC SBH distribution exhibits a 0.3 eV lowering in the peak and a broadening (tails from 1.1 eV to 2.1 eV), thus explaining the macroscopically observed average effect.     

Effect of NO annealing conditions on electrical characteristics of n-type 4H-SiC MOS capacitors

This paper presents the results of the effect of NO annealing temperature and annealing time on the interfacial properties of n-type 4H-SiC MOS capacitors. The interface trap density measured by conductance technique at 330°C decreases as NO annealing temperature increases from 930°C to 1130° and annealing time is extended from 30 min. to 180 min. The changes in effective oxide charge between room temperature and high temperature are calculated and used to compare different n-type 4H-SiC MOS capacitors. Higher NO annealing temperature and longer NO annealing time decrease the change in effective oxide charge, which is consistent with the NO annealing temperature/time dependence of interface trap density measured by conductance technique. However, NO annealing temperature has more pronounced influence on the SiO₂/SiC interface than NO annealing time.     

Hf-O-N and HfO2 barrier layers for Hf-Ti-O gate dielectric thin films

Hf-O-N and HfO₂ thin films were evaluated as barrier layers for Hf-Ti-O metal oxide semiconductor capacitor structures. The films were processed by sequential pulsed laser deposition at 300 °C and ultra-violet ozone oxidation process at 500 °C. The as-deposited Hf-Ti-O films were polycrystalline in nature after oxidation at 500 °C and a fully crystallized (o)-HfTiO₄ phase was formed upon high temperature annealing at 900 °C. The Hf-Ti-O films deposited on Hf-O-N barrier layer exhibited a higher dielectric constant than the films deposited on the HfO₂ barrier layer. Leakage current densities lower than 5 × 10 A/cm² were achieved with both barrier layers at a sub 20 Å equivalent oxide thickness.     

Ultrathin insulating silica layers prepared from adsorbed TEOS, H2O and NH3 as a catalyst

Homogeneous ultrathin silica films were deposited without need of any expensive equipment and high-temperature processes (t?200 °C). Repeated adsorption of tetraethoxysilane (TEOS) multimolecular layers and their subsequent reaction with H₂O/NH₃ mixed vapours at atmospheric pressure and room temperature were used. By preparing the Al/SiO₂/N-Si MOS structure conditions were attained for electrical characterisation of the thin oxide layer by capacitance (C-V) and current (I-V) measurements. These measurements confirmed acceptable insulating properties of the oxide, the maximum breakdown field intensity being E_bd=5.4 MV/cm. The total defect charge of the MOS structure was positive, affected by a high trap density at the Si-SiO₂ interface.     

Optical characteristics of Si/SiO2 multilayers prepared by magnetron sputtering

Si/SiO₂ multilayers have been successfully prepared by magnetron sputtering and subsequently thermal annealed in an Ar atmosphere at a temperature of more than 500 °C. The surface of the as-deposited films is compact and smooth, and the distribution of grain size estimated to be 20 nm is uniform. For Si/SiO₂ multilayers annealed at 1100 °C, the Si sublayer sandwiched between potential barrier SiO₂ is crystalline structure by means of the analysis of Raman spectra and XRD data. The visible PL peak accompanying to a blue-shift with the decrease of Si sublayer thickness has been observed, and the intensity of this peak enhances with the increase of annealing temperature. The visible luminescence properties of Si/SiO₂ multilayers can be ascribed to quantum confinement of electron-hole pairs in quantum wells with grain size lower than 4.5 nm. In Si/SiO₂ multilayers, not only quantum confinement but also Si-SiO₂ interface states play an important role in the optical transition. The PL peak located at 779 nm is independent of the thickness of Si sublayer, so it may be ascribed to interface mediated transition. Typical Si dangling bonds defect could be a dominating obstacle to high luminescence efficiencies.     

Electrical characteristics and TDDB breakdown mechanism of N2-RTA-treated Hf-based high-κ gate dielectrics

This study investigates the effects of rapid thermal annealing (RTA) in nitrogen ambient on HfO₂ and HfSiO_x gate dielectrics, including their electrical characteristics, film properties, TDDB reliability and breakdown mechanism. The optimal temperature for N₂ RTA treatment is also investigated. The positive oxide trap charges (oxygen vacancies) in HfO₂ and HfSiO_x dielectric films can be reduced by the thermal annealing, but as the annealing temperature increased, many positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy level will be formed in the grain boundaries, degrading the electrical characteristics, and changing the breakdown mechanism. We believe that variation in the number of positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy levels is the main cause of the CV shift and difference in the breakdown behaviors between HfO₂ and HfSiO_x dielectrics. With respect to CV characteristics and TDDB reliability, the optimal temperature for N₂ RTA treatment is in the range 500-600 °C and 800-900 °C, respectively.     

Water-enhanced negative bias temperature instability in p-type low temperature polycrystalline silicon thin film transistors

Water-enhanced degradation of p-type low temperature polycrystalline silicon thin film transistors under negative bias temperature (NBT) condition is studied. H₂O penetration into gate oxide network and the role of H₂O during NBT stress are confirmed and clarified respectively. To prevent H₂O diffusion, a combination of a layer of PECVD SiO₂ and a layer of PECVD Si₃N₄ as passivation layers are investigated, revealing that 100 nm SiO₂ and 300 nm Si₃N₄ can effectively block H₂O diffusion and improve device NBT reliability.     

Co gamma irradiation effects on electrical characteristics of Al/Y2O3/n-Si/Al capacitors

Al/Y₂O₃/n-Si/Al capacitors were irradiated by using a ⁶⁰Co gamma ray source and a maximum dose up to 8.4 kGy. The effect of an annealing treatment performed at 600 or 900 °C on the yttrium oxide (Y₂O₃) films was investigated by XRD and Raman spectroscopy. High-frequency capacitance-voltage (C-V) and conductance-voltage (G-V) measurements as well as quasi-static measurements of the MOS structures were analysed. The annealing improves the crystalline state of the Y₂O₃ thin film material and decreases the values of the flat-band voltage and of the interface trap level density indicating an improvement of the electrical properties of the interface thin film-substrate. But at this interface, the formation of an yttrium-silicate layer was also evidenced. After gamma irradiation, the values of the flat-band voltage and of the interface trap level density related to the Al/Y₂O₃/n-Si/Al structure increase and especially for the structure made with the materials annealed at 900 °C for 1 h. In that case, the structure is very sensitive to a gamma irradiation dose up to 8.4 kGy.     

Effective formation of interface controlled Y2O3 thin film on Si(1 0 0) in a metal-(ferroelectric)-insulator-semiconductor structure

Yttrium was deposited on the chemical oxide of Si and annealed under vacuum to control the interface for the formation of Y₂O₃ as an insulating barrier to construct a metal-ferroelectric-insulator-semiconductor structure. Two different pre-annealing temperatures of 600 and 700 °C were chosen to investigate the effect of the interface state formed after the pre-annealing step on the successive formation of Y₂O₃ insulator and Nd₂Ti₂O₇ (NTO) ferroelectric layer through annealing under an oxygen atmosphere at 800 °C. Pre-anneal treatments of Y-metal/chemical-SiO₂/Si at 600 and 700 °C induced a formation of Y₂O₃ and Y-silicate, respectively. The difference in the pre-anneal temperature induced almost no change in the electrical properties of the Y₂O₃/interface/Si system, but degraded properties were observed in the NTO/Y₂O₃/interface/Si system pre-annealed at 600 °C when compared with the sample pre-annealed at 700 °C. C-V characteristics of the NTO/Y₂O₃/Si structured system showed a clockwise direction of hysteresis, and this gap could be used as a memory window for a ferroelectric-gate. A smaller hysteric gap and electrical breakdown values were observed in the NTO/Y₂O₃/Si system pre-annealed at 600 °C, and this was due to an unintentional distribution of the applied field from the presence of an interfacial layer containing Y-silicate and SiO₂ phases.     

Effect of Ar annealing temperature on SiO2/4H-SiC interface studied by spectroscopic ellipsometry and atomic force microscopy

The authors have investigated the effects of different annealing temperatures in Ar atmosphere on the SiO₂/4H-SiC interfaces by spectroscopic ellipsometry (SE) and atomic force microscopy (AFM). There is a strong correlation between the annealing temperatures and the quality of SiO₂/4H-SiC interface. Annealing at 600 °C can significantly improve the quality of SiO₂/4H-SiC interface with no transition layer. The reasons for such improvement in the quality of the SiO₂/4H-SiC interface after moderate temperature annealing at 600 °C may be explained by the formation and consumption of carbon clusters and silicon oxycarbides during annealing.     

Hydrogen passivation effects under negative bias temperature instability stress in metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon capacitors for flash memories

The paper presents the passivation effect of post-annealing gases on the negative bias temperature instability of metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon (MONOS) capacitors. MONOS samples annealed at 850 °C for 30 s by a rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing gases N₂ and N₂-H₂ (2% hydrogen and 98% nitrogen gas mixture) at 450 °C for 30 min. MONOS samples annealed in an N₂-H₂ environment are found to have lowest oxide trap charge density shift, ΔN_ot = 8.56 × 10¹¹ cm⁻², and the lowest interface-trap density increase, ΔN_it = 4.49 × 10¹¹ cm⁻² among the three samples as-deposited, annealed in N₂ and N₂-H₂ environments. It has also been confirmed that the same MONOS samples have the lowest interface-trap density, D_it = 0.834 × 10¹¹ eV⁻¹ cm⁻², using small pulse deep level transient spectroscopy. These results indicate that the density of interface traps between the silicon substrate and the tunneling oxide layer are significantly reduced by the additional furnace annealing in the N₂-H₂ environment after the RTA.     

Yttrium silicide formation and its contact properties on Si(1 0 0)

Yttrium silicide formation and its contact properties on Si(1 0 0) have been studied in this paper. By evaporating a yttrium metal layer onto Si(1 0 0) wafer in conventional vacuum condition and rapid thermal annealing, we found that YSi_2-x begins to form at 350 °C, and is stable to 950 °C. Atomic force microscopy characterization shows the pinholes formation in the formed YSi_2-x film. By current-voltage measurement, the Schottky barrier height (SBH) of YSi_2-x diode on p-type Si(1 0 0) was shown to be between 0.63 and 0.69 eV for annealing temperature from 500 to 900 °C. By low temperature current-voltage measurement, the SBH of YSi_2-x diode on n-type Si(1 0 0) was directly measured and shown to be 0.46, 0.37, 0.32 eV for annealing temperature of 500, 600, and 900 °C, respectively, and possibly even lower for annealing at 700 or 800 °C.     

Anomalous thermal oxidation of gadolinium thin films deposited on silicon by high pressure sputtering

Thin gadolinium metallic layers were deposited by high-pressure sputtering in pure Ar atmosphere. Subsequently, in situ thermal oxidation was performed at temperatures ranging from 150 to 750 °C. At an oxidation temperature of 500 °C the films show a transition from monoclinic structure to a mixture of monoclinic and cubic. Regrowth of interfacial SiO_x is observed as temperature is increased, up to 1.6 nm for 750 °C. This temperature yields the lowest interface trap density, 4 × 10¹⁰ eV⁻¹ cm⁻², but the effective permittivity of the resulting dielectric is only 7.4. The reason of this low value is found on the oxidation mechanism, which yields a surface with located bumps. These bumps increase the average thickness, thus reducing the capacitance and therefore the calculated permittivity.     

Characterization of polycrystalline 3C-SiC thin film diodes for extreme environment applications

This paper describes the fabrication and characteristics of polycrystalline (poly) 3C-SiC thin film diodes for extreme environment applications, in which the poly 3C-SiC thin film was deposited onto oxidized Si wafers by APCVD using HMDS as a precursor. In this work, the optimized growth temperature and HMDS flow rate were 1100 °C and 8 sccm, respectively. A Schottky diode with a Au, Al/poly 3C-SiC/SiO₂/Si(n-type) structure was fabricated and its threshold voltage (V_d), breakdown voltage, thickness of depletion layer, and doping concentration (N_D) values were measured as 0.84 V, over 140 V, 61 nm, and 2.7 × 10¹⁹ cm³, respectively. To produce good ohmic contact, Al/3C-SiC were annealed at 300, 400, and 500 °C for 30 min under a vacuum of 5.0 × 10⁻⁶ Torr. The obtained p-n junction diode fabricated by poly 3C-SiC had similar characteristics to a single 3C-SiC p-n junction diode.     

Effect of high temperature annealing on tunnel oxide properties in TANOS devices

We investigate the effect of high temperature Post-Deposition Annealing of Al₂O₃ on the tunnel oxide of TANOS-like non-volatile memories. We found that, when temperature steps above 850 °C are applied after the stack deposition, a transition layer is forming by the intermixing of the Si₃N₄ with the upper part of the underneath SiO₂. We found that this transition layer has worse dielectric properties as compared to SiO₂, altering in a not-negligible way the performance of TANOS memories, and in particular severely penalizing retention.     

Improving electrical characteristics of W/HfO2/In0.53Ga0.47As gate stacks by altering deposition techniques

The effects of controlling InGaAs substrate temperature during electron beam deposition of HfO₂ on electrical characteristics of W/HfO₂/n-In_0.53Ga_0.47As capacitors are investigated. It is found that by depositing a thin HfO₂ layer at the interface when substrate temperature is raised to 300 °C, frequency dispersion at depletion and accumulation conditions is reduced and interface state density is lowered regardless of the HfO₂ thickness. Cross-sectional transmission electron microscopy images have revealed that the formation of mesoscopic voids in the InGaAs substrate near the interface is suppressed with HfO₂deposition at 300 °C at the interface. A band diagram with an additional bulk trap energy level has been proposed to explain the frequency dispersion and conductance peaks at accumulation condition.