Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output characteristics and increase in the breakdown voltage when compared with a conventional DG structure. For the first time, we show that the presence of single halo on the source side results in a step function in the surface potential, which screens the source side of the structure from the drain voltage variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices over conventional DG MOSFET and provides an incentive for further experimental exploration.     

Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension

A novel cylindrical surrounding gate MOSFETs with electrically induced source/drain extension is proposed and demonstrated by numerical simulation for the first time. In the new device, a constant voltage is applied to the side-gate to form inversion layers acting as the extremely shallow virtual source/drain. Using three-dimensional device simulator, we have investigated the device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing, electrical field and carrier temperature. Based on our simulation results, we demonstrate that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.     

Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement.     

全耗尽异质栅单Halo SOI MOSFET二维模型

为了抑制深亚微米SOI MOSFET的短沟道效应,并提高电流驱动能力,提出了异质栅单Halo SOI MOSFET器件结构,其栅极由具有不同功函数的两种材料拼接而成,并在沟道源端一侧引入Halo技术.采用分区的抛物线电势近似法和通用边界条件求解二维Poisson方程,为新结构器件建立了全耗尽条件下的表面势及阈值电压二维解析模型.对新结构器件与常规SOI MOSFET性能进行了对比研究.结果表明,新结构器件能有效抑制阈值电压漂移、热载流子效应和漏致势垒降低效应,并显著提高载流子通过沟道的输运速度.解析模型与器件数值模拟软件MEDICI所得结果高度吻合.     

A new asymmetrical halo source GOLD drain (HS-GOLD) deepsub-half-micrometer n-MOSFET design for reliability and performance

An asymmetrical n-MOSFET device structure was developed that is suitable, in terms of reliability and performance, for scaling down to the sub-quarter-micrometer level without reduction of the supply voltage below 3.5 V. In this structure, large-tilt implantation is used to form the gate-overlapped LDD (GOLD) region at the drain electrode only. A halo (punchthrough stopper) is used at the source, but not at the drain. Superior hot carrier reliability and high punchthrough resistance are obtained using this device structure. A reliability-limited supply voltage of 4.2 V is obtained for an asymmetrical n-MOSFET with effective channel lengths as short as 0.25 μm. By extrapolation from the measured threshold roll-off characteristics, the authors expect that this structure can be designed with substantially shorter channel length while maintaining the 3.5-V supply voltage     

Analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions

Physics-based analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions is presented. The effect of inversion carriers on the channel’s potential is considered in presented model. Using this analytical model, the characteristics of EJ-CSG are investigated in terms of surface potential and electric field distribution, threshold voltage roll-off, and DIBL. Results show that the application of electrically induced S/D extensions to the cylindrical surrounding-gate MOSFET will successfully suppress the hot-carrier effects, threshold voltage roll-off, and DIBL. It is also revealed that a moderate side-gate bias voltage, a small gate oxide thickness, and a small silicon channel radius are needed to improve device characteristics. The derived analytical model is verified by its good agreement with the three-dimensional numerical device simulator ISE.     

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.     

22nm技术节点异质栅MOSFET的特性研究

研究了22 nm栅长的异质栅MOSFET的特性,利用工艺与器件仿真软件Silvaco,模拟了异质栅MOSFET的阈值电压、亚阈值特性、沟道表面电场及表面势等特性,并与传统的同质栅MOSFET进行比较。分析结果表明,由于异质栅MOSFET的栅极由两种不同功函数的材料组成,因而在两种材料界面附近的表面沟道中增加了一个电场峰值,相应地漏端电场比同质栅MOSFET有所降低,所以在提高沟道载流子输运效率的同时也降低了小尺寸器件的热载流子效应。此外,由于该器件靠近源极的区域对于漏压的变化具有屏蔽作用,从而有效抑制了小尺寸器件的沟道长度调制效应,但是由于其亚阈值特性与同质栅MOSFET相比较差,导致漏致势垒降低效应(DIBL)没有明显改善。     

一种非对称双栅应变硅HALO掺杂沟道MOSFET阈值电压解析模型

提出了一种非对称双栅应变硅HALO掺杂沟道金属氧化物半导体场效应管结构.该器件前栅和背栅由两种不同功函数的金属构成,沟道为应变硅HALO掺杂沟道,靠近源区为低掺杂区域,靠近漏区为高掺杂区域.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,分别求解了前背栅表面势、前背栅表面电场及前背栅阈值电压,建立了双栅器件的表面势、表面电场和阈值电压解析模型.详细讨论了物理参数对解析模型的影响.研究结果表明,该器件能够很好的抑制短沟道效应、热载流子效应和漏致势垒降低效应.模型解析结果与DESSIS仿真结果吻合较好,证明了该模型的正确性.     

Voltage difference engineering in SOI MOSFETs: A novel side gate device with improved electrical performance

We studied the impact of voltage difference engineering in a silicon-on-insulator metal oxide semiconductor field-effect transistor (SOI-MOSFET) and compared the performance to that of a conventional SOI-MOSFET (C-SOI). Our structure, called a SIG-SOI MOSFET, includes main and side gates with an optimum voltage difference between them. The voltage difference leads to an inverted channel as an electrical drain extension under the side gate. This channel creates a stepped potential distribution along the channel that it cannot be seen in the C-SOI MOSFETs. The voltage difference controls the channel properly and two-dimensional two-carrier device simulations revealed lower threshold voltage variations, larger breakdown voltage, higher voltage gain, lower hot carrier effects, improved drain-induced barrier lowering, lower drain conductance, higher unilateral power gain, and lower leakage current compared to a C-SOI device. Thus, our proposed structure has higher performance than a typical C-SOI structure.     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

Modelling of parameters for asymmetric halo and symmetric DHDMG n-MOSFETs

This article presents an analytical surface potential, threshold voltage and drain current model for asymmetric pocket-implanted, single-halo dual material gate and double-halo dual material gate (DHDMG) n-MOSFET (MOSFET, metal–oxide–semiconductor field-effect transistor) operating up to 40?nm regime. The model is derived by applying Gauss's law to a rectangular box, covering the entire depletion region. The asymmetric pocket-implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends along with the inner fringing capacitances at both the source and the drain ends and the subthreshold drain and the substrate bias effect. Using the surface potential model, the threshold voltage and drain currents are estimated. The same model is used to find the characteristic parameters for dual-material gate (DMG) with halo implantations and double gate. The characteristic improvement is investigated. It is concluded that the DHDMG device structure exhibits better suppression of the short-channel effect (SCE) and the threshold voltage roll-off than DMG and double-gate MOSFET. The adequacy of the model is verified by comparing with two-dimensional device simulator DESSIS. A very good agreement of our model with DESSIS is obtained proving the validity of our model used in suppressing the SCEs.     

Degradation in thin-film SOI MOSFET's caused by single-transistorlatch

The measurement of anomalous hot-carrier damage in thin-film n-channel SOI MOSFETs is reported. Due to the presence of a parasitic bipolar transistor between the source and drain, the minimum drain voltage for breakdown in these devices occurs when the device is biased in subthreshold. Using charge-pumping measurements, it is shown that if the device is biased in this regime, where single-transistor latch occurs, hot holes are injected into the gate oxide near the drain. Consequently, the maximum allowable drain voltage for these devices is governed by the parasitic bipolar properties of the SOI MOSFET     

FinFET design considerations based on 3-D simulation and analytical modeling

Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison.     

Full quantum simulation study of a nano tri-material double gate silicon-on-insulator MOSFET

We present 2D full quantum simulation based on the self-consistent solution of 2D Poisson–Schrödinger equations, within the nonequilibrium Green’s function formalism, for a novel multiple region silicon-on-insulator (SOI) MOSFET device architecture – tri-material double gate (TMDG) SOI MOSFET. This new structure has three materials with different work functions in the front gate, which show reduced short-channel effects such as the drain-induced barrier lowering and subthreshold swing, because of a step function of the potential in the channel region that ensures the screening of the drain potential variation by the gate near the drain. Also, the quantum simulations show the new structure significantly decreases leakage current and drain conductance and increases on–off current ratio and voltage gain as compared to conventional and dual material DG SOI MOSFET.     

双掺杂多晶Si栅MOSFET的截止频率研究

在前期对双掺杂多晶Si栅(DDPG)LDMOSFET的电场、阈值电压、电容等特性所作分析的基础上,仍然采用双掺杂多晶Si栅结构,以低掺杂漏/源MOS(LDDMOS)为基础,重点研究了DDPG-LDDMOSFET的截止频率特性.通过MEDICI软件,模拟了栅长、栅氧化层厚度、源漏区结深、衬底掺杂浓度以及温度等关键参数对器件截止频率的影响,并与相同条件下P型单掺杂多晶Si栅(p-SDPG)MOSFET的频率特性进行了比较.仿真结果发现,在栅长90 nm、栅氧厚度2 nm,栅极P,n掺杂浓度均为5×1019cm-3条件下,截止频率由78.74 GHz提高到106.92 GHz,幅度高达35.8%.此结构很好地改善了MOSFET的频率性能,得出的结论对于结构的设计制作和性能优化具有一定的指导作用,在射频领域有很好的应用前景.     

The effects of process induced gate-to-source/drain junction separation in MOSFET structures

As device size decreases, the effect of process fluctuations on the device structure and performance will become more apparent. Implantation, annealing and etching fluctuations can lead to a separation between the edge of the gate and the source/drain extensions. This paper investigates the effect of separation on the device characteristics of 1.5 μm mask gate length MOSFETs. It was found that introducing separation reduced the overall peak substrate current, increased the breakdown voltage, increased the hot carrier hardness and greatly increased the device’s lifetime. However, separation also increased the threshold voltage and reduced the drain current. The separation was found not to contribute any extra parasitic resistance but manifested itself as an increase in the effective electrical channel length. Varying the amount of separation demonstrated that the input capacitance was reduced, and that the speed was increased relative to a standard LDD MOSFET.     

An SOI voltage-controlled bipolar-MOS device

This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI MOSFET allows lateral bipolar current to be added to the MOS channel current and thereby enhances the current drive capability of the device. Part of the bipolar current emitted by the source terminal merges into the channel before reaching the drain, which renders the base width substantially shorter than the gate length. This novel operating mode of a short-channel SOI transistor is particularly attractive for high-speed operation, since the device is capable of both reduced voltage swing operation and high current drive, n-p-n and p-n-p devices, as well as complementary inverters have been successfully fabricated.     

异质栅非对称Halo SOI MOSFET

为了抑制异质栅SOI MOSFET的漏致势垒降低效应,在沟道源端一侧引入了高掺杂Halo结构.通过求解二维电势Poisson方程,为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型,并对其性能改进情况进行了研究.结果表明,新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应,并进一步提高载流子输运效率.新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱,但随Halo区长度非单调变化.解析模型与数值模拟软件MEDICI所得结果高度吻合.     

异质栅非对称Halo SOI MOSFET

为了抑制异质栅SOI MOSFET的漏致势垒降低效应，在沟道源端一侧引入了高掺杂Halo结构．通过求解二维电势Poisson方程，为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型，并对其性能改进情况进行了研究．结果表明，新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应，并进一步提高载流子输运效率．新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱，但随Halo区长度非单调变化．解析模型与数值模拟软件MEDICI所得结果高度吻合．