Electrical method of measuring physical thickness and nitrogen concentration of silicon oxynitride gate dielectric for MOSFETs

This paper proposes an electrical method of measuring the physical thickness T_ox and the nitrogen concentration α_N of the silicon oxynitride (SiON) gate dielectric for MOSFETs. The proposed method uses the facts that the gate dielectric breakdown field strength E_BD depends on α_N for a given T_ox and the direct tunneling (DT) current depends strongly on T_ox. Gate current I_g versus gate voltage V_g (I_g-V_g) curves at a given α_N were calculated for different T_oxs using the DT model, and measurements were compared to the curves to obtain T_ox. The α_N was obtained by comparing the measured E_BD at a given T_ox with the theoretical E_BD for a SiON gate dielectric. These two steps were iterated until the convergence error of α_N was less than 1%. The I_g-V_g curves calculated using the extracted T_oxs and α_Ns agreed very well with measurements when V_g was less than the gate breakdown voltage. The difference between the equivalent oxide thickness (EOT) measured using the C-V method and the EOT calculated using the extracted T_ox and α_N was less than 7%, demonstrating that the proposed method can accurately determine T_ox and α_N of an ultra-thin SiON gate dielectric from only the measured I_g-V_g curve of the MOSFET.     

Operation model of floating-Si-gate channel-corner-avalanche-transition (FCAT) nonvolatile memory devices

A write/erase model is described for FCAT nonvolatile memory devices which perform write/erase operations with 10–20 V pulses of less than 100-1 μs duration. The amplitude of the threshold voltage shift is analyzed as a function of the source and gate pulse amplitudes using a sample equivalent source circuit. The high level saturated threshold voltage, V_TH, obtained by electron injection into the floating gate and the low level saturated threshold voltage, V_TL, due to hole injection are shown to be linear functions of V_G and V_S, and the analysis agrees well with experimental results. The influence of series resistance, including substrate resistance, in the source circuit is also discussed.     

Investigation of power Trench MOSFETs with retrograde body profile

We present here a power Trench MOSFET (T-MOS) with retrograde body doping profile. The channel length and trench depth are both shortened compared with conventional T-MOS. High energy implantation is used to form retrograde body profile. Electronic parameters of the new structure have been obtained by process and device simulation. The results show that the new structure has much lower specific on-resistance (R_ds,on) because of its shorter channel when compared with conventional T-MOS. As the trench depth is shallowed, the gate charge density Q_g is also reduced.     

Improved retention characteristic of charge-trapped flash device with sealing layer/Al2O3 or Al2O3/high-k stacked blocking layers

Although programming and erase speeds of charge trapping (CT) flash memory device are improved by using Al₂O₃ as blocking layer, its retention characteristic is still a main issue. CT flash memory device with Al₂O₃/high-k stacked blocking layer is proposed in this work to enhance data retention. Moreover, programming and erase speeds are slightly improved. In addition, sealing layer (SL), which is formed by an advanced clustered horizontal furnace between charge trapping layer and Al₂O₃ as one of the blocking layers is also studied. The retention characteristic is enhanced by SL approach due to lower gate leakage current with less defect. With the combination of SL and Al₂O₃/high-k stacked blocking layer approaches, retention property can be further improved.     

Atmos—An electrically reprogrammable read-only memory device

An adjustable threshold MOS (Atmos) transistor is described that can be used as an electrically reprogrammable read-only memory by changing the charge content of a floating polysilicon gate. This floating gate is charged negatively (write) by means of a nonavalanche mechanism and charged positively (erase) by the avalanche breakdown of source or drain junction and subsequent hole injection into the oxide. The write time is between 10 and 100 ms, the erase time on the order of 1 s. The charge retention of the floating gate is about 90 percent after storage for 1000 h at 125°C.     

Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance

The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.     

Performance improvement of flash memory using AlN as charge-trapping Layer

Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si₃N₄) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high-k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO₂ as a blocking oxide in p-Si/SiO₂/AlN/SiO₂/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.     

dc-Conduction mechanism in lanthanum–manganese oxide films grown on p-Si substrate

Thin films of (La–Mn) double oxide were prepared on p-Si substrates for electrical investigations. The samples have been characterised by X-ray fluorescence (XRF) and X-ray diffraction (XRD) methods. The XRF spectrum was used to determine the weight fraction ratio of Mn to La in the prepared samples. The XRD study shows the formation of grains of LaMnO₃ compound through a solid-state reaction for annealing at 800 °C. Samples used to study the electrical characteristics of the prepared films were constructed in form of a metal–oxide–Si MOS structures. Those MOS structures were characterised by the measuring their capacitance as a function of gate voltage C(V_g) in order to determine the oxide charge density Q_ox, the surface density of states D_it at the oxide/Si interface, and to extract the oxide voltage in terms of gate voltage. The extracted dielectric constant of the double oxide film is lower than that of pure La₂O₃ film and larger than that of pure Mn₂O₃ film, but the formation of LaMnO₃ grains by a solid-state reaction at 800 °C increases the relative permittivity to 11.5. These experimental conclusions might be useful to be used in the field of Si-oxide alternative technique. The leakage dc current density vs. oxide field J(E_ox) relationship for crystalline films follow the mechanism of Richardson–Schottky (RS), from which the field-lowering coefficient and the dynamic relative permittivity were determined. Nevertheless, the leakage current density measured in a temperature range of (293–363 K) was not controlled by the RS mechanism. It was observed that the temperature dependence of the leakage current in crystalline (La–Mn) oxide insulating films has metallic-like temperature behaviour, which might be important in the technical applications.     

Structural advantages of rectangular-like channel cross-section on electrical characteristics of silicon nanowire field-effect transistors

We have experimentally demonstrated structural advantages due to rounded corners of rectangular-like cross-section of silicon nanowire (SiNW) field-effect transistors (FETs) on on-current (I_ON), inversion charge density normalized by a peripheral length of channel cross-section (Q_inv) and effective carrier mobility (μ_eff). The I_ON was evaluated at the overdrive voltage (V_OV) of 1.0 V, which is the difference between gate voltage (V_g) and the threshold voltage (V_th), and at the drain voltage of 1.0 V. The SiNW nFETs have revealed high I_ON of 1600 μA/μm of the channel width (w_NW) of 19 nm and height (h_NW) of 12 nm with the gate length (L_g) of 65 nm. We have separated the amount of on-current per wire at V_OV = 1.0 V to a corner component and a flat surface component, and the contribution of the corners was nearly 60% of the total I_ON of the SiNW nFET with L_g of 65 nm. Higher Q_inv at V_OV = 1.0 V evaluated by advanced split-CV method was obtained with narrower SiNW FET, and it has been revealed the amount of inversion charge near corners occupied 50% of all the amount of inversion charge of the SiNW FET (w_NW = 19 nm and h_NW = 12 nm). We also obtained high μ_eff of the SiNW FETs compared with that of SOI planar nFETs. The μ_eff at the corners of SiNW FET has been calculated with the separated amount of inversion charge and drain conductance. Higher μ_eff around corners is obtained than the original μ_eff of the SiNW nFETs. The higher μ_eff and the large fractions of I_ON and Q_inv around the corners indicate that the rounded corners of rectangular-like cross-sections play important roles on the enhancement of the electrical performance of the SiNW nFETs.     

Silicon-gate CMOS devices with 300 Å gate oxides

Polycrystalline silicon gate (phosphorus doped) complementary MOS structures were fabricated with gate oxide thicknesses down to 300 Å. Measurements of the oxide fixed charge, Q_ss, and of the back-gate bias dependence of the threshold voltage indicate an absence of phosphorus diffusion through the gate oxide during conventional processing.     

A new small-signal MOSFET model and parameter extraction method for RF IC's application

In this paper, an accurate and simple small signal model of RF MOSFETs accounting for the distributed gate effect, the substrate parasitics and charge conservation is proposed. Meanwhile, a direct and accurate extraction method using linear regression approach for the components of the equivalent circuit of the MOSFET with S-parameters analysis is also proposed. The proposed model and extraction method are verified with the experimental data and an excellent agreement is obtained up to 10 GHz. The extraction results from the measured data for various bias conditions are presented. Also, the extracted parameters, such as transconductance g_m, match well with those obtained from DC measurements. Besides, it is shown that a significant error in circuit performances would be found if the charge conservation is not properly considered.     

Nonvolatile Floating‐Gate Memories Based on Stacked Black Phosphorus–Boron Nitride–MoS2 Heterostructures

Research on van der Waals heterostructures based on stacked 2D atomic crystals is intense due to their prominent properties and potential applications for flexible transparent electronics and optoelectronics. Here, nonvolatile memory devices based on floating‐gate field‐effect transistors that are stacked with 2D materials are reported, where few‐layer black phosphorus acts as channel layer, hexagonal boron nitride as tunnel barrier layer, and MoS₂ as charge trapping layer. Because of the ambipolar behavior of black phosphorus, electrons and holes can be stored in the MoS₂ charge trapping layer. The heterostructures exhibit remarkable erase/program ratio and endurance performance, and can be developed for high‐performance type‐switching memories and reconfigurable inverter logic circuits, indicating that it is promising for application in memory devices completely based on 2D atomic crystals.     

Low frequency noise in thin gate oxide MOSFETs

Low frequency, 1/f, noise of the drain current, I_D, fluctuations was measured on a series of Si MOSFETs with the gate oxide thickness, t_ox, varied from 25 to 40 Å by steps of 5 Å. The salient point of this work is a demonstration that, at sufficiently low I_D intensities, a mean low noise level in the MOSFETs is reduced as the gate oxide becomes thinner. This is explained assuming that the noise originates from the electron capture/release on Si/SiO₂ interface/border traps. The flat band voltage fluctuations, observable as noise, are linked then to the oxide charge fluctuations by a factor, that is inversely proportional to the gate capacitance, C_ox, and thus proportional to t_ox. At higher I_D, the results are more complicated, as the access resistance noise is also involved. We provide an interpretation of the ensemble of the data and show that the noise analysis can furnish quantitative estimates of several device characteristics. Device degradation and its consequences for the low frequency noise at higher current levels are also discussed.     

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

This paper describes the use of II–VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO _x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn_0.95Mg_0.05S-ZnS tunneling layers. The II–VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.     

Precise determination of metal effective work function and fixed oxide charge in MOS capacitors with high-κ dielectric

Effective metal work function, Φ_m,eff, and oxide charge, Q_ox, were determined on MOS capacitors with slanted high-κ dielectric. Φ_m,eff and Q_ox were extracted using flat-band voltage shift versus equivalent oxide thickness data, both deduced from the capacitance–voltage measurements. Slanted HfSiO_x dielectric (initial thickness was 9 nm) was prepared by gradual etching in HF-based solution. As a metal electrode, thin Ru-films were deposited by MOCVD-derived technique—Atomic Vapor Deposition^® on the slanted HfSiO_x as well as SiO₂ dielectrics. The Φ_m,eff of Ru was found to be 4.74 and 4.81 eV for Ru/HfSiO_x and Ru/SiO₂ gate stacks, respectively. Ultraviolet photoelectron spectroscopy yields the work function of 4.62 eV in agreement with the capacitance–voltage data. We also studied the I–V characteristics of the Ru/HfSiO_x/Si MOS capacitors. The barrier height was found to be constant within the HfSiO_x bulk.     

Famos—A new semiconductor charge storage device

A new non-volatile charge storage device is described. The floating gate avalanche injection MOS (FAMOS) structure is a p-channel silicon gate field effect transistor in which no electric contact is made to the silicon gate. It combines the floating gate concept with avalanche injection of electrons from the surface depletion region of a p-n junction to yield reproducible charging characteristics with long term storage retention.     

Oxide interfacial charge engineering towards normally-off AlN/GaN MOSHEMT

In this paper a detail insight into the role of oxide/barrier interfacial charges (N_ox) for shifting the threshold voltage (V_T) of AlN/GaN metal oxide semiconductor high electron mobility transistors (MOSHEMTs) is gained. A model is developed for V_T considering all possible charges arise at different interfaces. To validate the model the proposed device is simulated by considering different insulators and N_ox into account. It is very fascinating to observe that V_T is highly sensitive towards change in N_ox at higher oxide dimensions, whereas at lower dimensions N_ox has very negligible effect. Normally-off operation can be achieved by increasing or decreasing N_ox in MOSHEMT with Al₂O₃ or HfO₂ as gate dielectric respectively.     

Analog/RF Study of Self-aligned In<Subscript>0.53</Subscript>Ga<Subscript>0.47</Subscript>As MOSFET with Scaled Gate Length

This study presents the impact of gate length scaling on analog and radio frequency (RF) performance of a self- aligned multi-gate n-type In_0.53Ga_0.47As metal oxide semiconductor field effect transistor. The device is fabricated using a self-aligned method, air-bridge technology, and 8 nm thickness of the Al₂O₃ oxide layer with different gate lengths. The transconductance-to-normalized drain current ratio (g _m/I _D) method is implemented to investigate analog parameters. Moreover, g _m and drain conductance (g _D) as key parameters in analog performance of the device are evaluated with g _m/I _D and gate length variation, where g _m and g _D are both showing enhancement due to scaling of the gate length. Early voltage (V _EA) and intrinsic voltage gain (A _V) value presents a decreasing trend by shrinking the gate length. In addition, the results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.     

P-Type Floating Gate for Retention and P/E Window Improvement of Flash Memory Devices

A flash memory with a lightly doped p-type floating gate is proposed, which improves charge retention and programming/erase (P/E) V_th window. Improvement in P/E window is enhanced for cells with smaller capacitance coupling ratio, which is important for future scaled flash memory cells. Both device simulation and experimental verification are presented.