Effect of rapid thermal annealing on deep level defects in the Si-doped GaN

Rapid thermal annealing effects on deep level defects in the n-type GaN layer grown by metalorganic chemical vapor deposition (MOCVD) have been characterized using deep level transient spectroscopy (DLTS) technique. The samples were first characterized by current-voltage (I-V) and capacitance-voltage (C-V) measurements. The measurements showed that the barrier height of the as-grown sample to be 0.74 eV (I-V) and 0.95 eV (C-V) respectively. However, the Schottky barrier height of the sample annealed at 800 °C increased to 0.84 eV (I-V) and 0.99 eV (C-V) respectively in nitrogen atmosphere for 1 min. Further, it was observed that the Schottky barrier height slightly decreased after annealing at 900 °C. DLTS results showed that the two deep levels are identified in as-grown sample (E1 and E3), which have activation energies of 0.19 ± 0.01 eV and 0.80 ± 0.01 eV with capture cross-sections 2.06 × 10⁻¹⁷ cm² and 7.68 × 10⁻¹⁸ cm², which can be related to point defects. After annealing at 700 °C, the appearance of one new peak (E2) at activation energy of 0.49 ± 0.02 eV with capture-cross section σ_n = 5.43 × 10⁻¹⁷ cm², suggest that E2 level is most probably associated with the nitrogen antisites. Thermal annealing at 800 °C caused the E1 and E3 levels to be annealed out, which suggest that they are most probably associated with the point defects. After annealing at 900 °C the same (E1 and E3) deep levels are identified, which were identified in as-grown n-GaN layer.     

On the energy distribution of interface states and their relaxation time and capture cross section profiles in Al/SiO2/p-Si (MIS) Schottky diodes

The energy distribution profile of the interface states (N_ss) and their relaxation time (τ) and capture cross section (σ_p) of metal-insulator-semiconductor (Al/SiO₂/p-Si) Schottky diodes have been investigated by using the high-low frequency capacitance and conductance methods. The capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of these devices were investigated by considering series resistance (R_s) effects in a wide frequency range (5 kHz-1 MHz.). It is shown that the capacitance of the Al/SiO₂/p-Si Schottky diode decreases with increasing frequency. The increase in capacitance especially at low frequencies results form the presence of interface states at Si/SiO₂ interface. The energy distributions of the interface states and their relaxation time have been determined in the energy range of (0.362-E_v)-(0.512-E_v) eV by taking into account the surface potential as a function of applied bias obtained from the measurable C-V curve (500 Hz) at the lowest frequency. The values of the interface state density (N_ss) ranges from 2.34 × 10¹² to 2.91 ×  10¹² eV⁻¹/cm², and the relaxation time (τ) ranges from 1.05 × 10⁻⁶ to 1.58 × 10⁻⁴ s, showing an exponential rise with bias from the top of the valance band towards the mid-gap.     

Effect of axial halogen substitution on the performance of subphthalocyanine based organic photovoltaic cells

To probe the influence of molecular dipole on the open circuit voltage (V_OC) of molecular heterojunction organic solar cells, we study axially fluorinated boron subphthalocyanine/fullerene (SubPc-F/C₆₀) junctions. These exhibit an open-circuit voltage V_OC = 1.00 V, a value closer to the HOMO–LUMO offset at the donor–acceptor interface = 1.69 eV than the V_OC = 1.06 V measured for junctions between the archetypal chlorinated SubPc and C₆₀, with corresponding HOMO–LUMO offset = 1.84 eV. Aside from the axial halogen substitution, the two compounds exhibit similar molecular structure and optical absorption. The energy levels and structure of the heteromolecular polaron pair are calculated, and the ideal organic diode model for SubPc-Cl is modified accordingly, successfully reproducing the experimental SubPc-F device characteristics. The reproducible difference in V_OC is attributed to the different electric dipole strength between SubPc-F and SubPc-Cl and its influence on polaron pair dynamics at the heterojunction.     

Annealing temperature effect on electrical and structural properties of Cu/Au Schottky contacts to n-type GaN

Schottky contacts were fabricated on n-type GaN using a Cu/Au metallization scheme, and the electrical and structural properties have been investigated as a function of annealing temperature by current-voltage (I-V), capacitance-voltage (C-V), Auger electron spectroscopy (AES) and X-ray diffraction (XRD) measurements. The extracted Schottky barrier height of the as-deposited contact was found to be 0.69 eV (I-V) and 0.77 eV (C-V), respectively. However, the Schottky barrier height of the Cu/Au contact slightly increases to 0.77 eV (I-V) and 1.18 eV (C-V) when the contact was annealed at 300 °C for 1 min. It is shown that the Schottky barrier height decreases to 0.73 eV (I-V) and 0.99 eV (C-V), 0.56 eV (I-V) and 0.87 eV (C-V) after annealing at 400 °C and 500 °C for 1 min in N₂ atmosphere. Norde method was also used to extract the barrier height of Cu/Au contacts and the values are 0.69 eV for the as-deposited, 0.76 eV at 300 °C, 0.71 eV at 400 °C and 0.56 eV at 500 °C which are in good agreement with those obtained by the I-V method. Based on Auger electron spectroscopy and X-ray diffraction results, the formation of nitride phases at the Cu/Au/n-GaN interface could be the reason for the degradation of Schottky barrier height upon annealing at 500 °C.     

On the profile of frequency and voltage dependent interface states and series resistance in (Ni/Au)/Al0.22Ga0.78N/AlN/GaN heterostructures by using current-voltage (I-V) and admittance spectroscopy methods

In order to explain the experimental effect of interface states (N_ss) and series resistance (R_s) of device on the non-ideal electrical characteristics, current-voltage (I-V), capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of (Ni/Au)/Al_0.22Ga_0.78N/AlN/GaN heterostructures were investigated at room temperature. Admittance measurements (C-V and G/ω-V) were carried out in frequency and bias voltage ranges of 2 kHz-2 MHz and (−5 V)-(+5 V), respectively. The voltage dependent R_s profile was determined from the I-V data. The increasing capacitance behavior with the decreasing frequency at low frequencies is a proof of the presence of interface states at metal/semiconductor (M/S) interface. At various bias voltages, the ac electrical conductivity (σ_ac) is independent from frequencies up to 100 kHz, and above this frequency value it increases with the increasing frequency for each bias voltage. In addition, the high-frequency capacitance (C_m) and conductance (G_m/ω) values measured under forward and reverse bias were corrected to minimize the effects of series resistance. The results indicate that the interfacial polarization can more easily occur at low frequencies. The distribution of N_ss and R_s is confirmed to have significant effect on non-ideal I-V, C-V and G/ω-V characteristics of (Ni/Au)/Al_0.22Ga_0.78N/AlN/GaN heterostructures.     

Characterization of current-voltage (I-V) and capacitance-voltage-frequency (C-V-f) features of Al/SiO2/p-Si (MIS) Schottky diodes

The current-voltage (I-V) characteristics of metal-insulator-semiconductor Al/SiO₂/p-Si (MIS) Schottky diodes were measured at room temperature (300 K). In addition, capacitance-voltage-frequency (C-V-f) characteristics are investigated by considering the interface states (N_ss) at frequency range 100 kHz to 1 MHz. The MIS Schottky diode having interfacial insulator layer thickness of 33 Å, calculated from the measurement of the insulator capacitance in the strong accumulation region. At each frequency, the measured capacitance decreases with increasing frequency due to a continuous distribution of the interface states. From the I-V characteristics of the MIS Schottky diode, ideality factor (n) and barrier height (Φ_b) values of 1.766 and 0.786 eV, respectively, were obtained from a forward bias I-V plot. In addition, the interface states distribution profile as a function of (E_ss − E_v) was extracted from the forward bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_e) for the Schottky diode. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer, the interface states and barrier inhomogeneity of the device. As expected, the C-V curves gave a barrier height value higher than those obtained from I-V measurements. This discrepancy is due to the different nature of the I-V and C-V measurement techniques.     

Stoichiometry-dependent deep levels in undoped p-type Al0.38Ga0.62As grown by liquid phase epitaxy

Photocapacitance (PHCAP) and photoluminescence (PL) measurements were applied to unintentionally doped p-type Al_0.38Ga_0.62As grown by liquid phase epitaxy using the temperature difference method under controlled vapor pressure. PHCAP spectra revealed three dominant deep levels at E_v+0.9, E_v + 1.45, and E_v+1.96 eV, and a deep level at E_v+0.9−1.5 eV which was not neutralized by forward bias injection. These level densities increase with increasing arsenic vapor pressure and net shallow acceptor density. Furthermore, PL spectra reveal a deep level at 1.6–1.7 eV. The PL intensity of this deep level increases with increasing arsenic vapor pressure. These deep levels are thought to be associated with excess As.     

Effect of series resistance on the electrical characteristics and interface state energy distributions of Sn/p-Si (MS) Schottky diodes

In this study, electrical characteristics of the Sn/p-type Si (MS) Schottky diodes have been investigated by current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height obtained from C-V measurement is higher than obtained from I-V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure Sn/p-Si interface. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (Φ_b) and the series resistance (R_S). The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions. In addition, the interface-state density (N_SS) as a function of energy distribution (E_SS-E_V) was extracted from the forward-bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_b) and series resistance (R_S) for the Schottky diodes. While the interface-state density (N_SS) calculated without taking into account series resistance (R_S) has increased exponentially with bias from 4.235 × 10¹² cm⁻²eV⁻¹ in (E_SS - 0.62) eV to 2.371 × 10¹³ cm⁻²eV⁻¹ in (E_SS - 0.39) eV of p-Si, the N_SS obtained taking into account the series resistance has increased exponentially with bias from of 4.235 × 10¹² to 1.671 × 10¹³ cm⁻²eV⁻¹ in the same interval. This behaviour is attributed to the passivation of the p-doped Si surface with the presence of thin interfacial insulator layer between the metal and semiconductor.     

On the profile of frequency dependent series resistance and dielectric constant in MIS structure

In this study, the frequency dependent of the forward and reverse bias capacitance-voltage (C-V) and conductance-voltage (G/ω - V) measurements of Al/SiO₂/p-Si (MIS) structures are carried out in frequency range of 10 kHz-10 MHz. The frequency dependence of series resistance (R_s), density of surface states (N_ss), dielectric constant (ε′), dielectric loss (ε″), dielectric loss tangent (tan δ) and the ac electrical conductivity (σ_dc) are studied for these structure at room temperature. Experimental results show that both electrical and dielectric parameters were strongly frequency and voltage dependent. The ε′ and ε″ are found to decrease with increasing frequency while σ_ac is increased. Also, both the effects of surface states N_ss and R_s on C-V and G/ω - V characteristics are investigated. It has been seen that the measured C and G decrease with increasing frequency due to a continuous distribution of N_ss in frequency range of 10 kHz-1 MHz. The effect of R_s on the C and G are found noticeable at high frequencies. Therefore, the high frequencies C and G values measured under both reverse and forward bias were corrected for the effect of series resistance R_s to obtain real MIS capacitance C_c and conductance G_c using the Nicollian and Goetzberger technique. The distribution profile of R_s-V gives a peak in the depletion region at low frequencies and disappears with increasing frequencies.     

Similarities of lag phenomena and current collapse in field-plate AlGaN/GaN HEMTs with different types of buffer layers

We make a two-dimensional transient analysis of field-plate AlGaN/GaN high electron mobility transistors (HEMTs) with a Fe-doped semi-insulating buffer layer, which is modeled that as deep levels, only a deep acceptor located above the midgap is included (E_C − E_DA = 0.5 eV, E_C: energy level at the bottom of conduction band, E_DA: deep acceptor's energy level). And the results are compared with a case having an undoped semi-insulating buffer layer in which a deep donor above the midgap (E_C − E_DD = 0.5 eV. E_DD: the deep donor's energy level) is considered to compensate a deep acceptor below the midgap (E_DA − E_V = 0.6 eV, E_V: energy level at the top of valence band). It is shown that the drain-current responses when the drain voltage is lowered abruptly are reproduced quite similarly between the two cases with different types of buffer layers, although the time region where the slow current transients occur is a little different. The lags and current collapse are reduced by introducing a field plate. This reduction in lags and current collapse occurs because the deep acceptor's electron trapping is reduced under the gate region in the buffer layer. The dependence of drain lag, gate lag and current collapse on the field-plate length and the SiN layer thickness is also studied, indicating that the rates of drain lag, gate lag and current collapse are quantitatively quite similar between the two cases with different types of buffer layers when the deep-acceptor densities are the same.     

On the profile of temperature dependent series resistance in Al/Si3N4/p-Si (MIS) Schottky diodes

The temperature dependence of capacitance-voltage (C-V) and conductance-voltage (G/w-V) characteristics of metal-insulator-semiconductor (Al/Si₃N₄/p-Si) Schottky barrier diodes (SBDs) was investigated by considering series resistance effect in the temperature range of 80-300 K. It is found that in the presence of series resistance, the forward bias C-V plots exhibit a peak, and experimentally show that the peak positions with a maximum at 260 K shift toward lower voltages with increasing temperature. The C-V and (G/w-V) characteristics confirm that the interface state density (N_ss) and series resistance (R_s) of the diode are important parameters that strongly influence the electric parameters of MIS structures. The crossing of the G/w-V curves appears as an abnormality compared to the conventional behavior of ideal Schottky diode. It is thought that the presence of series resistance keeps this intersection hidden and unobservable in homogeneous Schottky diodes, but it appears in the case of inhomogeneous Schottky diode. In addition, the high frequency (C_m) and conductance (G_m/w) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance.     

The interface states analysis of the MIS structure as a function of frequency

The energy distribution of interface states (N_ss) and their relaxation time (τ) were of the fabricated the Al/SiO₂/p-Si (MIS) structures were calculated using the forward bias current-voltage (I-V), capacitance-frequency (C-f) and conductance-frequency (G-f) measurements. Typical ln[I/(1 − exp(−qV/kT)] versus V characteristics of MIS structure under forward bias show one linear region. From this region, the slope and the intercept of this plot on the current axis allow to determine the ideality factor (n), the barrier height (Φ_b) and the saturation current (I_S) evaluated to 1.32, 0.77 eV and 3.05 × 10⁻⁹ A, respectively. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer at metal-semiconductor interface, the interface states and barrier inhomogeneity of the device. The energy distribution of interface states (N_ss) and their relaxation time (τ) have been determined in the energy range from (0.37 − E_v) to (0.57 − E_v) eV. It has been seen that the N_ss has almost an exponential rise with bias from the mid gap toward the top of valance band. In contrary to the N_ss, the relaxation time (τ) shows a slow exponential rise with bias from the top of the E_v towards the mid gap energy of semiconductor. The values of N_ss and τ change from 6.91 × 10¹³ to 9.92 × 10¹³ eV⁻¹ cm⁻² and 6.31 × 10⁻⁴ to 0.63 × 10⁻⁴ s, respectively.     

Temperature dependent electrical and dielectric properties of Sn/p-Si metal-semiconductor (MS) structures

In this study, we investigated temperature dependent electrical and dielectric properties of the Sn/p-Si metal-semiconductor (MS) structures using capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics in the temperature range 80-400 K. The dielectric constant (ε′), dielectric loss (ε′′), dielectric loss tangent (tan δ) and ac electrical conductivity (σ_ac) were calculated from the C-V and G/ω-V measurements and plotted as a function of temperature. The values of the ε′, ε′′, tan δ and σ_ac at low temperature (=80 K) were found to be 0.57, 0.37, 0.56 and 1.04 × 10⁻⁷, where as the values of the ε′, ε′′, tan δ and σ_ac at high temperature (=400 K) were found to be 0.75, 0.44, 0.59 and 1.21 × 10⁻⁶, respectively. An increase in the values of the ε′, ε′′, tan δ and σ_ac where observed with increase in temperature. Furthermore, the effects of interface state density (N_SS) and series resistance (R_S) on C-V characteristics were investigated in the wide temperature range.     

Organic nonvolatile memory transistors based on fullerene and an electron-trapping polymer

We report for the first time organic n-type nonvolatile memory transistors based on a fullerene (C₆₀) semiconductor and an electron-trapping polymer, poly(perfluoroalkenyl vinyl ether) (CYTOP). The transistors with a Si++/SiO₂/CYTOP/C₆₀/Al structure show good n-type transistor performance with a threshold voltage (V_th) of 2.8 V and an electron mobility of 0.4 cm² V⁻¹ s⁻¹. Applying gate voltages of 50 or −45 V for about 0.1 s to the devices induces the reversible shifts in their transfer characteristics, which results in a large memory window (ΔV_th) of 10 V. A memory on/off ratio of 10⁵ at a small reading voltage below 5 V and a retention time greater than 10⁵ s are achieved. The memory effect in the transistor is ascribed to electrons trapped at the CYTOP/SiO₂ interface. Because of the use of high-electron-mobility C₆₀, the switching voltages of our memory transistors become significantly lower than those of conventional memory transistors based on pentacene.     

The electrical characteristics of Sn/methyl-red/p-type Si/Al contacts

The junction characteristics of the organic compound methyl-red film (2-[4-(dimethylamino)phenylazo]benzoic acid) on a p-type Si substrate have been studied. The current-voltage characteristics of the device have rectifying behavior with a potential barrier formed at the interface. The barrier height and ideality factor values of 0.73 eV and 3.22 for the structure have been obtained from the forward bias current-voltage (I-V) characteristics. The interface state energy distribution and their relaxation time have ranged from 1.68 × 10¹² cm⁻² eV⁻¹ and 1.68 × 10⁻³ s in (0.73-E_v) eV to 1.80 × 10¹² cm⁻² eV⁻¹ and 5.29 × 10⁻⁵ s in (0.43-E_v) eV, respectively, from the forward bias capacitance-frequency and conductance-frequency characteristics. Furthermore, the relaxation time of the interface states shows an exponential rise with bias from (0.43-E_v) eV towards (0.73-E_v) eV.     

Laterally inhomogeneous barrier analysis of identically prepared Cd/CdS/n-Si/Au-Sb structures by SILAR method

In this study, CdS thin films have been deposited on n-Si substrate using a successive ionic layer adsorption and reaction (SILAR) method at room temperature. Structural properties have been investigated by means of X-ray diffraction (XRD) and scanning electron microscopy (SEM) measurements. The XRD and SEM investigations show that films are covered well, polycrystalline structure and good crystallinity levels. The Cd/CdS/n-Si/Au-Sb structures (28 dots) have been identically prepared by the SILAR method. The effective barrier heights and ideality factors of these structures have been obtained from forward bias current-voltage (I-V) and reverse bias capacitance voltage (C-V) characteristics. The barrier height (BH) for the Cd/CdS/n-Si/Au-Sb structure calculated from the I-V characteristics have ranged from 0.664 eV to 0.710 eV, and the ideality factor from 1.190 to 1.400. Lateral homogeneous barrier height has been determined approximately 0.719 eV from the experimental linear relationship between BHs and ideality factors. The experimental BH and ideality factor distributions obtained from the I-V characteristics have been fitted by a Gaussian function, and their means of values have been found to be (0.683 ± 0.01) eV and (1.287 ± 0.05), respectively. The barrier height values obtained from the reverse bias C⁻²-V characteristics have ranged from 0.720 eV to 0.865 eV and statistical analysis yields the mean (0.759 ± 0.02) eV. Additionally, a doping concentration obtained from C⁻²-V characteristics has been calculated (8.55 ± 1.62) × 10¹⁴ cm⁻³.     

Nonstoichiometric deep levels in Mg-doped GaP epitaxial layers

We have investigated the relation between deep levels in Mg-doped p-type GaP liquid phase epitaxy (LPE) layers and stoichiometry of the surface of the substrates by PHCAP measurement. Concentration of a deep donor level at E_C−1.9–2.1 eV is higher in an n-type undoped GaP substrate annealed with applying phosphorus vapor pressure of 20 kPa than in sample annealed beneath a carbon cover. Next, Mg-doped LPE layers are grown on substrates that have been pre-annealed under phosphorus vapor pressure just before the growth. The densities of deep levels at E_V+0.85 and E_V+1.5 eV in long-time (2 h) pre-annealing sample are greatly decreased, but a deep level at E_C−1.9–2.1 eV shows opposite tendency. The latter is thought to be identical to a deep level detected in the substrate, probably phosphorus interstitial atoms.     

Calculation from the current-voltage and capacitance-voltage measurements of characteristics parameters of Cd/CdS/n-Si/Au-Sb structure with CdS interface layer grown on n-Si substrate by SILAR method

The CdS thin film has been directly formed on n-type Si substrate to form an interfacial layer between cadmium (Cd) and n-type Si with Successive Ionic Layer Adsorption and Reaction (SILAR) method. An Au-Sb electrode has been used as an ohmic contact. The Cd/CdS/n-Si/Au-Sb structure has demonstrated clearly rectifying behaviour by the current-voltage (I-V) curves studied at room temperature. The characteristics parameters such as barrier height, ideality factor and series resistance of Cd/CdS/n-Si/Au-Sb structure have been calculated from the forward bias I-V and reverse bias C⁻²-V characteristics. The diode ideality factor and the barrier height have been calculated as n = 2.06 and Φ_b = 0.92 eV by applying a thermionic emission theory, respectively. The diode shows non-ideal I-V behaviour with an ideality factor greater than unity that can be ascribed to the interfacial layer, the interface states and the series resistance. At high current densities in the forward direction, the series resistance (R_s) effect has been observed. The values of R_s obtained from dV/d(lnI)-I and H(I)-I plots are near to each others (R_s = 182.24 Ω and R_s = 186.04 Ω, respectively). This case shows the consistency of the Cheung′s approach. In the same way, the barrier height calculated from C⁻² -V characteristics varied from 0.698 to 0.743 eV. Furthermore, the density distribution of interface states (N_ss) of the device has been obtained from the forward bias I-V characteristics. It has been seen that, the N_ss has almost an exponential rise with bias from the mid gap toward the bottom of conduction band.     

Defect-engineering in SiC by ion implantation and electron irradiation

Three examples are given, which show that ion implantation and electron irradiation can drastically modify the electrical properties of SiC and SiC-based MOS capacitors. (1) It is demonstrated that sulphur ions (S⁺) implanted into 6H-SiC act as double donors with ground states ranging from 310 to 635 meV below the conduction bandedge. (2) Co-implantation of nitrogen (N⁺) - and silicon (Si⁺) - ions into 4H-SiC leads to a strong deactivation of N donors. Additional experiments with electron (e⁻)-irradiated 4H-SiC samples (E(e⁻) = 200 keV) support the idea that this deactivation is due to the formation of an electrically neutral (N_x-V_C, y)-complex. (3) Implantation of a surface-near Gaussian profile into n-type 4H-SiC followed by a standard oxidation process leads to a strong reduction of the density of interface traps D_it close to the conduction bandedge in n-type 4H-SiC/SiO₂ MOS capacitors.     

Temperature and frequency dependent electrical and dielectric properties of Al/SiO2/p-Si (MOS) structure

The electrical and dielectric properties of Al/SiO₂/p-Si (MOS) structures were studied in the frequency range 10 kHz-10 MHz and in the temperature range 295-400 K. The interfacial oxide layer thickness of 320 Å between metal and semiconductor was calculated from the measurement of the oxide capacitance in the strong accumulation region. The frequency and temperature dependence of dielectric constant (ε′), dielectric loss (ε″), dielectric loss tangent (tan δ) and the ac electrical conductivity (σ_ac) are studied for Al/SiO₂/p-Si (MOS) structure. The electrical and dielectric properties of MOS structure were calculated from C-V and G-V measurements. Experimental results show that the ε′ and ε″ are found to decrease with increasing frequency while σ_ac is increased, and ε′, ε″, tan δ and σ_ac increase with increasing temperature. The values of ε′, ε″ and tan δ at 100 kHz were found to be 2.76, 0.17 and 0.06, respectively. The interfacial polarization can be more easily occurred at low frequencies, and the number of interface state density between Si/SiO₂ interface, consequently, contributes to the improvement of dielectric properties of Al/SiO₂/p-Si (MOS) structure. Also, the effects of interface state density (N_ss) and series resistance (R_s) of the sample on C-V characteristics are investigated. It was found that both capacitance C and conductance G were quite sensitive to temperature and frequency at relatively high temperatures and low frequencies, and the N_ss and R_s decreased with increasing temperature. This is behavior attributed to the thermal restructuring and reordering of the interface. The C-V and G/ω-V characteristics confirmed that the N_ss, R_s and thickness of insulator layer (δ) are important parameters that strongly influence both the electrical and dielectric parameters and conductivity in MOS structures.