Comparison of 3C–SiC, 6H–SiC and 4H–SiC MESFETs performances

A comparative analysis of the main DC and microwave performances of MESFETs made of the commercially available silicon carbide polytypes 3C–SiC, 6H–SiC and 4H–SiC is presented. In this purpose, we have developed an analytical model that takes into account the basic material properties such as field dependent mobility, critical electric field, ionization grade of impurities, and saturation of the charge carrier velocity. For a better precision in appreciating device characteristics in the case of a short gate device, the influences of the gate length and parasitic elements of the structure, e.g. source and drain resistances, are considered too. Cut-off frequency f_T, the corresponding output power P_m and the thermal stability are also evaluated and compared with the available experimental data, revealing the specific electrical performances of MESFETs, when any of the three polytypes is used in device fabrication.     

An Analytical Three-Region Two-Dimensional Model for SiGe MOSFETs Operating at Millimeter Wave Frequencies

An analytical two-dimensional model for an n-channel SiGe MOSFET is presented. In this paper a three-region model for SiGe is developed. The space charge region under the gate has been divided into three regions and the two-dimensional potential distribution is found by choosing appropriate boundary conditions for the drain, source and depletion regions. The analytical model predicts unity current-gain cut-off frequency (f _T ) of a 0.5 μm SiGe MOSFET to be over 18.6 GHz.     

Improved double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region

An improved double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region was proposed. The recessed source/drain drift region is to reduce channel thickness between gate and drain as well as eliminate gate depletion layer extension to source/drain. The recessed source/drain drift region of the proposed structure can be realized with the formation of double-recessed gate region. The simulated results showed that the breakdown voltage of the proposed structure is 145 V compared to 109 V of that of the published 4H-SiC MESFETs with double-recessed gate structure and yet maintain almost same saturation drain current characteristics. The output power density of the proposed structure is about 33% larger than that of the published double-recessed gate structure. The cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of the proposed structure are 21.8 GHz and 81.5 GHz compared to 19.0 GHz and 76.4 GHz of that of the published double-recessed gate structure, respectively.     

Compact analytical model for single gate AlInSb/InSb high electron mobility transistors

We have developed a 2D analytical model for the single gate Al In Sb/In Sb HEMT device by solving the Poisson equation using the parabolic approximation method.The developed model analyses the device performance by calculating the parameters such as surface potential,electric field distribution and drain current.The high mobility of the Al In Sb/In Sb quantum makes this HEMT ideal for high frequency,high power applications.The working of the single gate Al In Sb/In Sb HEMT device is studied by considering the variation of gate source voltage,drain source voltage,and channel length under the gate region and temperature.The carrier transport efficiency is improved by uniform electric field along the channel and the peak values near the source and drain regions.The results from the analytical model are compared with that of numerical simulations(TCAD) and a good agreement between them is achieved.     

An analytical threshold voltage and subthreshold current model forshort-channel MESFETs

Short-channel effects on the subthreshold behavior are modeled in self-aligned gate MESFETs with undoped substrates through an analytical solution of the two-dimensional Poisson equation in the subthreshold region. Based on the resultant potential solution, simple and accurate analytical expressions for short-channel threshold voltage, subthreshold swing, and subthreshold drain current are derived. These are then used to develop an expression for minimum acceptable channel length. A comparative study of the short-channel effects in MESFETs with doped and undoped substrates indicates that channel lengths will be limited to 0.15-0.2 μm by subthreshold conduction. Besides offering insight into the device physics of the short-channel effects in MESFETs, the model provides a useful basis for accurate analysis and simulation of small-geometry GaAs MESFET digital circuits     

Recessed p-buffer layer SiC MESFET: A novel device for improving DC and RF characteristics

This is the first report of novel structures designated as recessed p-buffer (RPB) silicon carbide (SiC) metal semiconductor field effect transistors (MESFETs). Important parameters such as gate–source capacitance, short channel effect, DC trans-conductance, cut-off frequency, DC output conductance, drain current and breakdown voltage of the two structures, the source side-recessed p-buffer (SS-RPB) and drain side-recessed p-buffer (DS-RPB), are simulated and compared with the conventional recessed gate SiC MESFET. Our simulation results describe that reducing the channel thickness under the gate at the source side of the SS-RPB structure, improves the gate–source capacitance, DC trans-conductance, and cut-off frequency compared with DS-RPB and conventional structures. Short channel effects for the SS-RPB structure are improved compared with that of the DS-RPB structure. Also, the SS-RPB structure has smaller DC output conductance in comparison with the conventional and DS-RPB structures. However, saturated drain current and breakdown voltage in the DS-RPB structure is larger than those in the conventional and SS-RPB structures.     

Gate field emission induced breakdown in power SiC MESFETs

The breakdown mechanism of SiC MESFETs has been analyzed by careful investigation of gate leakage current characteristics. It is proposed that gate current-induced avalanche breakdown, rather than drain avalanche breakdown, is the dominant failure mechanism for SiC MESFETs: thermionic-field emission and field emission are dominant for the ON state (above pinch-off voltage) and the OFF state (below pinch-off voltage), respectively. The effect of Si/sub 3/N/sub 4/ passivation on breakdown voltage has been also investigated. Si/sub 3/N/sub 4/ passivation decreases the breakdown voltage due to higher electric field at the gate edge compared to edge fields before passivation. A reduction in surface trapping effects after passivation results in the higher electric field because the depletion region formed by trapped electrons is reduced significantly.     

Fabrication and characterization of 4H-SiC planar MESFETs

The planar 4H-SiC MESFETs were fabricated by employing an ion-implantation process instead of a recess gate etching process, which is commonly adapted in compound semiconductor MESFETs, to eliminate potential damage to the gate region during etching process. Excellent ohmic and Schottky contact properties were achieved by using the modified RCA cleaning of 4H-SiC surface and the sacrificial thermal oxide layer. The fabricated MESFETs was also free from drain current instability, which the most of SiC MESFETs have been reported to suffer for the charge trapping. The drain current recovery characteristics were also improved by passivating the surface with a thermal oxide layer and eliminating the charge trapping at the surface. The performance of fabricated MESFETs was characterized by analyzing the small-signal equivalent circuit parameters extracted from the measured parameters.     

Characterization of SiC MESFETs with narrow channel layer

SiC MESFETs with a narrow channel layer are proposed to alleviate the short-channel effects, in particular the drain-induced barrier lowering (DIBL) effect that results in threshold voltage that is dependent on the gate length and the drain voltage applied. Such narrow channel layer 4H-SiC MESFETs were fabricated and characterized. The thickness and doping concentration of the channel layer are 0.08 μm and 8.0 × 10¹⁷ cm⁻³, respectively. The measurement results showed that the threshold voltage of the MESFETs is about −1.1 V and is independent of the gate length from 1 to 3 μm, and the drain voltage applied up to 40 V. Good saturation behavior with fairly low output conductance was also achieved, which is desirable for small signal applications. The results obtained for the narrow channel layer MESFETs are also compared with those measured for conventional devices with thicker channel layer of 0.20 μm and doping concentration of 2.5 × 10¹⁷ cm⁻³.     

Influence of Si<Subscript>3</Subscript>N<Subscript>4</Subscript> passivation on surface trapping in SiC metal-semiconductor field-effect transistors

The SiC metal-semiconductor field-effect transistors (MESFETs) have been reported to have current instability and strong dispersion caused by trapping phenomena at the surface and in the substrate, which degrade direct-current (DC) and radio-frequency (RF) performance. This paper illustrates the change in electrical characteristics of SiC MESFETs after Si₃N₄ passivation. Because of a reduction of surface trapping effects, Si₃N₄ passivation can diminish current collapse under pulsed DC conditions, increasing the RF power performance. The reduction of surface trapping effects is verified by the change in the ratio of the drain current to the gate current under pinch-off conditions.     

High-quality schottky and ohmic contacts in planar 4H-SiC metal semiconductor field-effect transistors and device performance

We have fabricated planar 4H-SiC, metal-semiconductor field-effect transistors (MESFETs) with high-quality metal/SiC contacts. To eliminate potential damage to the gate region caused by etching and simplify the device fabrication process, gate Schottky contacts were formed without any recess gate etching, and an ideality factor of 1.03 was obtained for these gate contacts. The interface state density between the contact metal and SiC was 5.7×10¹² cm⁻²eV⁻¹, which was found from the relationship between the barrier height and the metal work function. These results indicate that the interface was well controlled. Thus, a transconductance of 30 mS/mm was achieved with a 3-μm gate length as the performance figure of these MESFETs with high-quality metal/SiC contacts. Also, a low ohmic contact resistance of 1.2×10⁻⁶ Θcm² was obtained for the source and drain ohmic contacts by using ion implantation.     

S-band operation of SiC power MESFET with 20 W (4.4 W/mm) output power and 60% PAE

Previous efforts have revealed instabilities in standard SiC MESFET device electrical characteristics, which have been attributed to charged surface states. This work describes the use of an undoped "spacer" layer on top of a SiC MESFET to form a "buried-channel" structure where the active current carrying channel is removed from the surface. By using this approach, the induced surface traps are physically removed from the channel region, such that the depletion depth caused by the unneutralized surface states cannot reach the conductive channel. This results in minimal RF dispersion ("gate lag") and, thus, improved RF performance. Furthermore, the buried-channel approach provides for a relatively broad and uniform transconductance (G/sub m/) with gate bias (V/sub gs/), resulting in higher efficiency MESFETs with improved linearity and lower signal distortion. SiC MESFETs having 4.8-mm gate periphery were fabricated using this buried-channel structure and were measured to have an output power of 21 W (P/sub out//spl sim/4.4 W/mm), 62% power added efficiency, and 10.6 dB power gain at 3 GHz under pulse operation. When operated at continuous wave, similar 4.8-mm gate periphery SiC MESFETs produced 9.2 W output power (P/sub out//spl sim/2 W/mm), 40% PAE, and /spl sim/7 dB associated gain at 3 GHz.     

Gate-voltage dependence of source and drain series resistances andeffective gate length in GaAs MESFETs

Experimental data and calculated results are presented to show that the source and drain series resistances in GaAs MESFETs are gate-voltage dependent. This dependence is caused by the gate-voltage modulation of the ungated portions of the channel. A simple analytical model is proposed that accounts for this dependence by introducing an effective gate-voltage-dependent gate length. For nominal 1-μm gate devices the effective gate length is 0.2-0.3 μm longer than the metallurgical gate length     

Numerical analysis of the photoeffects in GaAs MESFET's

The photoeffects on the I-V characteristics of GaAs MESFETs have been studied by a two-dimensional numerical method. It is theoretically verified that the photovoltaic effect occurring at the channel/substrate interface is responsible for the substantial increase of the drain current. The reverse gate current due to illumination is caused by sweep-out by the high electrical field in the gate depletion region, where a large gradient in the depth profile of the hole Fermi energy is found. For devices with a lightly doped n-type buffer layer, the increase of the drain current is less than for devices without a buffer layer, but is still substantial     

Characterization of the frequency dispersion of transconductance and drain conductance of GaAs MESFET

Frequency dispersions of the transconductance and the drain conductance of ion-implanted gallium arsenide (GaAs) metal-semiconductor field-effect transistors (MESFETs) are measured and analyzed. In the linear region of the MESFET (low drain voltage), a positive transconductance dispersion is observed, which is caused by the deep-level traps at the surface between the source and the gate. In the saturation region (high drain voltage), however, a negative transconductance dispersion becomes dominant. The drain conductance does not show a dispersion in the linear region, while a distinct positive dispersion is observed in the saturation region with the same activation energy as the negative transconductance dispersion. The difference of the dispersion activation energy of the MESFET with and without the p-buried layer beneath the channel indicates that the negative transconductance and the drain conductance dispersion are caused by the deep-level traps at the channel-substrate interface. Because there exists the high electric field at the drain edge of the gate and an electron accumulation layer is formed, the potential in the channel becomes lower when the drain current is larger with high gate voltage. The emission of electrons from electron traps with lower potential is the cause of the negative frequency dispersion.     

Enhanced CAD model for gate leakage current in heterostructurefield effect transistors

A simple and accurate circuit model for Heterostructure Field Effect Transistors (HFETs) is proposed to simulate both the gate and the drain current characteristics accounting for hot-electron effects on gate current and the effect of the gate current on the channel current. An analytical equation that describes the effective electron temperature is developed in a simple form. This equation is suitable for implementation in circuit simulators. The model describes both the drain and gate currents at high gate bias voltages. It has been implemented in our circuit simulator AIM-Spice, and good agreement between simulated and measured results is achieved for enhancement-mode HFETs fabricated in different laboratories. The proposed equivalent circuit and model equations are applicable to other compound semiconductor FETs, i.e., GaAs MESFETs     

Gain improvement and microwave operation of 4H–SiC MESFET with a new recessed metal ring structure

A new multi-recessed 4H-SiC MESFET with recessed metal ring for RF embedded circuits is proposed (MR2-MESFET). The key idea in the proposed structure is based on the elimination of the spaces adjacent to gate and stopped the depletion region extending towards drain and source and the reduction of the channel thickness between gate and drain to increase breakdown voltage (V_BR); meanwhile the elimination of the gate depletion layer extension to source/drain to decrease gate-source capacitance (C_gs). The influence of multi-recessed drift region and recessed metal ring structures on the characteristics of the MR2-MESFET is studied by numerical simulation. The optimized results show that the V_BR of the MR2-MESFET is 119% larger than that of the conventional 4H–SiC MESFET (C-MESFET); meanwhile maintain 85% higher saturation drain current. Therefore, the maximum output power density of the MR2-MESFET is 23.1 W/mm compared to 5.5 W/mm of the C-MESFET. Also, the cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of 24.9 and 91.7 GHz are obtained for the MR2-MESFET compared to 11 and 40 GHz of the C-MESFET structure, respectively. The proposed MR2-MESFET shows a maximum stable gain (MSG) exceeding 23.6 dB at 3.1 GHz which is the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

Carrier transit delays in nanometer-scale GaAs MESFET's

MESFETs with gate lengths in the range of 40 to 300 nm with GaAs and AlGaAs buffer layers were characterized by high-frequency transit-time measurements. The total carrier transit time is interpreted as being composed of an intrinsic part, a drain delay, and a channel charging delay. The drain field's effect on the geometry of the gate depletion region, and the injection of carriers into the buffer layer are used to describe the origin of these delays and their limiting effect on the high-frequency performance of sub-0.1-μm gate-length MESFETs     

High-power-density 4H-SiC RF MOSFETs

The authors have made the first 4H-SiC RF power MOSFETs with cutoff frequency up to 12 GHz, delivering RF power of 1.9 W/mm at 3 GHz. The transistors withstand 200 V drain voltage, are normally off, and show no gate lag, which is often encountered in SiC MESFETs. The measured devices have a single drain finger and a double gate finger, and a total gate width of 0.8 mm. To their knowledge, this is the first time that power densities above 1 W/mm at 3 GHz are reported for SiC MOSFETs.