温度应力对MEMS器件分层失效的影响规律

通过分析MEMS器件多层结构界面裂纹疲劳扩展的影响因素及温度应力对界面疲劳的影响机理,建立了温度应力对分层失效影响的理论模型,并建立了双材料结构层的有限元分析模型,研究了温度应力对界面裂纹疲劳扩展的影响规律。研究结果表明:在温度应力作用下,裂纹易沿界面方向扩展;温度幅值升高,裂纹疲劳扩展速率呈指数关系增大;裂纹从形成初期到扩展至分层失效的过程中历经较慢扩展、相对平稳扩展和快速扩展三个阶段。     

温度应力对MEMS器件分层失效的影响规律

通过分析MEMS器件多层结构界面裂纹疲劳扩展的影响因素及温度应力对界面疲劳的影响机理,建立了温度应力对分层失效影响的理论模型,并建立了双材料结构层的有限元分析模型,研究了温度应力对界面裂纹疲劳扩展的影响规律。研究结果表明:在温度应力作用下,裂纹易沿界面方向扩展;温度幅值升高,裂纹疲劳扩展速率呈指数关系增大;裂纹从形成初期到扩展至分层失效的过程中历经较慢扩展、相对平稳扩展和快速扩展三个阶段。     

多层瓷介电容器失效模式和机理

系统介绍了开路、短路和电参数漂移这三种主要的MLCC失效模式,以及介质层内空洞和电极结瘤、介质层分层、热应力和机械应力引起介质层裂纹、其他微观机理等五种主要的失效机理。针对MLCC的失效分析技术,从生产工艺和使用设计上提出了预防MLCC失效的措施。     

单面蚀刻型埋容PCB开发

应埋容PCB市场需求,采用C-Ply埋容材料制作单面蚀刻型平板埋容PCB;根据埋容材料特性、埋容工艺特点进行理论研究和生产验证,重点研究埋容层菲林补偿、埋容层层间对准度、电容值精度、埋容层可靠性、超薄材料过水平线等;最终开发出单面蚀刻型平板埋容PCB产品,并具备批量生产能力。     

HDI板塞埋孔微裂纹研究和改善

文章在分析塞埋孔微裂纹机理的基础上系统研究了烘板工艺,半固化片树脂含量和不同塞埋孔树脂及塞埋孔前处理工艺等对塞埋孔微裂纹的影响,通过增加黑化前烘板流程、优先选择高树脂含量的半固化片、塞埋孔前采用棕化前处理并优先选择与半固化片Tg和Z-CTE一致性更好的树脂塞埋孔,实现了塞埋孔微裂纹的显著改善,并有效控制了HDI分层风险。     

封装基板阻焊层分层分析与研究

封装基板的可靠性对封装产品至关重要。通过对超薄层压基板封装产品的失效实例进行分析研究,确认由于基板阻焊层受应力造成阻焊层与铜层出现分层。经基板分层应力仿真模拟,发现阻焊层的厚度对阻焊层受到的应力影响最明显。增加阻焊层的厚度,可减小阻焊层与铜层之间的应力,解决阻焊层与铜层之间的分层问题,也提高了基板封装产品的可靠性。     

EMC材料特性对SCSP器件应力及层裂的影响

利用动态机械分析仪测定环氧模塑封(EMC)材料的粘弹特性数据,使用有限元软件MSCMarc分别模拟了EMC材料粘弹性、随温度变化的弹性以及恒弹性三种情况下,SCSP器件在–55～+125℃的等效应力分布及界面层裂。结果表明:125℃和–55℃时最大等效应力分别出现在恒弹性模型、粘弹性模型顶层芯片的悬置区域;将EMC材料视为恒弹性性质时等效应力比粘弹性时大了15.10MPa;–55℃时EMC材料粘弹性模型中裂纹尖端的J积分值比恒弹性模型增长了45%左右,容易引起分层裂纹扩展。     

二极管玻璃封装机械裂纹的产生原因和改良措施研究

在电子设备中广泛应用的玻封二极管属于机械应力敏感器件,异常的封装烧结工艺或过大的安装应力都可能导致玻壳发生开裂失效.通过对一例玻封二极管玻壳开裂失效的问题进行分析,发现杜美丝表面氧化层裂纹缺陷会导致玻壳烧结界面局部产生较大内应力,烧结后冷却速率过快,就会导致这些较大的内应力无法充分释放,产生残余应力,较大的残余应力会造...     

纳米尺度界面分层破坏行为的实验研究与分析

为系统研究纳米尺度材料中的界面分层破坏行为,基于悬臂梁弯曲法,利用聚焦离子束技术,从宏观多层薄膜材料(硅/铜/氮化硅,Si/Cu/SiN)中制备出了不同类型的(直、扭转)纳米悬臂梁试样,用以开展相应的实验研究。之后,在透射电子显微镜中分别对直纳米悬臂梁和扭转纳米悬臂梁试样进行原位加载实验。在直纳米悬臂梁试样中,Cu/Si界面受到由弯矩导致的拉应力而发生分层破坏;在扭转纳米悬臂梁试样中,通过改变加载点的位置调整界面上正应力与剪应力的比值,开展了不同复合型的界面裂纹启裂实验。利用有限元法分析了临界载荷作用下Cu/Si界面上的应力场,发现所有试样的应力集中区域均在距界面端部100 nm的范围内。在直纳米悬臂梁试样中,法向应力控制着Cu/Si界面端部的裂纹启裂行为,为单一型分层破坏;在扭转纳米悬臂梁试样中,界面裂纹启裂时的临界正应力与剪应力之间存在着一个圆形准则。     

埋置电容PCB工艺的开发和量产

根据客户埋置电容PCB量产需求,开发了A与B两种埋容材料的埋置电容工艺,分别为A单面蚀刻工艺与B双面蚀刻工艺。针对客户特殊设计的特殊要求,成功开发了0.1 mm激光通孔埋容板工艺。根据两种埋容材料的不同工艺,进行了理论研究和批量生产,重点研究了翘曲、板损、埋容精度控制、误差控制等问题,设计了埋容板插板架来解决阻焊油墨制作问题并推广。进行上述研究的同时,总结出适合我司的埋容工艺,形成埋容板生产控制文件,实现公司埋容板从试板向量产的飞跃,为公司提供了新的利润增长点。     

Reduction of crosstalk noise in modular jack for high-speeddifferential signal interconnection

Crosstalk noise has become a significant problem in the design of high-speed digital interconnections. In this paper, we demonstrate a crosstalk reduction method, which has been successfully applied to the design of a CAT-5E modular jack. The CAT-5E is a newly adopted cabling and connector standard for advanced cabling network systems to assure more robust, reliable and high-speed operation, which is based on differential mode signal transmission using unshielded twist pair (UTP) cable. The improved design of the modular jack shows minimal crosstalk noise and return loss over a wide range of manufacturing conditions. The improved crosstalk characteristics of the modular jack were accomplished by inserting embedded capacitors on the printed circuit board (PCB) of the modular jack. The embedded capacitors compensate for the unbalanced capacitive crosstalk that occurs in the plug and insert. In particular, the embedded balancing capacitor is designed to have maximum capacitance, with limited PCB area, by using a double-sided PCB design. Less than -45 dB near-end-crosstalk (NEXT) was achieved after the crosstalk noise compensation, satisfying the CAT-5E specification for frequencies up to 100 MHz     

Optimization of Epoxy-Barium Titanate Nanocomposites for High Performance Embedded Capacitor Components

One of the most promising avenues to meet the requirements of higher performance, lower cost, and smaller size in electronic systems is the embedded capacitor technology. Polymer-ceramic nanocomposites can combine the low cost, low temperature processability of polymers with the desirable electrical and dielectric properties of ceramic fillers, and have been identified as the major dielectric materials for embedded capacitors. However, the demanding requirements of mechanical properties and reliability of embedded capacitor components restrict the maximum applicable filler loading (<50vol%) of nanocomposites and thereby limit their highest dielectric constants (<50) for real applications. In this paper, we present a study on the optimization of the epoxy-barium titanate nanocomposites in order to obtain high performance, reliable embedded capacitor components. To improve the reliability of polymer-ceramic nanocomposites at a high filler loading, the epoxy matrix was modified with a secondary rubberized epoxy, which formed isolated flexible domains (island) in the continuous primary epoxy phase (sea). The effects of sea-island structure on the thermal mechanical properties, adhesion, and thermal stress reliability of embedded capacitors were systematically evaluated. The optimized, rubberized nanocomposite formulations had a high dielectric constant above 50 and successfully passed the stringent thermal stress reliability test. A high breakdown voltage of 89MV/m and a low leakage current of about 1.9times10^-11A/cm² were measured in the large area thin film capacitors     

环氧/BaTiO3复合物埋入电容膜和电容膏

概述了环氧/BaTiO3复合物埋入电容膜和电容膏的开发,它们适用于PCB之类的有机基材内制造具有高介质常数和低误差的埋入电容.     

印制电路板分层改善研究

随着欧盟RoHs法令从2006年7月开始实施,印制电路板装配不得不随之无铅化,传统已使用超过50年的63Sn／37Pb焊接材料被SnAgCu（Sn96．5％／Ag3．0％／Cu0．5％）代替,熔点由原来的187℃提升到217℃,相应的焊接温度由220℃。230℃提升到240℃。260℃,印制电路板必须经历熔点以上的焊接时间多出了50多秒,印制电路板吸收热大增,印制电路板必须提高耐热性能与之配合。在过去的一年中,印制电路板分层问题一直困扰着电路板制造商。 印制板分层的机理是电路板吸热后,不同材料之间产生不同的膨胀系数而形成内应力,如果树脂与树脂,树脂与铜箔的粘接力不足以抵抗这种内应力将产生分层,所以解决分层的思路是： 1．生产流程控制尽可能保证板子有最佳的抵抗内应力的能力; 2．使用性能优越的材料减少内应力。 丈章希望通过研究,在成本和品质双重约束下,找到最佳的解决方案,用最低的成本来解决分层问题。思路是从研究分层的原因着手,通过实验设计的方法,对分层的因素从材料选择、印制电路板制造过程控制到电路板装配的整个过程,进行系统分析。 本研究项目耗费25万元的试验材料成本,历时三个多月,最终从成本和品质控制,提升公司竞争力的角度,提出解决分层的三套方案。 在将实验结果运用到A公司的实践中后,产生了良好的经济效益,每月减少客诉成本约30万元,减少成本浪费约80万元,取得超过预期效益。     

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.     

有机基板中埋入无源元件概述

介绍了埋入无源元件在减小基板面积和提高基板高频特性的优点,总结了目前正在应用和研究的埋入电阻和埋入电容技术的实现方法.并提出基于埋入平面薄膜电阻和埋入薄芯介质材料形成平面电容技术的混合埋入技术将成为未来埋入无源元件PCB的主流技术.最后阐述了埋入无源元件技术在产业化过程中遇到的困难.     

Ultrahigh‐Working‐Frequency Embedded Supercapacitors with 1T Phase MoSe2 Nanosheets for System‐in‐Package Application

Commercial aluminium electrolyte capacitors (AECs) are too large for integration in future highly integrated electronic systems. Supercapacitors, in comparison, possess a much higher capacitance per unit volume and can be embedded as passive capacitors to address such challenges in electronics scaling. However, the slow frequency response (<10¹ Hz) typical of supercapacitors is a major hurdle to their practical application. Here, it is demonstrated that 1T‐phase MoSe₂ nanosheets obtained by laser‐induced phase transformation can be used as an electrode material in embedded micro‐supercapacitors. The metallic nature of MoSe₂ nanosheet‐based electrodes provides excellent electron‐ and ion‐transport properties, which leads to an unprecedented high‐frequency response (up to 10⁴ Hz) and cycle stability (up to 10⁶ cycles) when integrated in supercapacitors, and their power density can be ten times higher than that of commercial AECs. Furthermore, fabrication processes of the present device are fully compatible with system‐in‐package device manufacturing to meet stringent specifications for the size of embedded components. The present research represents a critical step forward in in‐package and on‐chip applications of electrolytic capacitors.     

激光重熔A356铝合金表面的力学性能

采用不同的激光功率在A356铝合金表面进行激光重熔试验,分析了重熔层的组织和显微硬度,并采用三点弯曲试验研究了重熔层的力学性能以及重熔层与基体的结合性能。结果表明:与基体相比,激光重熔层的硬度得到了大幅提升;重熔层中的细晶强化及第二相弥散强化提高了重熔层的强度,延缓了重熔层中第一裂纹的发生;重熔层与基板区域具良好的冶金结合能力,界面区域无裂缝;经激光重熔处理的试样表现出了良好的表面力学性能,在1500 W及2000 W激光功率下获得的重熔层与基体间未出现分层现象。     

High Density Double and Triple Layer Tantalum Pentoxide Decoupling Capacitors

High-performance integrated circuits (ICs) require extremely low impedance power distribution. The low voltage, high current requirements of these devices must be provided by decoupling capacitors very close to the IC. Currently this decoupling is provided by discrete surface mount capacitors with relatively high parasitic inductance, requiring many devices in parallel to provide low impedance at high frequencies. Thin film, large area tantalum pentoxide (TaO) dielectric capacitors exhibit very low parasitic inductance, but have been limited in capacitance density to 100nF/cm for single layer devices. Multilayer thin film capacitors can substantially increase the available capacitance. These multilayer thin film capacitors can be fabricated in a variety of ways, allowing them to be embedded between FR-4 layers, under ICs, or even embedded in IC packages. We previously described the initial results of two-layer capacitors fabricated on silicon . These devices had two dielectric layers and three copper plates. Recently we extended the technology to three dielectric layers, and fabricated devices with dielectrics as thin as 1000, to yield a total capacitance density of 0.6F/cm. Capacitors were fabricated on silicon wafers by sputtering a metal plate topped with tantalum, and then wet anodizing the tantalum layer. The process was repeated to create a multilayer stack. The stack was then patterned from top to bottom by successive lithographic and etching steps. This paper will describe the fabrication process in detail. Detailed electrical properties for the resulting two and three layer devices, such as capacitance density, leakage current, breakdown voltage, and impedance will be presented. Using the three-layer process, we fabricated devices for inclusion in a 3-D electronic assembly for a DARPA program, and these devices will be described. Screening and test methods to ensure device reliability will be briefly discussed.     

从日本专利看PCB基板材料制造技术的新发展之六——埋入电容基板用高ε覆铜板的技术进展

本连载文章,以近一两年发表的日本专利为对象,研究、综述了日本PCB基板材料业在制造技术上的新发展。本篇主要围绕着有关埋入电容基板用高ε覆铜板技术开发的主题。