印制电路板局部高密度互连的新方法

通过将PCB和高密度互连膜局部粘附到一起（LST－HDI－PCB），使得传统的印制电路板（PCB），如象陶瓷基板和环氧玻璃板，实现了局部高密度互连，这是解决印制电路板高密度互连（HDI－PCB）需求的一种新方法。这种概念可为传统的PCB任意区域提供HDI。在该技术中，使用了Cu/Pl(铜／聚酰亚胺）膜，可把Cu/PI膜层压到传统PCB上任意需要HDI的区域。按照这种新方法，使用批量生产线可同步制造传统的PCB和HDI－Cu/PI膜，其带来的成本优点胜过逐次组装的板子。目前我们开发的Cu/PI膜技术可在PI膜上沉积不同厚度的Cu层，而且没有针孔。这种技术特别适用于超细线和超细间距应用领域。此外，可对Cu/PI膜进行化学蚀刻及用激光打孔形成直径达50微米（micro)(2mil)的微孔，微孔和超细线及超细间距可实现超高密度的互连。在这种技术中，最细线和最线间距达10micro(0.4mil),使电路间距达到了20micro(0.8mil)。本讨论了完全用高I／O BGA、CSP及小型SMT器件组装的测试载体在开发研制过程中所遇到的问题和竞争的焦点以及该技术的发展现状。此外，还详细地论述了制造工艺和生产能力。     

面向当今封装的挠性印制电路板

挠性电路的特征适合于元件之间要求高密度互连的应用,其安装和连接的挠性特征,高密度电路的精确能力,耐热性能,电路终端选择的多样性以及材料和空间的有效使用等使挠性电路在当前和未来的封装应用中具有广阔的应用前景。     

印制电路板镀通孔制程可靠性问题与研究技术途径

影响镀通孔制程可靠性因素众多,关系复杂,需要一个有效的技术途径来研究该问题。文中总结了印制电路板镀通孔制程的各个加工步骤和工序的目的,以及制造过程中影响这些目的达成效果的影响因素。分析汇总了印制电路板镀通孔的各种失效模式和机理,及其对应的失效发生的部位和影响因素。在此基础上,明确了进行印制电路板镀通孔制程可靠性研究的技术途径,同时给出了实施这项研究的技术细节。     

高密度组装与印制电路板技术

半导体集成电路的出现将近有20年的历史了,在这期间一是努力谋求通过批量生产降低价格;二是提高集成度、提高性能,由中规模集成发展到大规模集成以至超大规模集成,在电子技术革新中经常起着主导作用。而另一方面,作为其配角的印制电路板(其出现早于集成电路)也出现了利用通孔镀铜法制造的两面     

高密度互连柔性电路板技术的发展

柔性电路板几乎用于每1类电器和电子产品中，而且是电子互连产品市场发展最快的产品之一，随着携带型电子产品小型化、轻量化及多功能化的发展，特别是半导体芯片的高集成化与高I／O数的迅速发展，柔性电路板技术向高密度即向精细导线／间距、微孔和精细窗口的方向发展。本从柔性电路板技术发展的驱动力、高密度柔性电路板基材、微孔制作技术以及覆盖层精细窗口制作技术等方面概述高密度柔性电路板的技术发展。     

高密度印制电路板（HDI）介绍

高密度印制电路板（HDI）介绍 印刷电路板是以绝缘材料辅以导体配线所形成的结构性元件。在制成最终产品时，其上会安装积体电路、电晶体、二极体、被动元件（如：电阻、电容、连接器等）及其他各种各样的电子零件。藉导线连通，可以形成电子讯号连结及应有机能。因此，印制电路板是一种提供元件连结的平台，用以承接联系零件的基的。     

高密度互连(HDI)电路板专利技术分析

本文从专利视角对高密度互连(HDI)电路板技术发展进行了统计分析,总结了关于高密度互连(HDI)电路板的专利申请量趋势、申请人地区分布等,并分析了高密度互连(HDI)电路板的技术发展.     

高密度互连电路板薄型化技术探讨

高密度互连电路板不断趋于薄型化。文章介绍了高密度互连电路板所用介质材料薄层化发展状态,并对薄型化加工中的关键技术问题进行了探讨。     

高密度多层印制电路板生产过程中的品质管理浅议

为了深入探讨高密度多层印制电路板生产过程中的品质管理,就如何提高过程质量控制手段,满足成品率稳步提升作了详尽的介绍。     

高频高密度互连刚挠结合板制作技术介绍

结合当今的电子产品发展方向,探索出一款12层,集合3阶HDI、高频板材、刚挠结合三种特性于一身的印制板的制作技术难点,并就问题点提出改善方法。     

Very high density interconnect elastomer chip sockets

The integration of more and more functionality into smaller and smaller form factor electronic products, drives the need for denser chip to substrate interconnect systems. As the number of I/O pins increases, the use of area array chips or packages becomes inevitable. Metal patterned elastomer chip sockets have now been improved to work with contact densities as high as 80 000 contacts/cm/sup 2/ corresponding to a pitch of 36 /spl mu/m. Sockets with 10 000 contacts and a 72-/spl mu/m pitch have survived more than 400 cycles in air-to-air thermal cycling chambers as well as freezing shocks caused by dipping into liquid nitrogen. Although the daisy chain test circuits breaks for temperatures lower than -50/spl deg/C and higher than 90/spl deg/C, they always return to the initial resistance values when entering the normal temperature range. The combination of a gold-to-gold contact interface and the elastic features of the contact bumps makes this socket an ideal compliance layer between bare chips and different types of carrier substrates, reducing the problems caused by thermomechanical mismatch between the substrate and the chip. Bad dies can easily be replaced, since the chip is not soldered or glued to the socket. The size and the possibility to control the geometry of the contacts provides means to maintain a good high-frequency characteristic impedance matching all the way to the chip pad.     

二阶HDI板工艺流程开发

主要讨论二阶HDI板的工艺开发流程,以实验的方式确定其关键制程的设置并对实验过程中遇到的一些问题进行讨论。     

Probabilistic prediction of wiring demand and routing requirementsfor high density interconnect substrates

Estimation of wiring and routability requirements for high density substrates is crucial for the development of new technologies, design, CAD tools, and optimization. This paper describes a new approach to wireability estimation that goes beyond Rent's rule. This approach depends on data flow and placement information available at early stages of the design process. Bus and random wiring are modeled explicitly. Excellent overall agreement is demonstrated between our predictions and published wiring data for two MCM systems. The relationship between placement and wireability will be presented through an optimization study by taking wiring parameters and their distributions as metrics. The application of this approach to the estimation of the required signal layers will be demonstrated     

一款任意层互连HDI板制作及流程管控

任意层互连板是印制板中制作难度大、工艺技术水平高的一种。文章选取一款用于移动通信智能终端的任意互连板,对其流程制作和品质管控做了初步阐释,希望能给业界同行提供一定的参考。     

Chemical and mechanical adhesion mechanisms of sputter-depositedmetal on epoxy dielectric for high density interconnect printed circuitboards

Strong chemical reactions between metal and polymer substrates significantly enhance adhesion of the metal to the polymer. This study investigated the adhesion of three types of thin film metals, including Cu, NiCr, and Cr, to a fully epoxy-based polymer. Before depositing these thin film metals, the epoxy surface was treated with either an Ar or O₂ plasma etch. It was found that NiCr and Cr produced higher peel strengths than Cu, but NiCr and Cr did not produce different peel strengths than each other. It was also found that O₂ plasma etch produced significantly higher peel strengths than Ar plasma etch for Cu and Cr, but not for NiCr. An XPS (X-ray photoelectron spectroscopy) study was performed to investigate the reactivities and possible chemical adhesion mechanisms of the metal thin films with the epoxy. It was determined that Cr reacted more strongly than Ni in forming metal oxide at the metal-epoxy interface. Cu was not seen to react strongly in forming oxide with the epoxy. Thermodynamic information supported the relative amounts of oxides found by XPS. Thermodynamic information also suggested that O₂ plasma etch did not produce significantly higher adhesion than Ar plasma etch on the NiCr samples due to the large Ni component of the NiCr thin film. An AFM (atomic force microscopy) study was performed to investigate possible mechanical adhesion mechanisms. Implications of the AFM results were that the main adhesion mechanism for all samples was chemical and that the Cu oxide that was available on the Cu samples was beyond the detection limits of the XPS equipment     

Cell-based interconnect migration by hierarchical optimization

Fueled by Moore's Law, VLSI market competition and economic considerations dictates the introduction of new processor's microarchitecture in a two-year cycle called “Tick-Tock” marketing strategy. A new processor is first manufactured in the most advanced stable process technology, followed in a one-year delay by introducing chips comprising same microarchitecture but manufactured in a newer scaled process technology, thus allowing higher production volumes, better performance and lower cost. Tick-Tock is enabled by the automation of chip's layout conversion from an older into a newer manufacturing process technology. This is a very challenging computational task, involving billions of polygons. We describe an algorithm of a hierarchy-driven optimization method for cell-based layout conversion used at Intel for already several product generations. It transforms the full conversion problem into successive problems of significantly smaller size, having feasible solutions if and only if the full-chip problem does. The proposed algorithm preserves the design intent, its uniformity and maintainability, a key for the success of large-scale projects.     

机器的设计过程

设计的过程是一个不断解决问题的过程,是一个项目管理的过程,是将不明了的问题转化为最终产品的过程。设计过程的成功与否决定了设计的价值,决定了最终产品的成本、质量和开发产品所需的时间。     

基于物联网技术的适老产品的设计研究与实践

在老龄化社会的今天,市场对适老产品和服务的需求巨大。适老产品和物联网技术进行整合会更加智慧及易用。信息社会使产品的内涵变得更加复杂,文章梳理出适合适老物联网技术产品研发的设计方法,并运用于指导实际的适老物联网产品开发。     

产品开发过程标准化对产品开发质量的影响

本文从产品开发的标准化的一些内容来探讨企业产品开发过程标准化对产品开发质量的影响.