数字视频转换编码技术

针对目前最流行的MPEG－2和MPEG－4两个压缩编码标准，就MPEG－2视频码流之间的转换编码、MPEG－2视频码流转换成MPEG－4码流以及MPEG－4视频码流之间的转换编码中的一些核心问题进行研讨。     

MPEG-2码流分析仪的整体设计与软件实现

首先对MPEG 2的码流结构和重要参数进行了描述。在此基础上,结合码流传输和解码的实际情况,对TS流的关键测试指标进行了探讨。其次,依据应用的需求,提出了MPEG 2码流分析仪的整体设计。最后,针对码流分析仪中的软件部分的实现做了详细论述。本文中的码流分析仪系统已经研制完成并且投入使用,实践证明,该系统是稳定可靠的,并且达到了各项指标要求。     

MPEG-2传输编解码器的DSP虚拟应用

MPEG－2视频编码广泛用于广播视频和HDTV。由于存储器和传输能力的限制,实际应用中,必须降低MPEG－2视频码流的比特率,因此,我们提出一种在DSP上实时实现的频域传输编解码技术（FDTC）,FDTC对存储器和复杂性要求较低,同时,低时延的码率控制技术提供了系统恒定比特率（CBR）的码流输出并且比级联的大容量MPEG－2视编解码器具有更好的峰值信噪比（PSNR）。     

适用于MPEG2 MP@ML标准的视频解码器设计

设计了一个适用于 MPEG2 MP@ML 标准的视频解码器结构 ,用 VHDL 语言进行了系统级的仿真和综合。系统工作时钟频率 40 MHz。用标准图象测试序列进行了验证 ,给出了测试结果和有关参数 ,满足 MPEG2 MP@ML 视频解码的实时处理要求。     

MPEG-2传输流中的时间信息与音视频同步

文中讨论了MPEG 2传输码流中的时间信息 (传输层中的节目参考时钟 ,PES层中的显示时间标签和节码时间标签 )在音视频同步中的作用。对理想解码器中的音频、视频同步原理作出了分析。指出了实际解码器实现视音频同步的困难之处并提出了解决办法。对实际解码中出现的视音频失同步的情况 ,通过对解码器的控制达到重复帧和丢帧的效果 ,从而重新实现了音、视频的同步。     

SGS-THOMSON公司交付第400万个MPEG解码器集成电路并且开始大量装运STI3520声频/视频解码器

SGS-THOMSON Microelec-tronics已销售400万个MPEG解码器集成电路,并且开始大量装运其最新产品:STI3520视频/声频MPEG-2解码器。 MPEG解码器集成电路在高性能多媒体个人计算机及给美国人带来几百万个数字电视频道的新一代消费产品中使用,并且可以把一     

桶形移位器在AVS熵解码器中的应用及仿真

AVS视频解码器作为一种媒体解码器,对实时性有较高的要求,这就要求解码器有较快的解码速度.针对这一技术需要,在AVS熵解码器的设计中,提出了一种用于码流截取的桶形移位器的设计方案.采用Verilog HDL语言进行设计和仿真,实现了码流的正确截取.本设计方案通过采用累加器和移位器的组合来实现数据传输,考虑了解码时延不同...     

MPEG—2视频业务的两种自回归模型的对比

为了实现多媒体节目流在IP网上的实时播放,因特网工程任务组（IETF）为MPEG－2码流的分割及实时传输制定了相关的协议。根据此协议对MOPEG VBR码流进行分割后,MPEG的三种类型型帧的自相关结构都表现出短时相关性,因此,采用AR（2）模型对三种类型的帧的大小进行了模拟,并且与AR（1）模型进行了对比。结果表明,AR（2）比AR（1）模型能够更好地反映视频源的统计特性。     

高清晰度电视芯片中视频和音频同步的异步实现

高清晰度电视的传输流采用了MPEG－2系统层标准ISO／IEC 13818－1。阐述了高清晰度电视（HDTV）传送流中时间信息码在视频和音频同步中的作用，分析了信源解码器中视频和音频同步的原理。就实际芯片中系统时钟的恢复，视频和音频的跳帧等机制进行了讨论，并提出了一种非锁相异步全数字视音同步实现方案。该方案采用了直接置数法恢复系统时钟,滞后跳帧法实现视频与系统时钟的同步，数字锁相法控制音频与系统时钟同步，最后，对视频帧率和音频PCM时钟的偏差等问题作了进一步的探讨。     

高清晰度电视视频解码器码流分配电路实时实现技术

我国自行研制的第一代高清晰度电视功能样机视频编、解码器中,采用十字划分方案,以便使用标准清晰度电视视频编、解码芯片实现高清晰度电视视频编、解码器。文中在介绍高清晰度电视视频码流结构的基础上,提出了高清晰度电视视频解码器中码流分配电路的实现方法,并给出了实现结果。实验表明,使用该方法可以实现码流中头信息的修改、码字划分及不定长视频包的有序传输及控制。     

HDTV接收系统中视频解码的研究与实现

本文简要分析了HDTV接收系统中视频解码的特点与实现方法,介绍了一种HDTV视频解码器的硬件结构及其工作过程。重点讨论了该视频解码器的软件系统结构,主要模块的设计与实现。该视频解码器可对符合MPEG-2 MP@HL的视频流进行解码并兼容多种视频格式的输出。     

MPEG—2视频解码的VHDL描述与验证

本文提出一种MPEG－2视频解码的硬件结构,并采用VHDL进行了描述。辚实现MPEG－2视频时的实时解码,本文针对时序控制、变长码解码、反量化、TDCT、运动补偿和输入输出控制等各部分都提出了相应的性能的电路结构。验证和仿真的结果表明：本文的设计可以完成相应的功能,能被用于实现MPEG－2MP@ML的实时解码芯片。     

Application Specific Processor Design for H.264 Decoder with a Configurable Embedded Processor

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction‐level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.     

用于DVD的MPEG2实时解码器研制

MPEG2作为数字视频压缩技术的国际通用标准,其实时解码器在数字视频产品中有着广泛的应用。本文介绍了一种采用部分总线结构的,用于DVD的MPEG2实时解码器的设计及硬件实现,并对系统的特点和其中的几个关键问题作了详细的分析与讨论,最后给出了实验结果及分析。     

An architecture of entropy decoder,inverse quantiser and predictor for multi-standard video decoding

A VLSI architecture for entropy decoder, inverse quantiser and predictor is proposed in this article. This architecture is used for decoding video streams of three standards on a single chip, i.e. H.264/AVC, AVS (China National Audio Video coding Standard) and MPEG2. The proposed scheme is called MPMP (Macro-block-Parallel based Multilevel Pipeline), which is intended to improve the decoding performance to satisfy the real-time requirements while maintaining a reasonable area and power consumption. Several techniques, such as slice level pipeline, MB (Macro-Block) level pipeline, MB level parallel, etc., are adopted. Input and output buffers for the inverse quantiser and predictor are shared by the decoding engines for H.264, AVS and MPEG2, therefore effectively reducing the implementation overhead. Simulation shows that decoding process consumes 512, 435 and 438 clock cycles per MB in H.264, AVS and MPEG2, respectively. Owing to the proposed techniques, the video decoder can support H.264 HP (High Profile) 1920 × 1088@30fps (frame per second) streams, AVS JP (Jizhun Profile) 1920 × 1088@41fps streams and MPEG2 MP (Main Profile) 1920 × 1088@39fps streams when exploiting a 200 MHz working frequency.     

一种用于MPEG2解码芯片的高效内存存储结构

为了提高MPEG2解码芯片的内存带宽利用率,根据SDRAM的固有特征和MPEG2解码时对内存读取的特点,提出了一种新的内存存储结构。采用该方法,可以大大减少内存读写的冗余时间,从而满足MPEG2 MP@HL解码器的设计要求。与直接映射相比,文章提出的方法可以使行激活的次数至少减少82.6%,内存读写时间减少59%以上。     

Boxing clever [Toshiba's Unified Digital Architecture]

The author describes how Toshiba's Unified Digital Architecture will enable the convergence of home entertainment and computing. The viable convergence platform combines the simplicity and reliability of consumer electronic (CE) appliances with a PC-like open extensible architecture optimised for the demands of A/V processing. Toshiba, a leading player in the CE appliance, PC and semiconductor industries, has formulated a proposal for a generic development platform for future-proof CE appliances designed expressly to satisfy these convergence criteria. The company has called its proposal the Unified Digital Platform (UDP). The UDP is designed to support a minimum set of common hardware components, comprising a RISC-based CPU, an MPEG -2 video decoder, an audio decoder (MPEG, Dolby), a graphics engine, a video interface, an audio interface and a network interface. Additional hardware components can be introduced to meet specific application requirements. Central to the UDP design is a data bus, the MM-bus (multimedia bus), designed to support data transfers between the system hardware components at rates consistent with the requirements of real-time A/V applications     

A video DSP with a macroblock-level-pipeline and a SIMD typevector-pipeline architecture for MPEG2 CODEC

A video DSP with macroblock-level-pipeline and a SIMD type vector-pipeline architecture (VDSP2) has been developed, using 0.5 μm triple-layer-metal CMOS technology. This 17.00 mm×15.00 mm chip consists of 2.5 M transistors, and operates at 100 MHz. The real-time encoder and decoder specified in the MPEG2 main profile at the main level can be realized with two VDSP2's and a motion estimation (ME) unit, and one VDSP2 respectively, at an 80 MHz clock rate, with a total power dissipation of 4.2 W at 3.3 V     

New architecture for MPEG video streaming system with backward playback support.

MPEG digital video is becoming ubiquitous for video storage and communications. It is often desirable to perform various video cassette recording (VCR) functions such as backward playback in MPEG videos. However, the predictive processing techniques employed in MPEG severely complicate the backward-play operation. A straightforward implementation of backward playback is to transmit and decode the whole group-of-picture (GOP), store all the decoded frames in the decoder buffer, and play the decoded frames in reverse order. This approach requires a significant buffer in the decoder, which depends on the GOP size, to store the decoded frames. This approach could not be possible in a severely constrained memory requirement. Another alternative is to decode the GOP up to the current frame to be displayed, and then go back to decode the GOP again up to the next frame to be displayed. This approach does not need the huge buffer, but requires much higher bandwidth of the network and complexity of the decoder. In this paper, we propose a macroblock-based algorithm for an efficient implementation of the MPEG video streaming system to provide backward playback over a network with the minimal requirements on the network bandwidth and the decoder complexity. The proposed algorithm classifies macroblocks in the requested frame into backward macroblocks (BMBs) and forward/backward macroblocks (FBMBs). Two macroblock-based techniques are used to manipulate different types of macroblocks in the compressed domain and the server then sends the processed macroblocks to the client machine. For BMBs, a VLC-domain technique is adopted to reduce the number of macroblocks that need to be decoded by the decoder and the number of bits that need to be sent over the network in the backward-play operation. We then propose a newly mixed VLC/DCT-domain technique to handle FBMBs in order to further reduce the computational complexity of the decoder. With these compressed-domain techniques, the proposed architecture only manipulates macroblocks either in the VLC domain or the quantized DCT domain resulting in low server complexity. Experimental results show that, as compared to the conventional system, the new streaming system reduces the required network bandwidth and the decoder complexity significantly.