IS-232电路中带自动关断的电荷泵优化设计

提出了一种用于RS-232电路中的升降压式的开关电容电荷泵,并阐述了电荷泵的工作原理,在减小功耗,使泵压稳定等方面对提高电荷泵的性能做了研究。该电荷泵通过检测输出电压来控制泵压,达到了稳压输出;同时,通过对RS-232电路的输入端进行监测来控制电荷泵的工作,大大降低了芯片功耗。最后,经过仿真对其性能进行了验证。     

RS-232电路中带自动关断的电荷泵优化设计

提出了一种用于RS-232电路中的升降压式的开关电容电荷泵,并阐述了电荷泵的工作原理,在减小功耗,使泵压稳定等方面对提高电荷泵的性能做了研究.该电荷泵通过检测输出电压来控制泵压,达到了稳压输出;同时,通过对RS-232电路的输入端进行监测来控制电荷泵的工作,大大降低了芯片功耗.最后,经过仿真对其性能进行了验证.     

液晶显示驱动电路中Fibonacci型电荷泵单元

本文中所设计的电荷泵将用于手机液晶显示驱动模块中.通过对Fibonacci型电荷泵上升时间的估算,对减小上升时间和动态功耗进行折中考虑,本文提出优化开关频率的方法.用1.2μm CMOS双阱工艺参数对所设计的电荷泵进行模拟,结果表明这个电荷泵具有较快的上升速度和较高的效率.通过提高V_GS电平和保证开关管的衬底始终接在最高电位上,文中提出了一种新型Fibonacci电荷泵,它可以正常工作在从1.2V到5V变化的多种电源电压下.     

一种用于LED驱动的高效电荷泵电路的设计

设计了一种用于LED驱动的高效1.33X/1.5X/2X电荷泵电路,可以根据输出电压的变化,自适应地切换工作模式。以提高电荷泵的转换效率为切入点,从降低电荷泵升压倍数和减小电荷泵自身功耗两个方面对电荷泵的效率进行了优化设计。从仿真与测试结果可以看出,1.33X模式的转换效率比传统的1.5X模式提高了10%左右,最高效率可达86%。     

低功耗电荷泵可编程增益放大器的设计与实现

提出了一种低功耗电荷泵可编程增益放大器(PGA)电路模型.通过简单数学建模和VerilogA仿真,得出了一般自动增益控制电路(AGC)优化稳定时间的条件和简化模型,通过ADC、电荷泵,进一步简化电路,降低功耗,并实现数字控制功能.根据这种设计,采用TSMC 0.18 μm CMOS 单层多晶硅6层金属工艺,实现了一个功耗电流为1 mA、线性增益范围为60 dB的电荷泵可编程增益放大器.     

一种用于LCD驱动的高效电荷泵的设计

电荷泵是一种流行的获取高于供电电源的直流电压转换技术.传统的电荷泵电路采用二极管连接的NMOS管级联来获取较高的电压,由于阈值电压的作用,这种电荷泵的提升效率会随着级数的增加而下降.为了提高效率,文中提出了一种提升5倍电压的采用液晶显示器(LCD)驱动的新型电荷泵结构.特别设计了开关管的栅控电路,消除了阈值电压对电压提升效率的影响,并且通过对开关管尺寸和控制时钟的进一步优化,提高了电压转换效率,降低了功耗,特别适合于小尺寸LCD驱动的需要.     

三阶电荷泵锁相环锁定时间的研究

对三阶电荷泵锁相环 ( CPPLL)的锁定时间与环路参数之间的关系进行了深入研究 ,提出了一种计算电荷泵锁相环锁定时间的新方法 ,并给出了锁定时间的计算公式。通过行为级模型验证 ,说明该公式可以快速准确地得到三阶电荷泵锁相环的锁定时间 ,并且很直观地反映出锁定时间与环路参数之间的关系。非常适合于电荷泵锁相环 ( CPPLL)的系统级设计和前期验证。     

基于CMOS工艺的622 MHz电荷泵锁相环设计

设计了由饱和区MOS电容调谐的环形压控振荡器(RVCO),并将其用于电荷泵锁相环(CPPLL)电路,其中电荷泵部分采用了能消除过冲注入电流的新型电荷泵电路,并采用SmartSpice软件和0.6μm混合信号的CMOS工艺参数进行了仿真。仿真结果表明,此锁相环的锁定时间为5.2μs,锁定范围约为100 MHz,输出中心频率622 MHz的最大周对周抖动为71ps,功耗为198 mW。此电荷泵锁相环电路可以应用于STM 1和STM 4两个速率级别的同步数字体系(SDH)系统。     

一种基于55nmCMOS工艺，输出频率0.1G-1.5G Hz的低抖动锁相环

本文设计了一种0.1G-1.5GHz,3.07pS RMS 抖动的多相位输出锁相环。通过引入双路径电荷泵,极大的减小了锁相环中的低通滤波器的尺寸。基于指定的功耗约束,提出了一种新颖的压控振荡器、电荷泵与鉴频鉴相器的尺寸优化方法,使用该方法,每个模块输出相位噪声减小了约3-6dBc/Hz。该锁相环在55nm的工艺下流片,集成了16pF的MOM电容,占用面积仅为0.05平方毫米。输出1.5GHz信号时,功耗2.8mW,相位噪声为-102dBc/Hz@1MHz。     

一种新型自平衡CPPLL电路结构及其应用

针对传统电荷泵电路中存在的电荷注入、电荷分享、时钟馈通等现象,对传统鉴频鉴相器和电荷泵进行了改进,提出了一种新型自平衡的CPPLL电路结构,并用于三角波振荡电路的设计.电路设计基于TSMC5V0.6μmBCD工艺,Spectre仿真结果显示,该电路能消弱电流失配、电荷注入、电荷分享等非理想特性,而且能产生稳定对称、频率宽范围(可达数GHz)可调的三角波输出信号,功耗1.4mW.     

On the design of power- and area-efficient Dickson charge pump circuits

This paper aims at investigating some methods for designing an area- and power-efficient Dickson charge pump circuit for on-chip high-voltage source generation. A comprehensive study on two conventional methods, with one of them based on optimizing the number of stage for minimum silicon area (minimum area method) and the other for maximum power efficiency (optimal power method), will be presented by considering both top- and bottom-plate parasitic capacitances. It was found that when the parasitic factors are as large as 0.1, the area and power efficiencies of the charge pumps designed with either the optimal power or minimum area method do not have much degradation. However, when the parasitic factors are small, charge pumps designed with the optimal power and minimum area methods can, respectively, result in a large area and poor power efficiency. The power efficiency of the charge pump designed with the minimum area method may be reduced by 50 %, while the area of the charge pump designed with the optimal power method can be 1–2 times larger, when the parasitic factors are 0.01. Hence, neither the optimal power nor minimum area methods should be used when the parasitic factors are small, unless the power or area is the only concern in the design. With this connection, the number of stage which leads to an area and power-efficient charge pump is suggested. Validity was proved by the good agreement between the simulated and the expected results for some designed charge pump circuits of the proposed design strategy.     

电压倍增之像素设计

为了节省面板电路驱动芯片的功率损耗以及制作成本,本研究提出一种新的像素电路设计,而在设计中将会融合电荷泵电路。利用这种电路设计的像素可有效地将像素电极上的驱动电压提高到输入电压的2～3倍以上。此像素电路设计具有两个优势:第一,可以有效降低显示面板的像素功率损耗;第二,不需高电压的面板电路驱动芯片,因此可节省芯片的成本及功率损耗。由模拟结果可知,像素电极上的驱动电压确实可由此像素电路设计而提高到输入电压的2～3倍以上;而像素的功率损耗也可有效地降低,约为传统像素的1/2。     

一种用于TDC的低功耗多相时钟生成电路北大核心

在无人机3D地形测绘中，作为核心模块的时间数字转换器(TDC)需要具有远距离测量能力和高测量分辨率。基于对测距系统的长续航、公里级测距能力和厘米级测量精度的综合考量，文章设计了一种用于TDC的低功耗多相位时钟生成电路。采用了伪差分环形压控振荡器，通过优化交叉耦合结构，在保证低功耗的前提下，提升了信号边缘的斜率，增强了时钟的抖动性能和对电源噪声的抑制能力。在电荷泵设计中，通过对环路带宽的考量选取了极低的偏置电流，在进一步降低功耗的同时缩小了环路滤波器的面积。基于SMIC 180 nm CMOS工艺完成了对多相时钟生成电路的设计。仿真结果表明，在400 MHz的输出频率下，环路带宽稳定在1 MHz。该电路在不同工艺角下均能达到较快的锁定速度，相位噪声为-88 dBc@1 MHz,功耗为1 mW,均方根抖动为27 ps,满足厘米级测距的精度需求。     

A dynamic analysis of the Dickson charge pump circuit

Dynamics of the Dickson charge pump circuit are analyzed. The analytical results enable the estimation of the rise time of the output voltage and that of the power consumption during boosting. By using this analysis, the optimum number of stages to minimize the rise time has been estimated as 1.4 N_min, where N_min is the minimum value of the number of stages necessary for a given parameter set of supply voltage, threshold voltage of transfer diodes, and boosted voltage. Moreover, the self-load capacitance of the charge pump, which should be charged up at the same time as the output load capacitance of the charge pump, has been estimated as about one-third of the total charge pump capacitance. As a result, the equivalent circuit of the charge pump has been modified. The analytical results are in good agreement with simulation by the iteration method, typically within 10% for the rise time and within 2% for the power consumption. In the case of a charge pump with MOS transfer transistors, the analytical results of the rise time agree with the SPICE simulation within 10%     

锁相环中基于电流控制技术的电荷泵的设计

锁相环能够跟踪输入信号的相位和频率,并输出相位锁定、低抖动的其他频率信号,广泛应用于通信系统中。高性能的锁相环芯片的设计,是当今通信领域研究的一个重点。文中对锁相环电路中的电荷泵电路模块进行改进,设计出一种带有电流控制技术的差分型电荷泵,实现了低功耗、高充放电速度的目的,并很好抑制电荷共享效应。同时通过电流模滤波器电路的设计,减小了整体电路的噪声,降低了功耗。     

一种改进输入时钟的EEPROM电荷泵设计

介绍了RFID无源电子标签中EEPROM的基本结构与工作原理。分析了NMOS管Dickson电荷泵及其由NMOS管构成的栅压自举电荷泵的特点与不足。针对当前电荷泵存在的电荷倒流、体效应问题,设计了一种改进输入时钟的电荷泵电路。通过对比仿真后发现,改进设计的电荷泵能减少电荷倒流、提高传输效率。已成功应用于RFID芯片的EEPROM中。     

Efficiency improvement in charge pump circuits

Conventional charge pump circuits use a fixed switching frequency that leads to power efficiency degradation for loading less than the rated loading. This paper proposes a level shifter design that also functions as a frequency converter to automatically vary the switching frequency of a dual charge pump circuit according to the loading. The switching frequency is designed to be 25 kHz with 12 mA loading on both inverting and noninverting outputs. The switching frequency is automatically reduced when loading is lighter to improve the power efficiency. The frequency tuning range of this circuit is designed to be from 100 Hz to 25 kHz. A start-up circuit is included to ensure proper pumping action and avoid latch-up during power-up. A slow turn-on, fast turn-off driving scheme is used in the clock buffer to reduce power dissipation. The new dual charge pump circuit was fabricated in a 3-μm p-well double-poly single-metal CMOS technology with breakdown voltage of 18 V, the die size is 4.7×4.5 mm². For comparison, a charge pump circuit with conventional level shifter and clock buffer was also fabricated. The measured results show that the new charge pump has two advantages: (1) the power dissipation of the charge pump is improved by a factor of 32 at no load and by 2% at rated loading of 500 Ω and (2) the breakdown voltage requirement is reduced from 19.2 to 17 V     

High efficiency all-PMOS charge pump for low-voltage operations

A high performance all-PMOS charge pump for low-voltage operations is proposed. According to the simulation results, the output voltage and power efficiency are improved by factors of 97 and 75.33% at 2 MHz for a power supply voltage of 1.5V, respectively, compared to conventional topology. A 12-stage charge pump circuit is implemented and measured to show good agreement.     

双模式高集成负电荷泵电路设计

提出了一种新颖的双模式高集成开关电容电荷泵。该电荷泵集成高频振荡器、电平移位、逻辑驱动以及4个功率MOSFET开关。与传统电荷泵相比,该电路可以工作在单电源以及双电源两种模式。单电源模式下,输出电压为-VCC;双电源模式下,输出电压为-3×VCC。电路采用0.35μm BCD工艺实现。测试结果表明:室温时,单电源模式和双电源模式下电荷泵输出电流分别为36 mA和80 mA时输出电压分别为-3.07 V和-12.10 V。在-55℃到125℃温度范围内,单电源模式和双电源模式下电荷泵输出电流分别为24 mA和50 mA时输出电压分别低于-3.06 V和-12.35 V。该电荷泵在两种模式下工作特性良好,已应用于相关工程项目。     

一种简单有效的电压泵闭环结构

介绍了一种根据标准ＣＭＯＳ ＥＥＰＲＯＭ工艺改进的简单有效的电压泵闭环结构，包括Ｄｉｃｋｓｏｎ电压泵，高频振荡器电路，编程脉冲波形控制电路等，阐述了电压泵各部分的工作原理以及开环结构以不足之处，电路模拟表明，此设计可以获得较好的结果。