Research on the contact resistance,reliability, and degradation mechanisms of anisotropically conductive film interconnection for flip-chip-on-flex applications

Although there have been many years of development, the degradation of the electrical performance of anisotropically conductive adhesive or film (ACA or ACF) interconnection for flip-chip assembly is still a critical drawback despite wide application. In-depth study about the reliability and degradation mechanism of ACF interconnection is necessary. In this paper, the initial contact resistance, electrical performance after reliability tests, and degradation mechanisms of ACF interconnection for flip-chip-on-flex (FCOF) assembly were studied using very-low-height Ni and Au-coated Ni-bumped chips. The combination of ACF and very-low-height bumped chips was considered because it has potential for very low cost and ultrafine pitch interconnection. Contact resistance changes were monitored during reliability tests, such as high humidity and temperature and thermal cycling. The high, initial contact resistance resulted from a thin oxide layer on the surface of the bumps. The reliability results showed that the degradation of electrical performance was mainly related to the oxide formation on the surface of deformed particles with non-noble metal coating, the severe metal oxidation on the conductive surface of bumps, and coefficient of thermal expansion (CTE) mismatch between the ACF adhesive and the contact conductive-surface metallization. Some methods for reducing initial contact resistance and improving ACF interconnection reliability were suggested. The suggestions include the removal of the oxide layer and an increase of the Au-coating film to improve conductive-surface quality, appropriate choice of conductive particle, and further development of better polymeric adhesives with low CTE and high electrical performance.     

Effects of different bonding parameters on the electrical performance and peeling strengths of ACF interconnection

The effects of different bonding parameters, such as temperature, pressure, curing time, bonding temperature ramp and post-processing, on the electrical performance and the adhesive strengths of anisotropic conductive film (ACF) interconnection are investigated. The test results show that the contact resistances change slightly, but the adhesive strengths increase with the bonding temperature increased. The curing time has great influence on the adhesive strength of ACF joints. The contact resistance and adhesive strength both are improved with the bonding pressure increased, but the adhesive strengths decrease if the bonding pressure is over 0.25 MPa. The optimum temperature, pressure, and curing time ranges for ACF bonding are concluded to be at 180–200 °C, 0.15–0.2 MPa, and 18–25 s, respectively. The effects of different Teflon thickness and post-processing on the contact resistance and adhesive strength of anisotropic conductive film (ACF) joints are studied. It is shown that the contact resistance and the adhesive strength both become deteriorated with the Teflon thickness increased. The tests of different post-processing conditions show that the specimens kept in 120 °C chamber for 30 min present the best performance of the ACF joints. The thermal cycling (−40 to 125 °C) and the high temperature/humidity (85 °C, 85% RH) aging test are conducted to evaluate the reliability of the specimens with different bonding parameters. It is shown that the high temperature/humidity is the worst condition to the ACF interconnection.     

A design tool to study the impact of mission-profile on the reliability of SiC-based PV-inverter devices

This paper introduces a reliability-oriented design tool for a new generation of grid connected PV-inverters. The proposed design tool consists of a real field mission profile model (for one year operation in USA-Arizona), a PV-panel model, a grid connected PV-inverter model, an electro-thermal model and the lifetime model of the power semiconductor devices. A simulation model able to consider one year real field operation conditions (solar irradiance and ambient temperature) is developed. Thus, one year estimation of the converter devices thermal loading distribution is achieved and is further used as an input to a lifetime model. The proposed reliability oriented design tool is used to study the impact of MP and device degradation (aging) in the PV-inverter lifetime. The obtained results indicate that the MP of the field where the PV-inverter is operating has an important impact in the converter lifetime expectation, and it should be considered in the design stage to better optimize the converter design margin. In order to improve the accuracy of the lifetime estimation it is crucial to consider also the device degradation feedback (in the simulation model) which has an impact of 30% in the precision of the lifetime estimation in the studied case.     

Effects of Cu and Pd addition on Au bonding wire/Al pad interfacial reactions and bond reliability

Finer pitch wire bonding technology has been needed since chips have more and finer pitch I/Os. However, finer Au wires are more prone to Au-Al bond reliability and wire sweeping problems when molded with epoxy molding compound. One of the solutions for solving these problems is to add special alloying elements to Au bonding wires. In this study, Cu and Pd were added to Au bonding wire as alloying elements. These alloyed Au bonding wires—Au-1 wt.% Cu wire and Au-1 wt.% Pd wire—were bonded on Al pads and then subsequently aged at 175°C and 200°C. Cu and Pd additions to Au bonding wire slowed down interfacial reactions and crack formation due to the formation of a Cu-rich layer and a Pd-rich layer at the interface. Wire pull testing (WPT) after thermal aging showed that Cu and Pd addition enhanced bond reliability, and Cu was more effective for improving bond reliability than Pd. In addition, comparison between the results of observation of interfacial reactions and WPT proved that crack formation was an important factor to evaluate bond reliability.     

光栅小角度变化引起的衍射光定位的变化及实验

本文通过对特定光栅作近似计算,推导出了光栅在小角度变化时,入射角和衍射角的改变量之间的对应关系,讨论了其实验的可行性和重要性.     

An investigation into the effects of probing and wire bonding stress on the reliability of BOAC

This work describes two types of low stress bonding over active circuit (BOAC) structures applying a finite element analysis. The advantage of improving the chip area utility of the BOAC design is approximately 150–180 μm for each dimension. A 0.13 μm 2 Mb high-speed SRAM with fluorinated silicate glass (FSG) low-k dielectric was combined with these two BOAC structures as the test vehicles to evaluate the impact of the probing and wire bonding stress on the reliability. Initially, a cantilevered probe card was applied to probe the BOAC pads using the typical and the worse probing conditions. Before and after the circuits probing (CP1 and CP2) the experimental results were compared, including the 2 Mb high-speed SRAM yield and wafer bit map data. The difference between the CP1 and CP2 results were negligible for all probing split cells. Next, the cross-section of the BOAC pad under the probing area was investigated following the worst probing condition. In addition, the BOAC pads evaluate the bondability, including the use of ball shear, wire pull and cratering tests. Moreover, all BOAC packaging samples underwent reliability tests, including HTOL, TCT, TST, and HTST. All the bondability and reliability tests passed the criteria for both proposed BOAC structures. Finally, the immunity level of both proposed BOAC pads, for ESD-HBM (human body mode) and ESD-MM (machine mode), differed slightly from the normal pads. No performance degradation was detected. Accordingly, this work shows that both proposed BOAC structures can be used to improve the active chip area utility or save the chip area.     

Numerical study of the effect of the doping profile on the threshold voltage of narrow-channel MOS transistor

A two-dimensional MOS process and device simulator, called IMPEDANCE, is used to study the influence of various doping profiles of stopper and channel implantations on the threshold voltage of narrow-channel MOS transistor (made with LOCOS isolation technology). For enhancement-mode transistors without channel implantation the lateral spread of the stopper implantation is the main factor for the threshold voltage increase with decreasing channel width. However the increase of the channel implantation dose reduces the dependence of the threshold voltage on the width especially at higher ion energies. In case of depletion-mode transistors the dependence of the threshold voltage on width is stronger owing to: (1) the existence of a lateral p-n junction between the channel and the stopper region and (2) the weaker gate control of the channel carriers.     

The effect of the elevated source/drain doping profile onperformance and reliability of deep submicron MOSFETs

Deep submicron NMOSFETs with elevated source/drain (ESD) were fabricated using self-aligned selective epitaxial deposition and engineered ion implanted profiles in the elevated layers, Deeper source/drain (S/D) junctions give rise to improved drive current over shallower profiles when the same spacer thickness and LDD doping level are used, Shallower junctions, especially with the heavily-doped S/D residing in the elevated layer, give better immunity to drain-induced-barrier lowering (DLBL) and bulk punchthrough. Tradeoffs between short-channel behavior and drive current with regard to S/D junction depth and spacer thickness were further studied using process/device simulations to cover a broader range of structure parameters. Despite the existence of epi facets along the sidewall spacers, the elevated S/D could be used as a sacrificial layer for silicidation, without degradation of the low-leakage junctions. The effects of the elevated S/D doping profile on substrate current and hot-electron-induced degradation were measured and analyzed. The simulated results were used, for the first time, to define the range of spacer thickness and LDD doses that are required in order for the lightly-doped region in the elevated S/D to effectively suppress the lateral electric field     

A study on the channel bonding in IoT networks: Requirements,applications, and challenges

The most well-known sort of remote Internet connection is wireless local area networks (WLANs) due to its unsophisticated operation and deployment. Subsequently, the quantity of gadgets getting to the Internet through WLANs, for example, PCs, cell phones, or wearables, is expanding radically at the equivalent time that applications' throughput necessities do. To provide wireless networks with supplementary spectral resources, the researchers are considering the aggregation of frequency spectrums in licensed, unlicensed, and shared access (SA) bands. Channel aggregation/channel bonding (CA/CB) techniques accumulate quite a few channels together as one channel for the purpose of achieving better bandwidth utilization. In this study, we focus on reliable CA/CB techniques in different wireless networks. CA/CB procedures are utilized for empowering higher information rates by transmitting in more extensive channels, accordingly expanding range proficiency with the assured secure channel for communication. We also discuss the spectral scarcity issues in today's wireless IoT network. This paper presents an extensive survey on CA/CB procedures and methods, issues and challenges, and open research areas related to IoT devices. We analyze the performance of channel CA/CB strategies in the different wireless networks too.     

The effect of reflow process on the contact resistance and reliability of anisotropic conductive film interconnection for flip chip on flex applications

The work presented in this paper focuses on the effect of reflow process on the contact resistance and reliability of anisotropic conductive film (ACF) interconnection. The contact resistance of ACF interconnection increases after reflow process due to the decrease in contact area of the conducting particles between the mating I/O pads. However, the relationship between the contact resistance and bonding parameters of the ACF interconnection with reflow treatment follows the similar trend to that of the as-bonded (i.e. without reflow) ACF interconnection. The contact resistance increases as the peak temperature of reflow profile increases. Nearly 40% of the joints were found to be open after reflow with 260 °C peak temperature. During the reflow process, the entrapped (between the chip and substrate) adhesive matrix tries to expand much more than the tiny conductive particles because of the higher coefficient of thermal expansion, the induced thermal stress will try to lift the bump from the pad and decrease the contact area of the conductive path and eventually, leading to a complete loss of electrical contact. In addition, the environmental effect on contact resistance such as high temperature/humidity aging test was also investigated. Compared with the ACF interconnections with Ni/Au bump, higher thermal stress in the Z-direction is accumulated in the ACF interconnections with Au bump during the reflow process owing to the higher bump height, thus greater loss of contact area between the particles and I/O pads leads to an increase of contact resistance and poorer reliability after reflow.     

A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections

Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.     

640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS,MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-μm CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160×114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-μm CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-Ω strip lines, high-speed signal lines, and 33 power supply layers formed using 50-μm thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80×120×20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection     

Numerical study on the injection performance of AlGaAs/GaAs abruptemitter heterojunction bipolar transistors

The injection performance of abrupt emitter HBT's and related effects on the device characteristics are studied by taking an Npn Al _0.25Ga_0.75As/GaAs/GaAs HBT as an example. In order to take into account the coupled transport phenomena of drift-diffusion and tunneling-emission processes across the abrupt heterojunction in a single coupled formulation, a numerical technique based on the boundary condition approach is employed. Compared to previous numerical investigations relying on either a drift-diffusion or a tunneling-emission scheme, more complete and accurate characterization of abrupt emitter HBT's has been achieved in this study. It is demonstrated that the presence of abrupt discontinuities of the conduction and valence bands at the emitter-base junction brings several different features to the injection efficiency and recombination characteristics of abrupt emitter HBT's compared to graded emitter HBT's. Based on investigations of the emitter doping effects on the current drive capability and device gain, an optimum emitter doping density is determined for a given structure. When the emitter-base p-n junction of the abrupt emitter HBT is slightly displaced with respect to the heterojunction, significant changes in the electrical characteristics are observed. A small displacement of the p-n junction into the narrow bandgap semiconductor is found to be very attractive for the performance optimization of abrupt emitter HBT's     

Wire bonding to advanced copper, low-K integrated circuits, the metal/dielectric stacks, and materials considerations

There are three areas to consider when designing/implementing wire bonding to advanced ULSI damascene-copper chips having copper metallization and low dielectric-constant polymers embedded beneath them (Cu/LoK). These are: 1) the copper-pad top-surface oxidation inhibitor coating - metal/organic/inorganic. (Current work involves evaluating the metal and inorganic options); 2) the low dielectric constant materials available; 3) under-pad metal/polymer stacks and support structures necessary for bondability and reliability. There are also various polymer/metallurgical interactions, resulting in long term packaged-device reliability problems, that can occur as the result of the wire bonding process over low modulus, LoK materials with barriers. These include cracked diffusion barriers, copper diffusion into the LoK polymers, cracking/spalling/crazing of the LoK materials, and bond pad indentation ("cupping"). Low-K polymer materials, with high expansion coefficients and low thermal conductivities, can also increase the stress and further extend any existing damage to barriers. Well designed LoK and the underpad structures should have no negative effect on bonding parameters and be invisible to the bonding process.     

A study on the performance and reliability of magnetostatic actuated RF MEMS switches

The magnetostatic radio frequency micro-electro-mechanical system switch is a special latching type of switch that possesses substantially high performance due to low loss, high linearity, and broad bandwidth. This new technology targets applications where high electrical performance and reliability are required in a harsh environment. A study on switch performance and reliability under different environmental conditions is crucial to its applications. In order to assess the reliability under desired environmental and operational conditions, comprehensive humidity and temperature reliability tests were conducted. The humidity test was conducted under high relative humidity and temperature cycling conditions. The thermal aging test was conducted at different temperature levels, which was used to study the fitness of lifetime distribution and validate the suitability of Arrhenius model that can be used for the lifetime prediction at normal operation temperature.     

二氧化硅与硅界面及其对能带轮廓及MOSFET栅遂穿电流影响的理论研究

利用第一原理对双键及桥氧两种二氧化硅与硅界面模型进行了理论研究。结果表明双键模型的界面转变区宽度较大。这种差别会导致MOSFET栅漏电的不同。遂穿电流的计算表明界面双键模型结构有较大的栅漏电。     

利用表面等离子体波共振效应(SPRE)对角度与共振波长关系的研究

本文利用了Kretchmann模型的表面等离子体波共振效应，研究了共振波长对入射角变化的敏感性，从而为研制一种新的角度传感器提供了依据。     

Theoretical study of the SiO2/Si interface and its effect on energy band profile and MOSFET gate tunneling current

Two SiO_2/Si interface structures,which are described by the double bonded model(DBM) and the bridge oxygen model(BOM),have been theoretically studied via first-principle calculations.First-principle simulations demonstrate that the width of the transition region for the interface structure described by DBM is larger than that for the interface structure described by BOM.Such a difference will result in a difference in the gate leakage current. Tunneling current calculation demonstrates that the SiO_2/Si...     

A comprehensive study of performance and reliability of P, As, andhybrid As/P nLDD junctions for deep-submicron CMOS logic technology

A comprehensive study of P, As, and hybrid As/P nLDD junctions is presented in terms of performance, reliability, and manufacturability for the first time. It is found that As junctions limit the performance of deep submicron devices due to unacceptable hot-carrier reliability, whereas a hybrid junction (light dose P added to medium dose As) dramatically improves hot-carrier reliability while maintaining high performance and manufacturability. For L_eff of 0.19 μm, using this hybrid junction in a manufacturing process, an inverter gate delay of 32 ps, dc hot carrier life time exceeding ten years, and off-state leakage below 30 pA/μm at 2.9 V have been achieved