A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching

This work describes a 10-b multibit-per-stage pipelined CMOS analog-to-digital converter (ADC) incorporating the merged-capacitor switching (MCS) technique. The proposed MCS technique improves the signal processing speed and resolution of the ADC by reducing the required number of unit capacitors by half in comparison to a conventional ADC. The ADC resolution based on the proposed MCS technique can be extended further by employing a commutated feedback-capacitor switching (CFCS) technique. The prototype ADC achieves better than 53-dB signal-to-noise-and-distortion ratio (SNDR) at 120 MSample/s and 54-dB SNDR and 68-dB spurious-free dynamic range (SFDR) for input frequencies up to Nyquist at 100 MSample/s. The measured differential and integral nonlinearities of the prototype are within /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25-/spl mu/m CMOS occupies 3.6 mm/sup 2/ of active die area and consumes 208 mW under a 2.5-V power supply.     

Digital background calibration of pipeline ADC based on correlation

Two novel calibration techniques based on dither injection and correlation are proposed. The first calibration algorithm utilises digital windows around the residue folding points by adding more comparators. Then all the capacitor mismatches and the linear gain error of the residue amplifier (RA) are calibrated by injecting dither signal in the windows. This new scheme would not change the key analogue signal path and thus brings no dither leakage in the digital domain. The other calibration algorithm injects dither signal into the split sampling capacitors to estimate the nonlinear kick-back error, which always exists in sample-hold amplifier less (SHA-less) structure. In addition, three other dither signals are injected into the added capacitors to calibrate the linear and nonlinear errors of the RA, which relaxes gain requirement in multiplying digtital-analogue-converter . Both the algorithms and the corresponding analogue-digital-converters (ADCs) are constructed and simulated in MATLAB. According to the simulation results, the first calibration technique increases signal-noise-distortion-ratio (SNDR) and spurious-free-dynamic-range (SFDR) by 40 and 42 dB, respectively. The second calibration scheme improves SNDR and SFDR by 19 and 34 dB in a SHA-less ADC.     

Improved low-distortion sigma-delta ADC with DWA for WLAN standards

An improved low distortion sigma-delta ADC (analog-to-digital converter) for wireless local area network standards is presented. A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted; however, this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR (signal to noise and distortion ratio), using 4-bit ADCs in both stages to minimize the quantization noise. Data weighted averaging technology is therefore used to decrease the mismatch noise induced by the 4-bit DACs, which improves the SFDR (spurious free dynamic range) of the ADC.The modulator has been implemented by a 0.18μm CMOS process and operates at a single 1.8 V supply voltage.Experimental results show that for a 1.25 MHz @ -6 dBFS input signal at 160 MHz sampling frequency, the improved ADC with all non-idealities considered achieves a peak SNDR of 80.9 dB and an SFDR of 87 dB, and the effective number of bits is 13.15 bits.     

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

A new power reduction technique for analog-to-digital converters (ADCs) is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-poly 7-metal CMOS technology. The 10-bit ADC dissipates 55 mW from 1.2-V supply, when the ADC operates at 200 mega-samples per second (MSPS). The 10-bit, 200-MSPS ADCs achieve maximum differential nonlinearity (DNL) of 0.66 least significant bit (LSB), maximum integral nonlinearity (INL) of 1.00 LSB, a spurious-free dynamic range (SFDR) of 66.5 dB and a peak signal-to-noise plus distortion ratio (SNDR) of 54.4 dB that corresponds to 8.7 effective number of bits (ENOB). The active area is 1.8 mm /spl times/ 1.4 mm.     

A CMOS switch-capacitor 14-bit 100 Msps pipeline ADC with over 90 dB SFDR

This article presents a design of 14-bit 100?Msamples/s pipelined analog-to-digital converter (ADC) implemented in 0.18?µm CMOS. A charge-sharing correction (CSC) is proposed to remove the input-dependent charge-injection, along with a floating-well bulk-driven technique, a fast-settling reference generator and a low-jitter clock circuit, guaranteeing the high dynamic performance of the ADC. A scheme of background calibration minimises the error due to the capacitor mismatch and opamp non-ideality, ensuring the overall linearity. The measured results show that the prototype ADC achieves spurious-free dynamic range (SFDR) of 91?dB, signal-to-noise-and-distortion ratio (SNDR) of 73.1?dB, differential nonlinearity (DNL) of +0.61/?0.57?LSB and integrated nonlinearity (INL) of +1.1/?1.0?LSB at 30?MHz input and maintains over 78?dB SFDR and 65?dB SNDR up to 425?MHz, consuming 223?mW totally.     

Digital background calibration of capacitor mismatches and harmonic distortion in pipelined ADC

A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.     

A 10-bit 2.5-MS/s SAR ADC with 60.46 dB SNDR in 0.13-μm CMOS technology

This paper presents a 10-bit 2.5-MS/s successive-approximation-register (SAR) analog- to-digital-converter (ADC) design for micro controller unit of signal process system. Because of the proposed new segmented architecture of 7 MSBs-plus-3 LSBs capacitor–resistor hybrid digital-to-analog-converter using a thermometer decoder for the most significant 5 MSBs, this design achieves superior static nonlinearity and dynamic performance of SNDR, SFDR. Utilizing the proposed deviation calibration technique, the discharging and charging via substrate resulting from deviation of the comparator’s common-mode voltage is cancelled. The ADC is fabricated in a standard 1P5M 0.13-μm CMOS technology. The peak DNL and INL are +0.18/?0.20-LSB, +0.30/?0.25 LSB respectively while the ENOB is 9.52-bit around all process–voltage–temperature corner analysis. At a 2.3-V supply voltage and a 2.5-MS/s sampling rate, the ADC achieves a SNDR of 60.46 dB, SFDR of 75.32 dB while the power dissipation is 0.191-mW, that resulting in a figure of merit of 98.45 fJ/c-s. The die of ADC measures 0.51 × 0.20 mm² resulting in area efficiency of 122.6 μm²/code and compared with the benchmark SAR ADCs, this work is the most area efficient design.     

1.8Vpp 250MS/s低谐波失真流水线ADC

采用40nm CMOS工艺设计了一款在250MS/s采样率下具有1.8Vpp满摆幅和低谐波失真性能的流水线ADC（Analog-to-Digital Converter）.针对传统源跟随器结构的输入缓冲器在大摆幅下驱动大采样电容时线性度恶化的问题,采用了改进型电流注入技术和漏端电压自举技术.ADC中实现采样和电荷转移功能的开关采用薄栅器件设计,其工作电压由片上LDO（Low Dropout Regulator）提供,在降低开关寄生和电荷注入的同时保障了器件的可靠性.测试结果表明,对于10.1MHz单音输入,该ADC在-1dBFS下的信噪失真比、无杂散动态范围和总谐波失真分别为68.3dB、76.4dBc、-75.1dBc,在-1.57dBFS下的信噪失真比、无杂散动态范围和总谐波失真分别达68.3dB、80.1dBc、-78.6dBc.     

A mismatch-error minimized four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC

This work proposes a four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC based on various analog techniques to minimize mismatches between channels without any calibration scheme. The proposed ADC eliminates an input SHA to reduce offset mismatches, while the pipelined SAR architecture solves the problem of limited input bandwidth as observed in conventional SHA-free ADCs. In addition, a shared residue amplifier between four channels minimizes various mismatches caused by amplifiers in the first-stage MDACs. Two types of references for the residue amplifier and the SAR ADCs isolate the reference instability problem due to different functional requirements, while the shared residue amplifier uses only a single reference during the amplifying mode of each channel to reduce a gain mismatch. For high performance of the SAR ADC, high-frequency clocks with a controllable duty cycle are generated on chip without external, complicated, high-speed multi-phase clocks. The prototype 11 b ADC in a 0.13 μm CMOS shows a measured DNL and INL of 0.31 LSB and 1.18 LSB, respectively, with an SNDR of 59.3 dB and an SFDR of 67.7 dB at 100 MS/s, and an SNDR of 54.5 dB and an SFDR of 65.5 dB at 150 MS/s. The ADC with an active die area of 2.42 mm² consumes 46.8 mW at 1.2 V and 150 MS/s.     

Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA

To reduce power dissipation, the input sample-and-hold amplifier (SHA) is eliminated in a pipelined analog-to-digital converter (ADC) with nested background calibration. The nested architecture calibrates the pipelined ADC with an algorithmic ADC that is also calibrated. Without an input SHA, a timing difference between the sampling instants of the two ADCs creates an error that interferes with calibration of the pipelined ADC. This problem is overcome with digital background timing compensation. It uses a differentiator with fixed coefficients to build an adaptive interpolator. With a 58-kHz sinusoidal input, the 12-bit 20-Msample/s pipelined ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.2 dB, a spurious-free dynamic range (SFDR) of 80.3 dB, and an integral nonlinearity (INL) of 0.75 least significant bit (LSB). With a 9-MHz input, the SNDR is 64.2 dB, and the SFDR is 78.3 dB. About 2 million samples or 0.1 s are required for convergence. The prototype occupies 7.5 mm² in 0.35-mum CMOS and dissipates 231 mW from 3.3 V, which is 23 mW less than in a previous prototype with the input SHA.     

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. An efficient common-mode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18-/spl mu/m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mm/sup 2/ of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100MS/s. For 99-MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8-V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline.     

一个高线性13位流水线CMOS A/D转换器

介绍了一个采用多种电路设计技术来实现高线性13位流水线A/D转换器.这些设计技术包括采用无源电容误差平均来校准电容失配误差、增益增强(gain-boosting)运放来降低有限增益误差和增益非线性,自举(bootstrapping)开关来减小开关导通电阻的非线性以及抗干扰设计来减弱来自数字供电的噪声.电路采用0.18μm CMOS工艺实现,包括焊盘在内的面积为3.2mm2.在2.5MHz采样时钟和2.4MHz输入信号下测试,得到的微分非线性为-0.18/0.15LSB,积分非线性为-0.35/0.5LSB,信号与噪声加失真比(SNDR)为75.7dB,无杂散动态范围(SFDR)为90.5dBc;在5MHz采样时钟和2.4MHz输入信号下测试,得到的SNDR和SFDR分别为73.7dB和83.9dBc.所有测试均在2.7V电源下进行,对应于采样率为2.5MS/s和5Ms/s的功耗(包括焊盘驱动电路)分别为21mW和34mW.     

一款结合数字校正技术的流水线ADC设计

基于65 nm CMOS工艺、1.2 V供电电压,设计了一款结合偏移双通道技术的流水线模数转换器(analog-to-digital convertor,ADC)。芯片的测试结果表明,该校正方法有效地消除和补偿了电容失配、级间增益误差和放大器谐波失真对流水线ADC综合性能的制约。流水线ADC在125 MS/s采样率、3 MHz正弦波输入信号的情况下,信噪失真比(signal-and-noise distortionratio,SNDR)从校正前的28 dB提高到61 dB,无杂散动态范围(spurious-free dynamic range,SFDR)从校正前的37 dB提高到62 dB。ADC芯片的功耗为72 mW,面积为1.56 mm2。偏移双通道数字校正技术在计算机软件上实现,数字电路在65 nm CMOS工艺、125 MHz时钟下估计得出的功耗为12 mW,面积为0.21 mm2。     

A background calibration in pipelined ADCs

In this paper, a novel background calibration is presented. The proposed scheme continuously measures and digitally compensates conversion errors caused by residue amplifier nonlinearity. This scheme can be used to relax analog circuit requirements for high-precision residue amplifier, accordingly decreasing the power consumption and/or increasing sampling rates in pipelined ADCs. The proposed scheme employs a fifth-order polynomial to eliminate conversion errors. One unique feature of the proposed scheme is that a single pseudorandom sequence, pn, is exploited. The simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion-ratio (SNDR) is improved from 40 to 66 dB and the spurious-free-dynamic-range (SFDR) is increased from 48 to 80 dB.     

A Filter Bank Mismatch Calibration Technique for Frequency-Interleaved ADCs

The filter bank mismatch of analog analysis filters in frequency-interleaved ADCs (FI-ADCs) degrades the system’s spurious-free dynamic range (SFDR) significantly. In this paper, a calibration approach for compensating such mismatch is presented. By modeling the parameter mismatches in the analysis filters, the filter bank mismatch compensation is divided into a coarse trimming mode and a fine-tuning mode. After the coarse trimming mode by trimming the resistors and capacitors in analog domain, the fine-tuning mode by updating coefficients of synthesis filters is further carried out in digital domain to achieve high-precision calibration. A design example of 10 GS/s 8-bit four-channel FI-ADC is built in MATLAB. The simulation results show that 25-tap synthesis filters could satisfy the reconstruction requirement of 8-bit ADC. The proposed calibration technique improves the SFDR to 51 dB, compensating the filter mismatch effectively.     

A digital processor for full calibration of pipelined ADCs

In this paper, a digital processor is presented for full calibration of pipeline ADCs. The main idea is to find an inverse model of ADC errors by using small number of the measured codes. This approach does not change internal parts of the ADC and most known errors are compensated simultaneously by digital post-processing of the output bits. Some function approximation algorithms are tested and their performances are evaluated. To verify the algorithms, a 12-bit pipelined ADC based on 1.5-bit per stage architecture is simulated with 1%-2% non-ideal factors in the SIMULINK with a 20 MHz sinusoidal input and a 100 MS/s sampling frequency. The selected algorithm has been implemented on a Virtex-4 LX25 FPGA from Xilinx. The designed processor improves the SNDR from 45 to 69 dB and increases the SFDR from 45.5 to 90 dB. The calibration processor also improves the integral nonlinearity of the ADC.     

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback

A new capacitor and opamp sharing technique that enables a very efficient low-power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back or memory effect in capacitors in the absence of a sample and hold is also presented. Fabricated in a 0.18 $mu{rm m}$ CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 ${rm mm}^{2}$ of active die area and achieves 66.7 dB SFDR and 53.2 dB SNDR when a 1 MHz input signal is digitized at 80 MS/s. The SFDR and SNDR are unchanged for a 50 MHz input signal. The prototype ADC consumes 36 mW at 1.8 V supply, of which the analog portion consumes 24 mW.      

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.     

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.     

22 μm-pitch 9-bit Column-Parallel Overlapping-Subrange SAR (CPOSSAR) ADC

The Column-Parallel Overlapping-Subrange Successive-Approximation-Register Analog-to-Digital Converter (CPOSSAR ADC) uses a 5-bit split capacitor DAC twice to achieve 9-bit resolution. Its total capacitor area is only 3% of a 9-bit binary weighted DAC and the average switching power is only 12% of a conventional 9-bit DAC. The ADC can perform a 9-bit conversion by first digitizing the 4 most significant bits (MSB) in a coarse conversion stage and then digitizing the 5 least significant bits (LSB) in a fine conversion stage. The accuracy requirement of the DAC is reduced by using overlapping subranges. The proposed ADC achieved an SFDR of 73.6 dB and a SINAD of 55 dB in post-layout simulation, corresponding to an ENOB of 8.8 bits. The design was fabricated in a TSMC׳s 0.35 μm high-voltage process. The use of overlapping subranges reduced the DNL error from +5.14/−1 LSB to +1.27/−0.92 LSB, and improved the INL error from +5.35/−5.34 LSB to +3.17/−3.18 LSB. At a sampling rate of 1.1 MS/s the ADC achieved 41.5 dB SFDR, 34.2 dB SINAD, and consumed 242 μW/channel dynamic power. An individual ADC channel is only 22 μm wide. COPSSAR ADCs are a factor of 4, 2, and 2.5 more area efficient than Multiple-ramp Single-slope ADCs, SAR ADCs, and Cyclic ADCs.