High-gain lateral bipolar action in a MOSFET structure

A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25-μm base width have been successfully fabricated in a p-well 0.25-μm bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported     

Heavy doping effects in p-n-p bipolar transistors

This paper presents the heavy doping effects on the injection current characteristics in p-n-p transistors with a heavily doped but thin base region. The results of the present study indicate that 1) at room temperature the hole current injected into heavily doped base is insensitive to the impurity compensation effect, 2) a linear relationship between the base sheet resistance and the collector-current density is observed when the base doping density is under 1 × 10¹⁹cm^-3. This relationship becomes supralinear as the doping density further increases. As a result, useful current gain exists in thin base transistors even when the base doping is greater than 1 × 10¹⁹cm^-3. From the collector-current-base sheet-resistance relationship and the base doping profile, the effective intrinsic carrier density as a function of the doping density is evaluated and found to increase 8.7 times over that of pure silicon, when the average doping density is 5 × 10¹⁹cm^-3(maximum doping density 1 × 10²⁰cm^-3). 3) The collector current and the current gain of the transistors become less sensitive to the temperature as the base doping density increases. We had observed a current gain up to 30 at 77 K for transistors with the maximum base doping density in the 10¹⁸cm^-3range. The transistors with lower base doping suffer much more degradation in current gain when the temperature is lowered to 77 K.     

Vertical p-n-p for complementary bipolar technology

A process to fabricate high-performance vertical p-n-p devices has been developed. The use of a high-dose boron-implanted poly-Si layer to form the emitter is essential to obtain shallow emitters with high emitter gradient. The devices exhibit very high current gain (>200) and a calculated cutoff frequency of 3.6 GHz. The process as developed is compatible with the n-p-n process and, thus, suitable for fabrication of complementary bipolar devices.     

p-n-p heterojunction bipolar transistors with buried subcollectorlayers

The buried-layer technology was applied to the fabrication of high-speed p-n-p AlGaAs/GaAs heterojunction bipolar transistors (HBTs). The subcollector layer was selectively implanted prior to the epitaxial growth of the rest of the device structure thereby eliminating the need for deep mesa isolation. Devices with 2×10-μm² emitter fingers and 100-nm base thickness had common-emitter current gains of 15 and cutoff frequencies of 17 GHz     

A fully planar p-n-p heterojunction bipolar transistor

The fabrication of fully planar p-i-n heterojunction bipolar transistors is reported. The devices were constructed using ion implantation into AlGaAs/GaAs heterostructures grown by metalorganic chemical vapor deposition (MOCVD). Incremental current gains of 100 have been observed for transistors with 22 μm×4 μm emitters, No emitter size effects was observed     

The performance potential of p-n-p heterojunction bipolar transistors

The performance of P-n-p AlGaAs/GaAs heterojunction microwave and switching transistors is compared to that of N-p-n structures. The maximum frequency of oscillation calculated for an optimized P-n-p microwave transistor is found to be only 29 percent less than that for an optimized N-p-n device. Similarly, the switching time of a P-n-p in a digital circuit is found to be only 28 percent greater than that of an N-p-n. These results are explained in terms of the parameters of a compact transistor model. The potential for use of the P-n-p HBT in microwave and switching applications is discussed in light of both performance and fabrication details.     

Thin-film lateral bipolar transistor in silicon-on-sapphire structure

Heteroepitaxial films of silicon-on-sapphire were used to fabricate lateral bipolar n-p-n transistors. The devices have a common-base direct-current amplification factor of 0.9 and a maximum frequency of oscillation of 2.4 GHz. As a result of the vertical p-n-junction arrangement, small junction areas are possible, e.g. 1×10?6cm2, which yield depletion-layer capacitances of 0.02?0.05 pF.     

High-gain 9.25 GHz silicon bipolar transistor power amplifier

A four-stage silicon bipolar transistor power amplifier operating at centre frequency 9.25 GHz is reported. The amplifier has output power exceeding 1.0 W over an instantaneous bandwidth of approximately 800 MHz. The power-added efficiency of the amplifier is measured to be better than 18%.     

A simple technique for improving lateral p-n-p transistor performance

Outlines a simple and elegant method that would simultaneously increase the current gain, frequency response, and voltage capability of the lateral p-n-p transistor. This is accomplished by introducing aluminium in the collector regions of the device.     

High-gain InGaAlAs/InGaAs heterojunction bipolar transistors andphototransistors

The characteristics of InGaAlAs/InGaAs heterojunction bipolar transistors (HBTs) grown by molecular beam epitaxy are described. A current gain of 15600 at a current density of ~10⁴ A/cm² and an emitter-base heterojunction ideality factor of 1.02 were measured. Appropriately designed InGaAlAs/InGaAs HBTs, when operated as phototransistors, also had high gains. A current gain of 1000 for a collector current of only 10 μA was obtained for phototransistors. Such high gains are due to low recombination currents as a consequence of the good crystalline quality of the InGaAlAs bulk and InGaAlAs/InGaAs interface     

High-gain bipolar transistors with polysilicon tunnel junction emitter contacts

Experimental measurements of the dc gain as a function of temperature and of emitter-base and collector-base current-voltage characteristics for bipolar transistors with polysilicon contacts to the emitter are reported, dc gains as high as 2000 have been measured in devices for which a thin insulating layer was encouraged to grow between the monocrystalline silicon emitter and the polycrystalline silicon contact layer. This gain is 20 times larger than that for devices in which the insulating film growth was inhibited. It is suggested that, for these particular devices, the polysilicon layer contributes to a contact which is very similar to that of a metal-insulator-semiconductor tunnel junction contact. A model based on this hypothesis is developed and shown to give a good fit to all the experimental data.     

High-performance p-n-p AlGaAs/GaAs heterojunction bipolar transistors: A theoretical analysis

The AlGaAs/GaAs P-n-p heterojunction bipolar transistor (HBT) is shown by a simple analysis to exhibit millimeter wave and digital switching performance comparable to similar N-p-n structures. For example, a P-n-p HBT with a 1-µm emitter stripe and 34-µm²total area yieldsf_{tau} = 31GHz,f_{max} = 94GHz, and an intrinsic switching speedtau_{s} = 8ps. A similar N-p-n structure exhibitsf_{tau} = 56GHz,f_{max} = 102GHz, andtau_{s} = 8ps.     

Device characteristics of the GaAs/InGaAsN/GaAs p-n-p doubleheterojunction bipolar transistor

We have demonstrated the dc and rf characteristics of a novel p-n-p GaAs/InGaAsN/GaAs double heterojunction bipolar transistor. This device has near ideal current-voltage (I-V) characteristics with a current gain greater than 45. The smaller bandgap energy of the InGaAsN base has led to a device turn-on voltage that is 0.27 V lower than in a comparable p-n-p AlGaAs/GaAs heterojunction bipolar transistor. This device has shown f_T and f_MAX values of 12 GHz. In addition, the aluminum-free emitter structure eliminates issues typically associated with AlGaAs     

A simple analytical model for estimating DC α of lateral p-n-p transistors

A quasi-one-dimensional model which can estimate dc α of lateral (p-n-p) transistors fairly accurately is proposed. Variation of α with epilayer thickness and electric field in the buried layer is investigated. Results obtained are in good agreement with the two-dimensional analysis.     

High-gain GaInP/GaAs heterojunction phototransistor utilising guard-ring structure

GaInP/GaAs heterojunction phototransistors with an emitter guard-ring contact are fabricated. The gain and speed of response of a device is significantly improved by the application of bias to the guard-ring, indicating that the recombination current is surface-dominated and that the quality of the GaInP/GaAs heterojunction interface is high.<>     

A column-base InP lateral bipolar transistor

An InP lateral bipolar transistor has been successfully fabricated on a semi-insulating substrate by implanting Si⁺ as the emitter and collector contacts and Mg⁺ as the column base. An array of 33 1-μm-diameter columns with 1-μm separation between each was formed between the emitter-collector spacing of 3 μm. A current gain of 290 was obtained at 77 K; it was over 12 at room temperature     

Current-gain enhancement in lateral p-n-p transistors by an optimized gap in the n+buried layer

A two-dimensional electrolytic tank analog study simulating volume recombination in the base region of lateral p-n-p transistors is presented. The effect of an n⁺buried layer is studied and it is found that a proper gap in this layer gives rise to a lateral transistor with common-emitter current-gain factor higher than that which can be achieved if the n⁺buried layer extends throughout the region below the transistor. This result is found to be true for various combinations of base geometry and minority carrier lifetimes which have been simulated. The analysis of the high-frequency performance shows that the gain-bandwidth product of the lateral p-n-p transistor is also maximized by providing an optimum gap in the buried layer.     

Performance of a CMOS compatible lateral bipolar photodetector onSOI substrate

The performance of a photodetector fabricated using a standard CMOS process on SOI substrate has been studied. The photodetector is basically a floating gate SOI NMOSFET operating in the lateral bipolar mode. The depletion region induced by the floating gate separates the optically generated electron-hole pairs in the direction perpendicular to the current. This results in an extra current amplification beyond that of a normal lateral bipolar transistor. A high responsivity of 289 A/W has been measured with an operating voltage as low as 0.1 V. The impacts of technology scaling on the performance of the photodetector are also studied     

A lateral silicon-on-insulator bipolar transistor with a self-aligned base contact

A novel lateral bipolar transistor structure in silicon-on-insulator (SOI) is presented. The structure allows for a minimum geometry base width yet still provides for a metal contact to the entire base region. Fabricated transistors exhibit a base resistance of less than 20 Ω.